| commit | 1954ff58264384de8241cc155ffe33829f0e616a | [log] [tgz] |
|---|---|---|
| author | Luis Vega <vegaluisjose@users.noreply.github.com> | Tue Jun 08 17:07:35 2021 -0700 |
| committer | GitHub <noreply@github.com> | Tue Jun 08 17:07:35 2021 -0700 |
| tree | 44eb07b749b53fbe7e0a0f70342b31d6bf1c0fd6 | |
| parent | d5e8117ce1535c527c536e115b4e58d53817b82f [diff] |
add unittest (#29)
diff --git a/tests/scripts/task_python_vta_tsim.sh b/tests/scripts/task_python_vta_tsim.sh index 0251915..ae9bedf 100755 --- a/tests/scripts/task_python_vta_tsim.sh +++ b/tests/scripts/task_python_vta_tsim.sh
@@ -49,6 +49,7 @@ # Build VTA chisel design and verilator simulator echo "Building VTA chisel design..." +make -C ${VTA_HW_PATH}/hardware/chisel unittest make -C ${VTA_HW_PATH}/hardware/chisel cleanall make -C ${VTA_HW_PATH}/hardware/chisel USE_THREADS=0 lib