commit	d5e8117ce1535c527c536e115b4e58d53817b82f	[log] [tgz]
author	Abhijit Davare <abhijit.davare@intel.com>	Mon Jun 07 18:26:41 2021 -0700
committer	GitHub <noreply@github.com>	Mon Jun 07 18:26:41 2021 -0700
tree	0f4ac9aaed6758f245d02abaf7adb56d02f6dfa5
parent	74f23fff285d4f57cad4afdb05e2bff08fd71f98 [diff]

Chisel Pipelined ALU (#27) * Remove parameter values from case class * Add new blockOutFactor parameter with default value = 1 * Support split access * Modify to support split interface, minor refactoring * Use split read/write intefaces * Pipelined ALU with split interfaces * Modify instantiation and usage of pipelined ALU and split interfaces * Don't use internal Random by default * Change tester name * Add generic tester class * Derive from GenericTest, minor refactoring * Test ALU index generator and pipelined ALU * Add ASF header * Bugfix: delay slicing index by a cycle to match SyncReadMem read delay * Formatting, comment, and minor refactoring changes for clarity * Fix scalastyle issues for test files

tree: 0f4ac9aaed6758f245d02abaf7adb56d02f6dfa5

README.md

VTA Hardware Design Stack

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

Generic, modular, open-source hardware
- Streamlined workflow to deploy to FPGAs.
- Simulator support to prototype compilation passes on regular workstations.
Driver and JIT runtime for both simulator and FPGA hardware back-end.
End-to-end TVM stack integration
- Direct optimization and deployment of models from deep learning frameworks via TVM.
- Customized and extensible TVM compiler back-end.
- Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.