commit 80f518a57bd9a1b59140d750413a7fb0c94a21a2
author Kevin Yuan <kevinyuan@users.noreply.github.com> Mon Jan 06 08:56:16 2020 +0800
committer Tianqi Chen <tqchen@users.noreply.github.com> Sun Jan 05 16:56:16 2020 -0800
tree 905bfd28658b6bd38c2685ebe466d4bfc0404dec
parent b693922332b43b931118c59f483c18dcaf365904

Added declare of aluBits for TensorAlu (#4624)

hardware/chisel/src/main/scala/core/TensorAlu.scala

diff --git a/hardware/chisel/src/main/scala/core/TensorAlu.scala b/hardware/chisel/src/main/scala/core/TensorAlu.scala
index 6f1a804..21e57f2 100644
--- a/hardware/chisel/src/main/scala/core/TensorAlu.scala
+++ b/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -108,6 +108,7 @@
   * acc-scratchpad.
   */
 class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
+  val aluBits = p(CoreKey).accBits
   val io = IO(new Bundle {
     val start = Input(Bool())
     val done = Output(Bool())