| # Licensed to the Apache Software Foundation (ASF) under one |
| # or more contributor license agreements. See the NOTICE file |
| # distributed with this work for additional information |
| # regarding copyright ownership. The ASF licenses this file |
| # to you under the Apache License, Version 2.0 (the |
| # "License"); you may not use this file except in compliance |
| # with the License. You may obtain a copy of the License at |
| # |
| # http://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, |
| # software distributed under the License is distributed on an |
| # "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY |
| # KIND, either express or implied. See the License for the |
| # specific language governing permissions and limitations |
| # under the License. |
| |
| package require -exact qsys 16.0 |
| |
| create_system soc_system |
| |
| set_project_property DEVICE [lindex $argv 0] |
| set_project_property DEVICE_FAMILY [lindex $argv 1] |
| |
| # module properties |
| set_module_property NAME soc_system |
| |
| # Instances and instance parameters |
| # (disabled instances are intentionally culled) |
| add_instance clk_0 clock_source 18.1 |
| set_instance_parameter_value clk_0 {clockFrequency} {50000000.0} |
| set_instance_parameter_value clk_0 {clockFrequencyKnown} {1} |
| set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE} |
| |
| add_instance hps_0 altera_hps 18.1 |
| set_instance_parameter_value hps_0 {HPS_PROTOCOL} {DDR3} |
| set_instance_parameter_value hps_0 {MEM_ASR} {Manual} |
| set_instance_parameter_value hps_0 {MEM_ATCL} {Disabled} |
| set_instance_parameter_value hps_0 {MEM_AUTO_LEVELING_MODE} {1} |
| set_instance_parameter_value hps_0 {MEM_BANKADDR_WIDTH} {3} |
| set_instance_parameter_value hps_0 {MEM_BL} {OTF} |
| set_instance_parameter_value hps_0 {MEM_BT} {Sequential} |
| set_instance_parameter_value hps_0 {MEM_CK_PHASE} {0.0} |
| set_instance_parameter_value hps_0 {MEM_CK_WIDTH} {1} |
| set_instance_parameter_value hps_0 {MEM_CLK_EN_WIDTH} {1} |
| set_instance_parameter_value hps_0 {MEM_CLK_FREQ} {400.0} |
| set_instance_parameter_value hps_0 {MEM_CLK_FREQ_MAX} {800.0} |
| set_instance_parameter_value hps_0 {MEM_COL_ADDR_WIDTH} {10} |
| set_instance_parameter_value hps_0 {MEM_CS_WIDTH} {1} |
| set_instance_parameter_value hps_0 {MEM_DEVICE} {MISSING_MODEL} |
| set_instance_parameter_value hps_0 {MEM_DLL_EN} {1} |
| set_instance_parameter_value hps_0 {MEM_DQ_PER_DQS} {8} |
| set_instance_parameter_value hps_0 {MEM_DQ_WIDTH} {32} |
| set_instance_parameter_value hps_0 {MEM_DRV_STR} {RZQ/6} |
| set_instance_parameter_value hps_0 {MEM_FORMAT} {DISCRETE} |
| set_instance_parameter_value hps_0 {MEM_GUARANTEED_WRITE_INIT} {0} |
| set_instance_parameter_value hps_0 {MEM_IF_BOARD_BASE_DELAY} {10} |
| set_instance_parameter_value hps_0 {MEM_IF_DM_PINS_EN} {1} |
| set_instance_parameter_value hps_0 {MEM_IF_DQSN_EN} {1} |
| set_instance_parameter_value hps_0 {MEM_IF_SIM_VALID_WINDOW} {0} |
| set_instance_parameter_value hps_0 {MEM_INIT_EN} {0} |
| set_instance_parameter_value hps_0 {MEM_INIT_FILE} {} |
| set_instance_parameter_value hps_0 {MEM_MIRROR_ADDRESSING} {0} |
| set_instance_parameter_value hps_0 {MEM_NUMBER_OF_DIMMS} {1} |
| set_instance_parameter_value hps_0 {MEM_NUMBER_OF_RANKS_PER_DEVICE} {1} |
| set_instance_parameter_value hps_0 {MEM_NUMBER_OF_RANKS_PER_DIMM} {1} |
| set_instance_parameter_value hps_0 {MEM_PD} {DLL off} |
| set_instance_parameter_value hps_0 {MEM_RANK_MULTIPLICATION_FACTOR} {1} |
| set_instance_parameter_value hps_0 {MEM_ROW_ADDR_WIDTH} {15} |
| set_instance_parameter_value hps_0 {MEM_RTT_NOM} {RZQ/6} |
| set_instance_parameter_value hps_0 {MEM_RTT_WR} {Dynamic ODT off} |
| set_instance_parameter_value hps_0 {MEM_SRT} {Normal} |
| set_instance_parameter_value hps_0 {MEM_TCL} {7} |
| set_instance_parameter_value hps_0 {MEM_TFAW_NS} {37.5} |
| set_instance_parameter_value hps_0 {MEM_TINIT_US} {500} |
| set_instance_parameter_value hps_0 {MEM_TMRD_CK} {4} |
| set_instance_parameter_value hps_0 {MEM_TRAS_NS} {35.0} |
| set_instance_parameter_value hps_0 {MEM_TRCD_NS} {13.75} |
| set_instance_parameter_value hps_0 {MEM_TREFI_US} {7.8} |
| set_instance_parameter_value hps_0 {MEM_TRFC_NS} {300.0} |
| set_instance_parameter_value hps_0 {MEM_TRP_NS} {13.75} |
| set_instance_parameter_value hps_0 {MEM_TRRD_NS} {7.5} |
| set_instance_parameter_value hps_0 {MEM_TRTP_NS} {7.5} |
| set_instance_parameter_value hps_0 {MEM_TWR_NS} {15.0} |
| set_instance_parameter_value hps_0 {MEM_TWTR} {4} |
| set_instance_parameter_value hps_0 {MEM_USER_LEVELING_MODE} {Leveling} |
| set_instance_parameter_value hps_0 {MEM_VENDOR} {Other} |
| set_instance_parameter_value hps_0 {MEM_VERBOSE} {1} |
| set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3} |
| set_instance_parameter_value hps_0 {MEM_WTCL} {7} |
| set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0} |
| set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0} |
| set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0} |
| set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0} |
| set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0} |
| set_instance_parameter_value hps_0 {LWH2F_Enable} {true} |
| set_instance_parameter_value hps_0 {S2F_Width} {0} |
| set_instance_parameter_value hps_0 {F2SDRAM_Type} {} |
| set_instance_parameter_value hps_0 {F2SDRAM_Width} {} |
| set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0} |
| |
| add_instance vta_0 vta 1.0 |
| |
| # connections and connection parameters |
| add_connection clk_0.clk hps_0.f2h_axi_clock clock |
| add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock |
| add_connection clk_0.clk vta_0.clock clock |
| add_connection clk_0.clk_reset vta_0.reset reset |
| |
| add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon |
| set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1} |
| set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000} |
| set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0} |
| |
| add_connection vta_0.m_axi_gmem hps_0.f2h_axi_slave avalon |
| set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave arbitrationPriority {1} |
| set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave baseAddress {0x0000} |
| set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave defaultConnection {0} |
| |
| # exported interfaces |
| add_interface clk clock sink |
| set_interface_property clk EXPORT_OF clk_0.clk_in |
| add_interface hps_0_h2f_reset reset source |
| set_interface_property hps_0_h2f_reset EXPORT_OF hps_0.h2f_reset |
| add_interface memory conduit end |
| set_interface_property memory EXPORT_OF hps_0.memory |
| add_interface reset reset sink |
| set_interface_property reset EXPORT_OF clk_0.clk_in_reset |
| |
| # interconnect requirements |
| set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE} |
| set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1} |
| |
| save_system soc_system.qsys |
