Port to the latest stable Chisel release (#33)
* modernize build.sbt
* fix some imports
* ignore target directory generated by sbt
* TensorGemm: explicitly define adder interface
* use ChiselStage instead of Driver
* setResource is now addResource
* add toInt in order to fix warning
diff --git a/hardware/chisel/.gitignore b/hardware/chisel/.gitignore
index f65a6ba..2ee056f 100644
--- a/hardware/chisel/.gitignore
+++ b/hardware/chisel/.gitignore
@@ -1 +1,3 @@
test_run_dir
+/target/
+/project/target/
diff --git a/hardware/chisel/build.sbt b/hardware/chisel/build.sbt
index 851f5ab..49c7951 100644
--- a/hardware/chisel/build.sbt
+++ b/hardware/chisel/build.sbt
@@ -21,60 +21,21 @@
version := "0.1.0-SNAPSHOT"
organization := "edu.washington.cs"
-def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
- Seq() ++ {
- // If we're building with Scala > 2.11, enable the compile option
- // switch to support our anonymous Bundle definitions:
- // https://github.com/scala/bug/issues/10047
- CrossVersion.partialVersion(scalaVersion) match {
- case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
- case _ => Seq(
- "-Xsource:2.11",
- "-language:reflectiveCalls",
- "-language:implicitConversions",
- "-deprecation",
- "-Xlint",
- "-Ywarn-unused",
- )
- }
- }
-}
-
-def javacOptionsVersion(scalaVersion: String): Seq[String] = {
- Seq() ++ {
- // Scala 2.12 requires Java 8. We continue to generate
- // Java 7 compatible code for Scala 2.11
- // for compatibility with old clients.
- CrossVersion.partialVersion(scalaVersion) match {
- case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
- Seq("-source", "1.7", "-target", "1.7")
- case _ =>
- Seq("-source", "1.8", "-target", "1.8")
- }
- }
-}
-
-scalaVersion := "2.11.12"
-
-resolvers ++= Seq(
- Resolver.sonatypeRepo("snapshots"),
- Resolver.sonatypeRepo("releases"))
-
-val defaultVersions = Map(
- "chisel3" -> "3.1.7",
- "chisel-iotesters" -> "1.2.4"
- )
-
-libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
- dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }
-
-libraryDependencies ++= Seq(
- "com.fasterxml.jackson.core" % "jackson-databind" % "2.10.3",
- "com.fasterxml.jackson.module" %% "jackson-module-scala" % "2.10.3"
+scalaVersion := "2.12.13"
+scalacOptions ++= Seq(
+ "-Xsource:2.11",
+ "-language:reflectiveCalls",
+ "-deprecation",
+ "-feature",
+ "-Xcheckinit",
)
-scalacOptions += "-language:reflectiveCalls"
-scalacOptions ++= Seq("-unchecked", "-deprecation", "-feature", "-Xfatal-warnings")
+resolvers += Resolver.sonatypeRepo("snapshots")
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.3"
+libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.3"
-scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
-javacOptions ++= javacOptionsVersion(scalaVersion.value)
+libraryDependencies += "com.fasterxml.jackson.core" % "jackson-databind" % "2.10.3"
+libraryDependencies += "com.fasterxml.jackson.module" %% "jackson-module-scala" % "2.10.3"
+
+addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full)
+addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
diff --git a/hardware/chisel/src/main/scala/core/TensorGemm.scala b/hardware/chisel/src/main/scala/core/TensorGemm.scala
index f63de94..8183557 100644
--- a/hardware/chisel/src/main/scala/core/TensorGemm.scala
+++ b/hardware/chisel/src/main/scala/core/TensorGemm.scala
@@ -44,18 +44,22 @@
io.y := addV
}
+class AdderIO(val aBits: Int, val bBits: Int) extends Bundle {
+ val outBits = Math.max(aBits, bBits) + 1
+ val a = Input(SInt(aBits.W))
+ val b = Input(SInt(bBits.W))
+ val y = Output(SInt(outBits.W))
+}
+
+trait IsAdder { val io: AdderIO }
+
/** PipeAdder
*
* This unit loads input bits into register and performs addition in the next cycle
*/
-class PipeAdder(aBits: Int = 8, bBits: Int = 8) extends Module {
- val outBits = Math.max(aBits, bBits) + 1
- val io = IO(new Bundle {
- val a = Input(SInt(aBits.W))
- val b = Input(SInt(bBits.W))
- val y = Output(SInt(outBits.W))
- })
- val add = Wire(SInt(outBits.W))
+class PipeAdder(aBits: Int = 8, bBits: Int = 8) extends Module with IsAdder {
+ val io = IO(new AdderIO(aBits, bBits))
+ val add = Wire(chiselTypeOf(io.y))
val rA = RegNext(io.a)
val rB = RegNext(io.b)
add := rA +& rB
@@ -67,14 +71,9 @@
* This unit wires input bits to an adder directly.
* The output comes out of combinational logic without waiting for another cycle.
*/
-class Adder(aBits: Int = 8, bBits: Int = 8) extends Module {
- val outBits = Math.max(aBits, bBits) + 1
- val io = IO(new Bundle {
- val a = Input(SInt(aBits.W))
- val b = Input(SInt(bBits.W))
- val y = Output(SInt(outBits.W))
- })
- val add = Wire(SInt(outBits.W))
+class Adder(aBits: Int = 8, bBits: Int = 8) extends Module with IsAdder {
+ val io = IO(new AdderIO(aBits, bBits))
+ val add = Wire(chiselTypeOf(io.y))
val rA = Wire(SInt(aBits.W))
val rB = Wire(SInt(bBits.W))
rA := io.a
diff --git a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
index a428916..73ae935 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
@@ -71,7 +71,7 @@
val reset = Input(Bool())
val dpi = new VTAHostDPIMaster
})
- setResource("/verilog/VTAHostDPI.v")
+ addResource("/verilog/VTAHostDPI.v")
}
/** Host DPI to AXI Converter.
diff --git a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
index bffbc1c..c77bafd 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
@@ -72,7 +72,7 @@
val reset = Input(Bool())
val dpi = new VTAMemDPIClient
})
- setResource("/verilog/VTAMemDPI.v")
+ addResource("/verilog/VTAMemDPI.v")
}
class VTAMemDPIToAXI(debug: Boolean = false)(implicit p: Parameters) extends Module {
diff --git a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
index 2f25328..96654d2 100644
--- a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
@@ -35,5 +35,5 @@
val reset = Input(Bool())
val dpi_wait = Output(Bool())
})
- setResource("/verilog/VTASimDPI.v")
+ addResource("/verilog/VTASimDPI.v")
}
diff --git a/hardware/chisel/src/main/scala/shell/SimShell.scala b/hardware/chisel/src/main/scala/shell/SimShell.scala
index 0909d1b..927f8af 100644
--- a/hardware/chisel/src/main/scala/shell/SimShell.scala
+++ b/hardware/chisel/src/main/scala/shell/SimShell.scala
@@ -20,7 +20,6 @@
package vta.shell
import chisel3._
-import chisel3.experimental.MultiIOModule
import vta.util.config._
import vta.interface.axi._
import vta.shell._
diff --git a/hardware/chisel/src/main/scala/shell/XilinxShell.scala b/hardware/chisel/src/main/scala/shell/XilinxShell.scala
index 28f95ea..1f49ba4 100644
--- a/hardware/chisel/src/main/scala/shell/XilinxShell.scala
+++ b/hardware/chisel/src/main/scala/shell/XilinxShell.scala
@@ -20,7 +20,6 @@
package vta.shell
import chisel3._
-import chisel3.experimental.{withClockAndReset, RawModule}
import vta.util.config._
import vta.interface.axi._
diff --git a/hardware/chisel/src/main/scala/test/Test.scala b/hardware/chisel/src/main/scala/test/Test.scala
index 7749d95..14fe1c2 100644
--- a/hardware/chisel/src/main/scala/test/Test.scala
+++ b/hardware/chisel/src/main/scala/test/Test.scala
@@ -20,7 +20,6 @@
package vta.test
import chisel3._
-import chisel3.experimental.MultiIOModule
import vta.util.config._
import vta.shell._
diff --git a/hardware/chisel/src/main/scala/vta/Configs.scala b/hardware/chisel/src/main/scala/vta/Configs.scala
index 350379b..73816c9 100644
--- a/hardware/chisel/src/main/scala/vta/Configs.scala
+++ b/hardware/chisel/src/main/scala/vta/Configs.scala
@@ -37,30 +37,30 @@
object DefaultPynqConfig extends App {
implicit val p: Parameters = new DefaultPynqConfig
- chisel3.Driver.execute(args, () => new XilinxShell)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new XilinxShell, args)
}
object DefaultF1Config extends App {
implicit val p: Parameters = new DefaultF1Config
- chisel3.Driver.execute(args, () => new XilinxShell)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new XilinxShell, args)
}
object DefaultDe10Config extends App {
implicit val p: Parameters = new DefaultDe10Config
- chisel3.Driver.execute(args, () => new IntelShell)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new IntelShell, args)
}
object TestDefaultPynqConfig extends App {
implicit val p: Parameters = new DefaultPynqConfig
- chisel3.Driver.execute(args, () => new Test)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new Test, args)
}
object TestDefaultF1Config extends App {
implicit val p: Parameters = new DefaultF1Config
- chisel3.Driver.execute(args, () => new Test)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new Test, args)
}
object TestDefaultDe10Config extends App {
implicit val p: Parameters = new DefaultDe10Config
- chisel3.Driver.execute(args, () => new Test)
+ (new chisel3.stage.ChiselStage).emitSystemVerilog(new Test, args)
}
diff --git a/hardware/chisel/src/test/scala/unittest/AluTest.scala b/hardware/chisel/src/test/scala/unittest/AluTest.scala
index c874b01..7c2cb88 100644
--- a/hardware/chisel/src/test/scala/unittest/AluTest.scala
+++ b/hardware/chisel/src/test/scala/unittest/AluTest.scala
@@ -56,7 +56,7 @@
// HLS shift left by >> negative number
// b always < 0 when opcode == 4
for (i <- 0 until size) {
- res(i) = a(i) << ((-1*b(i)) & mask)
+ res(i) = a(i) << ((-1*b(i)) & mask).toInt
}
} else { // default
for (i <- 0 until size) {
