| // Licensed to the Apache Software Foundation (ASF) under one |
| // or more contributor license agreements. See the NOTICE file |
| // distributed with this work for additional information |
| // regarding copyright ownership. The ASF licenses this file |
| // to you under the Apache License, Version 2.0 (the |
| // "License"); you may not use this file except in compliance |
| // with the License. You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, |
| // software distributed under the License is distributed on an |
| // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY |
| // KIND, either express or implied. See the License for the |
| // specific language governing permissions and limitations |
| // under the License. |
| |
| //======================================================= |
| // This code is partially generated by Terasic System Builder |
| //======================================================= |
| |
| module de10_nano_top( |
| |
| //////////// CLOCK ////////// |
| input FPGA_CLK1_50, |
| input FPGA_CLK2_50, |
| input FPGA_CLK3_50, |
| |
| //////////// HPS ////////// |
| inout HPS_CONV_USB_N, |
| output [14: 0] HPS_DDR3_ADDR, |
| output [ 2: 0] HPS_DDR3_BA, |
| output HPS_DDR3_CAS_N, |
| output HPS_DDR3_CK_N, |
| output HPS_DDR3_CK_P, |
| output HPS_DDR3_CKE, |
| output HPS_DDR3_CS_N, |
| output [ 3: 0] HPS_DDR3_DM, |
| inout [31: 0] HPS_DDR3_DQ, |
| inout [ 3: 0] HPS_DDR3_DQS_N, |
| inout [ 3: 0] HPS_DDR3_DQS_P, |
| output HPS_DDR3_ODT, |
| output HPS_DDR3_RAS_N, |
| output HPS_DDR3_RESET_N, |
| input HPS_DDR3_RZQ, |
| output HPS_DDR3_WE_N, |
| |
| //////////// LED ////////// |
| output [ 7: 0] LED |
| ); |
| |
| |
| |
| //======================================================= |
| // REG/WIRE declarations |
| //======================================================= |
| wire hps_fpga_reset_n; |
| wire fpga_clk_50; |
| // connection of internal logics |
| assign fpga_clk_50 = FPGA_CLK1_50; |
| |
| |
| //======================================================= |
| // Structural coding |
| //======================================================= |
| soc_system u0( |
| //Clock&Reset |
| .clk_clk(FPGA_CLK1_50), // clk.clk |
| .reset_reset_n(hps_fpga_reset_n), // reset.reset_n |
| //HPS ddr3 |
| .memory_mem_a(HPS_DDR3_ADDR), // memory.mem_a |
| .memory_mem_ba(HPS_DDR3_BA), // .mem_ba |
| .memory_mem_ck(HPS_DDR3_CK_P), // .mem_ck |
| .memory_mem_ck_n(HPS_DDR3_CK_N), // .mem_ck_n |
| .memory_mem_cke(HPS_DDR3_CKE), // .mem_cke |
| .memory_mem_cs_n(HPS_DDR3_CS_N), // .mem_cs_n |
| .memory_mem_ras_n(HPS_DDR3_RAS_N), // .mem_ras_n |
| .memory_mem_cas_n(HPS_DDR3_CAS_N), // .mem_cas_n |
| .memory_mem_we_n(HPS_DDR3_WE_N), // .mem_we_n |
| .memory_mem_reset_n(HPS_DDR3_RESET_N), // .mem_reset_n |
| .memory_mem_dq(HPS_DDR3_DQ), // .mem_dq |
| .memory_mem_dqs(HPS_DDR3_DQS_P), // .mem_dqs |
| .memory_mem_dqs_n(HPS_DDR3_DQS_N), // .mem_dqs_n |
| .memory_mem_odt(HPS_DDR3_ODT), // .mem_odt |
| .memory_mem_dm(HPS_DDR3_DM), // .mem_dm |
| .memory_oct_rzqin(HPS_DDR3_RZQ), // .oct_rzqin |
| //FPGA |
| .hps_0_h2f_reset_reset_n(hps_fpga_reset_n) // hps_0_h2f_reset.reset_n |
| ); |
| |
| |
| // Blink LED, to indicate everything is working |
| reg [25: 0] counter; |
| reg led_level; |
| always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin |
| if (~hps_fpga_reset_n) begin |
| counter <= 0; |
| led_level <= 0; |
| end |
| else if (counter == 24999999) begin |
| counter <= 0; |
| led_level <= ~led_level; |
| end |
| else |
| counter <= counter + 1'b1; |
| end |
| assign LED[0] = led_level; |
| |
| |
| endmodule |