apps/tsim_example/tests/python/verilog_accel.py

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import tvm
from tvm import te
import numpy as np
import tsim

def test_accel():
    rmax = 64
    dtype = "uint64"
    n = np.random.randint(1, rmax)
    c = np.random.randint(0, rmax)
    ctx = tvm.cpu(0)
    a = tvm.nd.array(np.random.randint(rmax, size=n).astype(dtype), ctx)
    b = tvm.nd.array(np.zeros(n).astype(dtype), ctx)
    f = tsim.load_module()
    cycles = f(a, b, c)
    msg = "cycles:{0:4} n:{1:2} c:{2:2}".format(cycles, n, c)
    np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg = "[FAIL] " + msg)
    print("[PASS] " + msg)

if __name__ == "__main__":
    tsim.init("verilog")
    for i in range(10):
        test_accel()