| /**************************************************************************** |
| * boards/arm/stm32/stm32f411-minimum/include/board.h |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * Licensed to the Apache Software Foundation (ASF) under one or more |
| * contributor license agreements. See the NOTICE file distributed with |
| * this work for additional information regarding copyright ownership. The |
| * ASF licenses this file to you under the Apache License, Version 2.0 (the |
| * "License"); you may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at |
| * |
| * http://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| * License for the specific language governing permissions and limitations |
| * under the License. |
| * |
| ****************************************************************************/ |
| |
| #ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H |
| #define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H |
| |
| /**************************************************************************** |
| * Included Files |
| ****************************************************************************/ |
| |
| #include <nuttx/config.h> |
| #ifndef __ASSEMBLY__ |
| # include <stdint.h> |
| #endif |
| |
| /**************************************************************************** |
| * Pre-processor Definitions |
| ****************************************************************************/ |
| |
| /* Clocking *****************************************************************/ |
| |
| /* System Clock source : PLLCLK (HSE) |
| * SYSCLK(Hz) : 96000000 Determined by PLL config |
| * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) |
| * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) |
| * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) |
| * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) |
| * HSI Frequency(Hz) : 16000000 (nominal) |
| * PLLM : 4 (STM32_PLLCFG_PLLM) |
| * PLLN : 192 (STM32_PLLCFG_PLLN) |
| * PLLP : 4 (STM32_PLLCFG_PLLP) |
| * PLLQ : 8 (STM32_PLLCFG_PPQ) |
| * Flash Latency(WS) : 3 |
| * Prefetch Buffer : OFF |
| * Instruction cache : ON |
| * Data cache : ON |
| * Require 48MHz for USB OTG FS, : Enabled |
| * SDIO and RNG clock |
| */ |
| |
| /* HSI - 16 MHz RC factory-trimmed |
| * LSI - 32 KHz RC |
| * HSE - 25 MHz Crystal |
| * LSE - 32 KHz Crystal |
| */ |
| |
| #define STM32_BOARD_XTAL 25000000ul |
| |
| #define STM32_HSI_FREQUENCY 16000000ul |
| #define STM32_LSI_FREQUENCY 32000 |
| #define STM32_LSE_FREQUENCY 32768 |
| #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
| |
| /* Main PLL Configuration. |
| * |
| * Formulae: |
| * |
| * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 |
| * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 |
| * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 |
| * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 |
| * |
| * There is no config for 100 MHz and 48 MHz for usb, |
| * so we would like to have SYSYCLK=96MHz and we must have the USB |
| * clock = 48MHz |
| * |
| * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 |
| * |
| * We will configure like this |
| * |
| * PLL source is HSE |
| * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
| * = (25,000,000 / 25) * 192 |
| * = 192,000,000 |
| * SYSCLK = PLL_VCO / PLLP |
| * = 192,000,000 / 2 = 96,000,000 |
| * USB OTG FS and SDIO Clock |
| * = PLL_VCO / PLLQ |
| * = 96,000,000 / 2 = 48,000,000 |
| */ |
| |
| #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) |
| #define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) |
| #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
| #define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) |
| |
| #define STM32_SYSCLK_FREQUENCY 96000000ul |
| |
| /* AHB clock (HCLK) is SYSCLK (96MHz) */ |
| |
| #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
| #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
| |
| /* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ |
| |
| #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
| #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
| |
| /* Timers driven from APB1 will be twice PCLK1 */ |
| |
| /* REVISIT */ |
| |
| #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| |
| /* APB2 clock (PCLK2) is HCLK (48MHz) */ |
| |
| #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
| #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
| |
| /* Timers driven from APB2 will be twice PCLK2 */ |
| |
| #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
| #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
| #define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) |
| |
| /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
| * otherwise frequency is 2xAPBx. |
| * Note: TIM1,8 are on APB2, others on APB1 |
| */ |
| |
| /* REVISIT */ |
| |
| #define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) |
| #define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) |
| #define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) |
| |
| /* SDIO dividers. Note that slower clocking is required when DMA is disabled |
| * in order to avoid RX overrun/TX underrun errors due to delayed responses |
| * to service FIFOs in interrupt driven mode. These values have not been |
| * tuned!!! |
| * |
| * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz |
| */ |
| |
| /* REVISIT */ |
| |
| #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) |
| |
| /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz |
| * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
| */ |
| |
| /* REVISIT */ |
| |
| #ifdef CONFIG_SDIO_DMA |
| # define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
| #else |
| # define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
| #endif |
| |
| /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz |
| * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
| */ |
| |
| /* REVISIT */ |
| |
| #ifdef CONFIG_SDIO_DMA |
| # define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
| #else |
| # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
| #endif |
| |
| /* DMA Channel/Stream Selections ********************************************/ |
| |
| /* Stream selections are arbitrary for now but might become important in the |
| * future is we set aside more DMA channels/streams. |
| * |
| * SDIO DMA |
| * DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA |
| * DMAMAP_SDIO_2 = Channel 4, Stream 6 |
| */ |
| |
| #define DMAMAP_SDIO DMAMAP_SDIO_1 |
| |
| /* Need to VERIFY fwb */ |
| |
| #define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 |
| #define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 |
| #define DMACHAN_SPI2_RX DMAMAP_SPI2_RX |
| #define DMACHAN_SPI2_TX DMAMAP_SPI2_TX |
| |
| /* Alternate function pin selections ****************************************/ |
| |
| /* USART1: |
| * RXD: PA10 CN9 pin 3, CN10 pin 33 |
| * PB7 CN7 pin 21 |
| * TXD: PA9 CN5 pin 1, CN10 pin 21 |
| * PB6 CN5 pin 3, CN10 pin 17 |
| */ |
| |
| #if 1 |
| # define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */ |
| # define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */ |
| #else |
| # define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */ |
| # define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ |
| #endif |
| |
| /* USART2: |
| * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 |
| * PD6 |
| * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 |
| * PD5 |
| */ |
| |
| #define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ |
| #define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ |
| #define GPIO_USART2_RTS GPIO_USART2_RTS_2 |
| #define GPIO_USART2_CTS GPIO_USART2_CTS_2 |
| |
| /* USART6: |
| * RXD: PC7 CN5 pin2, CN10 pin 19 |
| * PA12 CN10, pin 12 |
| * TXD: PC6 CN10, pin 4 |
| * PA11 CN10, pin 14 |
| */ |
| |
| #define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */ |
| #define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */ |
| |
| /* PWM |
| * |
| * The STM32F4 Discovery has no real on-board PWM devices, but the board |
| * can be configured to output a pulse train using TIM4 CH2 on PD13. |
| */ |
| #define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 //PA8 |
| #define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_1 //PA1 |
| #define GPIO_TIM3_CH3OUT GPIO_TIM3_CH3OUT_1 //PB0 |
| #define GPIO_TIM4_CH4OUT GPIO_TIM4_CH4OUT_1 //PB9 |
| |
| /* RGB LED |
| * |
| * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 |
| * |
| * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT |
| */ |
| |
| #define RGBLED_RPWMTIMER 1 |
| #define RGBLED_RPWMCHANNEL 1 |
| #define RGBLED_GPWMTIMER 2 |
| #define RGBLED_GPWMCHANNEL 2 |
| #define RGBLED_BPWMTIMER 4 |
| #define RGBLED_BPWMCHANNEL 4 |
| |
| /* UART RX DMA configurations */ |
| |
| #define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 |
| #define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 |
| |
| /* I2C |
| * |
| * The optional _GPIO configurations allow the I2C driver to manually |
| * reset the bus to clear stuck slaves. They match the pin configuration, |
| * but are normally-high GPIOs. |
| */ |
| |
| #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 |
| #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 |
| #define GPIO_I2C1_SCL_GPIO \ |
| (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) |
| #define GPIO_I2C1_SDA_GPIO \ |
| (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) |
| |
| #define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 |
| #define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 |
| #define GPIO_I2C2_SCL_GPIO \ |
| (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) |
| #define GPIO_I2C2_SDA_GPIO \ |
| (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) |
| |
| /* SPI |
| * |
| * There are sensors on SPI1, and SPI2 is connected to the FRAM. |
| */ |
| |
| #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 |
| #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 |
| #define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 |
| |
| #define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 |
| #define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 |
| #define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 |
| |
| /* LEDs |
| * |
| * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. |
| */ |
| |
| /* The board has only one controllable LED */ |
| |
| #define LED_STARTED 0 /* No LEDs */ |
| #define LED_HEAPALLOCATE 1 /* LED1 on */ |
| #define LED_IRQSENABLED 2 /* LED1 on */ |
| #define LED_STACKCREATED 3 /* LED1 on */ |
| #define LED_INIRQ 4 /* LED1 on */ |
| #define LED_SIGNAL 5 /* LED1 on */ |
| #define LED_ASSERTION 6 /* LED1 on */ |
| #define LED_PANIC 7 /* LED1 blinking */ |
| |
| /* LED index values for use with board_userled() */ |
| |
| #define BOARD_LED1 0 |
| #define BOARD_NLEDS 1 |
| |
| /* LED bits for use with board_userled_all() */ |
| |
| #define BOARD_LED1_BIT (1 << BOARD_LED1) |
| |
| /* Buttons |
| * |
| * B1 USER: the user button is connected to the I/O PA0 of the STM32 |
| * microcontroller. |
| */ |
| |
| #define BUTTON_USER 0 |
| #define BUTTON_EXTERNAL 1 //External user button connected to PA1 |
| #define NUM_BUTTONS 2 |
| |
| #define BUTTON_USER_BIT (1 << BUTTON_USER) |
| #define BUTTON_EXTERNAL_BIT (1 << BUTTON_EXTERNAL) |
| |
| #endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ |
