| /**************************************************************************** |
| * arch/arm/src/efm32/hardware/efm32tg_memorymap.h |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc. |
| * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved. |
| * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com> |
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| * |
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| ****************************************************************************/ |
| |
| #ifndef __ARCH_ARM_SRC_EFM32_HARDWARE_EFM3TG_MEMORYMAP_H |
| #define __ARCH_ARM_SRC_EFM32_HARDWARE_EFM3TG_MEMORYMAP_H |
| |
| /**************************************************************************** |
| * Pre-processor Definitions |
| ****************************************************************************/ |
| |
| /* Memory Base addresses */ |
| |
| #define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */ |
| # define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */ |
| #define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */ |
| # define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */ |
| #define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */ |
| # define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */ |
| #define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */ |
| # define EFM32_PER_MEM_BITS 0x00000020 /* PER used bits */ |
| #define EFM32_AES_MEM_BASE 0x400e0000 /* AES base address */ |
| # define EFM32_AES_MEM_BITS 0x00000010 /* AES used bits */ |
| |
| /* Bit banding area */ |
| |
| #define EFM32_BITBAND_PER_BASE 0x42000000 /* Peripheral Address Space bit-band area */ |
| #define EFM32_BITBAND_RAM_BASE 0x22000000 /* SRAM Address Space bit-band area */ |
| |
| /* Flash and SRAM Addresses */ |
| |
| #define EFM32_FLASH_BASE 0x00000000 /* Flash Base Address */ |
| #define EFM32_SRAM_BASE 0x20000000 /* SRAM Base Address */ |
| |
| /* Peripheral base address */ |
| |
| #define EFM32_VCMP_BASE 0x40000000 /* VCMP base address */ |
| #define EFM32_ACMP0_BASE 0x40001000 /* ACMP0 base address */ |
| #define EFM32_ACMP1_BASE 0x40001400 /* ACMP1 base address */ |
| #define EFM32_ADC0_BASE 0x40002000 /* ADC0 base address */ |
| #define EFM32_DAC0_BASE 0x40004000 /* DAC0 base address */ |
| #define EFM32_GPIO_BASE 0x40006000 /* GPIO base address */ |
| #define EFM32_I2C0_BASE 0x4000a000 /* I2C0 base address */ |
| #define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */ |
| #define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */ |
| #define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */ |
| #define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */ |
| #define EFM32_RTC_BASE 0x40080000 /* RTC base address */ |
| #define EFM32_LEUART0_BASE 0x40084000 /* LEUART0 base address */ |
| #define EFM32_LETIMER0_BASE 0x40082000 /* LETIMER0 base address */ |
| #define EFM32_PCNT0_BASE 0x40086000 /* PCNT0 base address */ |
| #define EFM32_WDOG_BASE 0x40088000 /* WDOG base address */ |
| #define EFM32_LCD_BASE 0x4008a000 /* LCD base address */ |
| #define EFM32_LESENSE_BASE 0x4008c000 /* LESENSE base address */ |
| #define EFM32_MSC_BASE 0x400c0000 /* MSC base address */ |
| #define EFM32_DMA_BASE 0x400c2000 /* DMA base address */ |
| #define EFM32_CMU_BASE 0x400c8000 /* CMU base address */ |
| #define EFM32_EMU_BASE 0x400c6000 /* EMU base address */ |
| #define EFM32_RMU_BASE 0x400ca000 /* RMU base address */ |
| #define EFM32_PRS_BASE 0x400cc000 /* PRS base address */ |
| #define EFM32_AES_BASE 0x400e0000 /* AES base address */ |
| |
| /* ROM specific region */ |
| |
| #define EFM32_ROMTABLE_BASE 0xe00fffd0 /* ROMTABLE base address */ |
| |
| /* Flash specific region */ |
| |
| #define EFM32_USERDATA_BASE 0x0fe00000 /* User data page base address */ |
| #define EFM32_LOCKBITS_BASE 0x0fe04000 /* Lock-bits page base address */ |
| #define EFM32_CALIBRATE_BASE 0x0fe08000 /* CALIBRATE base address */ |
| #define EFM32_DEVINFO_BASE 0x0fe081b0 /* DEVINFO base address */ |
| |
| #endif /* __ARCH_ARM_SRC_EFM32_HARDWARE_EFM3TG_MEMORYMAP_H */ |
