arch/arm64/Kconfig

#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_ARM64
comment "ARM64 Options"

choice
	prompt "ARM64 Toolchain Selection"
	default ARM64_TOOLCHAIN_GNU_EABI

config ARM64_TOOLCHAIN_GNU_EABI
	bool "Generic GNU EABI toolchain"
	select ARCH_TOOLCHAIN_GNU
	---help---
		This option should work for any modern GNU toolchain (GCC 4.5 or newer)

config ARM64_TOOLCHAIN_CLANG
	bool "LLVM Clang toolchain"
	select ARCH_TOOLCHAIN_CLANG

endchoice # ARM64 Toolchain Selection

choice
	prompt "ARM64 chip selection"
	default ARCH_CHIP_QEMU

config ARCH_CHIP_A64
	bool "Allwinner A64"
	select ARCH_CORTEX_A53
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_RESET
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_NEED_ADDRENV_MAPPING
	select ARM64_HAVE_PSCI
	---help---
		Allwinner A64 SoC

config ARCH_CHIP_RK3399
	bool "Rockchip RK3399"
	select ARCH_CORTEX_A53
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_RESET
	select ARCH_NEED_ADDRENV_MAPPING
	select ARM64_HAVE_PSCI
	---help---
		Rockchip RK3399 SoC

config ARCH_CHIP_QEMU
	bool "QEMU virt platform (ARMv8a)"
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_POWEROFF
	select ARCH_HAVE_RESET
	select ARCH_HAVE_TEXT_HEAP
	select ARM64_HAVE_PSCI
	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
	---help---
		QEMU virt platform (ARMv8a)

config ARCH_CHIP_GOLDFISH
	bool "goldfish platform (ARMv8a)"
	select ARCH_CORTEX_A53
	select ARCH_HAVE_MULTICPU
	select ARMV8A_HAVE_GICv2
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_HAVE_POWEROFF
	select ARCH_HAVE_RESET
	select ARCH_NEED_ADDRENV_MAPPING
	select ARM64_HAVE_PSCI
	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
	---help---
		Android GoldFish platform for NuttX (ARMv8a),
		based on ARM virt board

config ARCH_CHIP_FVP_ARMV8R
	bool "ARM FVP virt platform (ARMv8r)"
	select ARCH_CORTEX_R82
	select ARCH_HAVE_IRQTRIGGER
	---help---
		ARM FVP virt platform (ARMv8r)

config ARCH_CHIP_IMX8
	bool "NXP i.MX8 Platform (ARMv8a)"
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_NEED_ADDRENV_MAPPING
	---help---
		NXP i.MX8 (ARMv8a) applications processors

config ARCH_CHIP_IMX9
	bool "NXP i.MX9 Platform (ARMv8.2a)"
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_NEED_ADDRENV_MAPPING
	---help---
		NXP i.MX9 (ARMv8.2a) applications processors

config ARCH_CHIP_ZYNQ_MPSOC
	bool "XilinX Zynq UltraScale+ MPSoC"
	select ARCH_CORTEX_A53
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_RESET
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_NEED_ADDRENV_MAPPING
	select ARM64_HAVE_PSCI
	---help---
		XilinX ZYNQ MPSOC
		
config ARCH_CHIP_ARM64_CUSTOM
	bool "Custom ARM64 chip"
	select ARCH_CHIP_CUSTOM
	---help---
		Select this option if there is no directory for the chip under arch/arm64/src/.

endchoice # ARM64 chip selection

config ARCH_ARMV8A
	bool
	default n
	select ARCH_HAVE_EL3

config ARCH_ARMV8R
	bool
	default n
	select ARCH_SINGLE_SECURITY_STATE

config ARCH_SINGLE_SECURITY_STATE
	bool "ARM Single Security State Support"
	default n
	---help---
		Some ARM aarch64 Cortex-family processors only supports single
		security state(eg. Cortex-R82). For these Processors,
		GIC or other ARM architecture feature will with different
		configure

config ARCH_HAVE_EL3
	bool
	default n
	---help---
		Some ARM aarch64 Cortex-family processors only supports
		EL0~El2(eg. Cortex-R82). For these Processors, the code
		runing at EL3 is not necessary and system register for EL3
		is not accessible

config ARCH_ARM64_EXCEPTION_LEVEL
	int "Exception level to operate"
	default 1
	range 1 3
	---help---
		Default exception level is EL1 for the NuttX OS. However,
		if NuttX works as the primary bootloader, this may be set
		to EL3. Other levels are not supported at the moment.

config ARCH_SET_VMPIDR_EL2
	bool "Set VMPIDR_EL2 at EL2 stage"
	---help---
		VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
		From architecture manual of AArch64, the behave is:
		  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
		  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
		So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
		identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
		every CPU at boot EL2 stage.
		For some platform, the bootloader or hypervisor will do that at
		the EL2 stage, but not all.
		ARM FVP and VDK should set it since these platform will boot
		without BootLoader.

config ARCH_EARLY_PRINT
	bool "arch early print support"
	default n
	---help---
		The aarch64 have EL0~El3 execute level and NS/S (security state),
		the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
		state. but booting NuttX have different ELs and state while with
		different platform, if NuttX runing at wrong ELs or state it will
		not normal anymore. So we need to print something in arm64_head.S
		to debug this situation.
		Enabling this option will need to implement arm64_earlyprintinit and
		arm64_lowputc functions just you see in qemu_lowputc.S.
		by default, UART dev will be used. You can also logging the booting
		message through rewriting fake arm64_lowputc with other debug
		method (eg semihosting , ARM debug channel etc)
		if you not sure, keeping the option disable.

config ARCH_CORTEX_A53
	bool
	default n
	select ARCH_ARMV8A
	select ARCH_HAVE_TRUSTZONE
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MMU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TESTSET
	select ARM64_HAVE_NEON

config ARCH_CORTEX_A55
	bool
	default n
	select ARCH_ARMV8A
	select ARCH_HAVE_TRUSTZONE
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MMU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TESTSET
	select ARM64_HAVE_NEON

config ARCH_CORTEX_A57
	bool
	default n
	select ARCH_ARMV8A
	select ARCH_HAVE_TRUSTZONE
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MMU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TESTSET
	select ARM64_HAVE_NEON

config ARCH_CORTEX_A72
	bool
	default n
	select ARCH_ARMV8A
	select ARCH_HAVE_TRUSTZONE
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MMU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TESTSET
	select ARM64_HAVE_NEON

config ARCH_CORTEX_R82
	bool
	default n
	select ARCH_ARMV8R
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TESTSET
	select ARM64_HAVE_NEON

config ARCH_FAMILY
	string
	default "armv8-a"   if ARCH_ARMV8A
	default "armv8-r"   if ARCH_ARMV8R

config ARCH_CHIP
	string
	default "a64"       if ARCH_CHIP_A64
	default "rk3399"    if ARCH_CHIP_RK3399
	default "zynq-mpsoc" if ARCH_CHIP_ZYNQ_MPSOC
	default "qemu"      if ARCH_CHIP_QEMU
	default "goldfish"  if ARCH_CHIP_GOLDFISH
	default "fvp-v8r"   if ARCH_CHIP_FVP_ARMV8R
	default "imx8"      if ARCH_CHIP_IMX8
	default "imx9"      if ARCH_CHIP_IMX9

config ARM64_HAVE_PSCI
	bool "ARM PCSI (Power State Coordination Interface) Support"
	default n
	---help---
		This Power State Coordination Interface (PSCI) defines
		a standard interface for power management. the PCSI need
		to implement handling firmware at EL2 or EL3. The option
		maybe not applicable for arm core without PCSI firmware
		interface implement

config ARM64_PSCI
	bool "Enabled PSCI"
	depends on ARM64_HAVE_PSCI
	default y
	---help---
		See ARM64_HAVE_PSCI for details

config ARM64_HAVE_NEON
	bool
	default n
	---help---
		Decide whether support NEON instruction

config ARM64_NEON
	bool "Advanced SIMD (NEON) Extension"
	default y
	depends on ARM64_HAVE_NEON

config ARM64_DECODEFIQ
	bool "FIQ Handler"
	default n
	---help---
		Select this option if your platform supports the function
		arm_decodefiq().  This is used primarily to support secure TrustZone
		interrupts received on the FIQ vector.

config ARM64_GIC_VERSION
	int "GIC version"
	default 2           if ARCH_CHIP_A64
	default 3
	range 2 4
	---help---
		Version of Generic Interrupt Controller (GIC) supported by the
		architecture

if ARM64_GIC_VERSION = 2

config ARM64_GIC_EOIMODE
	bool
	default n
	---help---
		Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt
		deactivation operations.

endif

config ARM64_SEMIHOSTING_HOSTFS
	bool "Semihosting HostFS"
	depends on FS_HOSTFS
	---help---
		Mount HostFS through semihosting.

		This doesn't support some directory operations like readdir because
		of the limitations of semihosting mechanism.

if ARM64_SEMIHOSTING_HOSTFS

config ARM64_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
	bool "Cache coherence in semihosting hostfs"
	depends on ARCH_DCACHE
	---help---
		Flush & Invalidte cache before & after bkpt instruction.

endif # ARM64_SEMIHOSTING_HOSTFS

config ARM64_DCACHE_DISABLE
	bool "Disable DCACHE at __start"
	default n

config ARM64_ICACHE_DISABLE
	bool "Disable ICACHE at __start"
	default n

if ARCH_CHIP_A64
source "arch/arm64/src/a64/Kconfig"
endif

if ARCH_CHIP_RK3399
source "arch/arm64/src/rk3399/Kconfig"
endif

if ARCH_CHIP_QEMU
source "arch/arm64/src/qemu/Kconfig"
endif

if ARCH_CHIP_FVP_ARMV8R
source "arch/arm64/src/fvp-v8r/Kconfig"
endif

if ARCH_CHIP_IMX8
source "arch/arm64/src/imx8/Kconfig"
endif

if ARCH_CHIP_IMX9
source "arch/arm64/src/imx9/Kconfig"
endif

if ARCH_CHIP_GOLDFISH
source "arch/arm64/src/goldfish/Kconfig"
endif

if ARCH_CHIP_ZYNQ_MPSOC
source "arch/arm64/src/zynq-mpsoc/Kconfig"
endif

endif # ARCH_ARM64