arch/arm/src/armv8-r/Kconfig

#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

comment "ARMv8-R Configuration Options"

config ARMV8R_HAVE_GICv3
	bool "ARMV8R_GICv3 support"
	select ARCH_HAVE_IRQTRIGGER
	default y
	---help---
		Selected by the configuration tool if the architecture supports the
		Generic Interrupt Controller (GIC)

if ARMV8R_HAVE_GICv3

config ARMV8R_GIC_EOIMODE
	bool
	default n
	---help---
		Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt
		deactivation operations.

config ARMV8R_GIC_SPI_EDGE
	bool "Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default"
	default n
	---help---
		Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default.

endif # ARMV8R_HAVE_GICv3

config ARMV8R_MEMINIT
	bool
	default BOOT_SDRAM_DATA
	---help---
		If this configuration *not* selected, then it is assumed that all
		memory resources are initialized via arm_data_initialize() and
		available at power-up reset time.  Other memories, such as SDRAM or
		some ECC SRAM memories, require some platform-specific
		initialization first.  In that case, this option should be selected
		and the platform-specific implementation of arm_boot() must perform
		the memory initialization first, then explicitly call
		arm_data_initialize().

config ARMV8R_HAVE_DECODEFIQ
	bool
	default n

config ARMV8R_DECODEFIQ
	bool "FIQ Handler"
	default n
	depends on ARMV8R_HAVE_DECODEFIQ
	---help---
		Select this option if your platform supports the function
		arm_decodefiq().

config ARMV8R_ALIGNMENT_TRAP
	bool "Enable Alignment Check at __start"
	default n

config ARMV8R_CACHE_ROUND_ROBIN
	bool "Enable Cache Round Robin Replacement Policy at __start"
	default n

config ARMV8R_DCACHE_DISABLE
	bool "Disable DCACHE at __start"
	default n

config ARMV8R_ICACHE_DISABLE
	bool "Disable ICACHE at __start"
	default n

config ARMV8R_SCTLR_CCP15BEN
	bool "Enable CP15 Barrier at __start"
	default y

config ARMV8R_BACKGROUND_REGION
	bool "Enable MPU Background region at __start"
	default y

config ARMV8R_DIV0_FAULT
	bool "Enable DIV0 Fault at __start"
	default n

config ARMV8R_FAST_INTERRUPT
	bool "Enable Fast Interrupts at __start"
	default n

config ARMV8R_NONMASKABLE_FIQ
	bool "Enable Non-maskable FIQ Support at __start"
	default n

config ARMV8R_HAVE_L2CC
        bool
        default n
        ---help---
                Selected by the configuration tool if the architecture supports any
                kind of L2 cache.

config ARMV8R_HAVE_L2CC_PL310
        bool
        default n
        select ARMV8R_HAVE_L2CC
        ---help---
                Set by architecture-specific code if the hardware supports a PL310
                r3p2 L2 cache (only version r3p2 is supported).

if ARMV8R_HAVE_L2CC

menu "L2 Cache Configuration"

config ARMV8R_L2CC_PL310
        bool "ARMv8-R L2CC P310 Support"
        default n
        depends on ARMV8R_HAVE_L2CC_PL310
        select ARCH_L2CACHE
        ---help---
                Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
                multi-way cache macrocell, version r3p2.  The addition of an on-chip
                secondary cache, also referred to as a Level 2 or L2 cache, is a
                method of improving the system performance when significant memory
                traffic is generated by the processor.

if ARCH_L2CACHE
if ARMV8R_L2CC_PL310

config PL310_LOCKDOWN_BY_MASTER
        bool "PL310 Lockdown by Master"
        default n

config PL310_LOCKDOWN_BY_LINE
        bool "PL310 Lockdown by Line"
        default n

config PL310_ADDRESS_FILTERING
        bool "PL310 Address Filtering by Line"
        default n

config PL310_TRCR
        bool "PL310 TRCR set by usr"
        default n

if PL310_TRCR
config PL310_TRCR_TSETLAT
        int "PL310 TRCR setup latency"
        default 1

config PL310_TRCR_TRDLAT
        int "PL310 TRCR read access latency"
        default 1

config PL310_TRCR_TWRLAT
        int "PL310 TRCR write access latency"
        default 1
endif # PL310_TRCR

config PL310_DRCR
        bool "PL310 DRCR set by usr"
        default n

if PL310_DRCR
config PL310_DRCR_DSETLAT
        int "PL310 DRCR setup latency"
        default 1

config PL310_DRCR_DRDLAT
        int "PL310 DRCR read access latency"
        default 1

config PL310_DRCR_DWRLAT
        int "PL310 DRCR write access latency"
        default 1
endif # PL310_DRCR
endif # ARMV8R_L2CC_PL310

choice
        prompt "L2 Cache Associativity"
        default ARMV8R_ASSOCIATIVITY_8WAY
        depends on ARCH_L2CACHE
        ---help---
                This choice specifies the associativity of L2 cache in terms of the
                number of ways.  This value could be obtained by querying cache
                configuration registers.  However, by defining a configuration
                setting instead, we can avoid using RAM memory to hold information
                about properties of the memory.

config ARMV8R_ASSOCIATIVITY_8WAY
        bool "8-Way Associativity"

config ARMV8R_ASSOCIATIVITY_16WAY
        bool "16-Way Associativity"

endchoice # L2 Cache Associativity

choice
        prompt "L2 Cache Way Size"
        default ARMV8R_WAYSIZE_16KB
        depends on ARCH_L2CACHE
        ---help---
                This choice specifies size of each way. This value can be obtained
                by querying cache configuration registers.  However, by defining a
                configuration setting instead, we can avoid using RAM memory to hold
                information

config ARMV8R_WAYSIZE_16KB
        bool "16 KiB"

config ARMV8R_WAYSIZE_32KB
        bool "32 KiB"

config ARMV8R_WAYSIZE_64KB
        bool "64 KiB"

config ARMV8R_WAYSIZE_128KB
        bool "128 KiB"

config ARMV8R_WAYSIZE_256KB
        bool "256 KiB"

config ARMV8R_WAYSIZE_512KB
        bool "512 KiB"

endchoice # L2 Cache Way Size
endif # ARCH_L2CACHE
endmenu # L2 Cache Configuration
endif # ARMV8R_HAVE_L2CC