blob: 20bf0ed74f25ba9026551854482d118baa4e3fa7 [file] [log] [blame]
############################################################################
# arch/risc-v/src/rv32m1/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include common/Make.defs
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = rv32m1_head.S
# Specify our general Assembly files
CMN_ASRCS := $(filter-out riscv_exception_common.S,$(CMN_ASRCS))
# Specify our C code within this directory to be included
CHIP_CSRCS = rv32m1_allocateheap.c rv32m1_clockconfig.c rv32m1_gpio.c
CHIP_CSRCS += rv32m1_irq.c rv32m1_irq_dispatch.c
CHIP_CSRCS += rv32m1_lowputc.c rv32m1_serial.c
CHIP_CSRCS += rv32m1_start.c rv32m1_timerisr.c
CHIP_CSRCS += rv32m1_pcc.c
CHIP_CSRCS += rv32m1_delay.c rv32m1_timersvc.c