| /**************************************************************************** |
| * arch/arm/src/gd32f4/gd32f4xx_start.c |
| * |
| * Licensed to the Apache Software Foundation (ASF) under one or more |
| * contributor license agreements. See the NOTICE file distributed with |
| * this work for additional information regarding copyright ownership. The |
| * ASF licenses this file to you under the Apache License, Version 2.0 (the |
| * "License"); you may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at |
| * |
| * http://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| * License for the specific language governing permissions and limitations |
| * under the License. |
| * |
| ****************************************************************************/ |
| |
| /**************************************************************************** |
| * Included Files |
| ****************************************************************************/ |
| |
| #include <nuttx/config.h> |
| |
| #include <stdint.h> |
| #include <assert.h> |
| #include <debug.h> |
| |
| #include <nuttx/init.h> |
| |
| #include "arm_internal.h" |
| #include "nvic.h" |
| #include "mpu.h" |
| |
| #include "gd32f4xx.h" |
| #include "gd32f4xx_gpio.h" |
| #include "gd32f4xx_start.h" |
| |
| /**************************************************************************** |
| * Pre-processor Definitions |
| ****************************************************************************/ |
| |
| /* .data is positioned first in the primary RAM followed immediately by .bss. |
| * The IDLE thread stack lies just after .bss and has size give by |
| * CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE. |
| * ARM EABI requires 64 bit stack alignment. |
| */ |
| |
| #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) |
| |
| /**************************************************************************** |
| * Public Data |
| ****************************************************************************/ |
| |
| /* g_idle_topstack: _sbss is the start of the BSS region as defined by the |
| * linker script. _ebss lies at the end of the BSS region. The idle task |
| * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. |
| * The IDLE thread is the thread that the system boots on and, eventually, |
| * becomes the IDLE, do nothing task that runs only when there is nothing |
| * else to run. The heap continues from there until the end of memory. |
| * g_idle_topstack is a read-only variable the provides this computed |
| * address. |
| */ |
| |
| const uintptr_t g_idle_topstack = HEAP_BASE; |
| |
| /**************************************************************************** |
| * Private Function prototypes |
| ****************************************************************************/ |
| |
| #ifdef CONFIG_ARCH_FPU |
| static inline void gd32_fpuconfig(void); |
| #endif |
| |
| /**************************************************************************** |
| * Public Function prototypes |
| ****************************************************************************/ |
| #ifdef CONFIG_ARMV7M_STACKCHECK |
| /* we need to get r10 set before we can allow instrumentation calls */ |
| |
| void __start(void) noinstrument_function; |
| #endif |
| |
| /**************************************************************************** |
| * Private Functions |
| ****************************************************************************/ |
| |
| /**************************************************************************** |
| * Name: showprogress |
| * |
| * Description: |
| * Print a character on the UART to show boot status. |
| * |
| ****************************************************************************/ |
| |
| #ifdef CONFIG_DEBUG_FEATURES |
| # define showprogress(c) arm_lowputc(c) |
| #else |
| # define showprogress(c) |
| #endif |
| |
| /**************************************************************************** |
| * Name: gd32_fpuconfig |
| * |
| * Description: |
| * Configure the FPU. Relative bit settings: |
| * |
| * CPACR: Enables access to CP10 and CP11 |
| * CONTROL.FPCA: Determines whether the FP extension is active in the |
| * current context: |
| * FPCCR.ASPEN: Enables automatic FP state preservation, then the |
| * processor sets this bit to 1 on successful completion of any FP |
| * instruction. |
| * FPCCR.LSPEN: Enables lazy context save of FP state. When this is |
| * done, the processor reserves space on the stack for the FP state, |
| * but does not save that state information to the stack. |
| * |
| * Software must not change the value of the ASPEN bit or LSPEN bit either: |
| * - the CPACR permits access to CP10 and CP11, that give access to the FP |
| * extension, or |
| * - the CONTROL.FPCA bit is set to 1 |
| * |
| ****************************************************************************/ |
| |
| #ifdef CONFIG_ARCH_FPU |
| #ifndef CONFIG_ARMV7M_LAZYFPU |
| |
| static inline void gd32_fpuconfig(void) |
| { |
| uint32_t regval; |
| |
| /* Set CONTROL.FPCA so that we always get the extended context frame |
| * with the volatile FP registers stacked above the basic context. |
| */ |
| |
| regval = getcontrol(); |
| regval |= CONTROL_FPCA; |
| setcontrol(regval); |
| |
| /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend |
| * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we |
| * are going to turn on CONTROL.FPCA for all contexts. |
| */ |
| |
| regval = getreg32(NVIC_FPCCR); |
| regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN); |
| putreg32(regval, NVIC_FPCCR); |
| |
| /* Enable full access to CP10 and CP11 */ |
| |
| regval = getreg32(NVIC_CPACR); |
| regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); |
| putreg32(regval, NVIC_CPACR); |
| } |
| |
| #else |
| |
| static inline void gd32_fpuconfig(void) |
| { |
| uint32_t regval; |
| |
| /* Clear CONTROL.FPCA so that we do not get the extended context frame |
| * with the volatile FP registers stacked in the saved context. |
| */ |
| |
| regval = getcontrol(); |
| regval &= ~CONTROL_FPCA; |
| setcontrol(regval); |
| |
| /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend |
| * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we |
| * are going to keep CONTROL.FPCA off for all contexts. |
| */ |
| |
| regval = getreg32(NVIC_FPCCR); |
| regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN); |
| putreg32(regval, NVIC_FPCCR); |
| |
| /* Enable full access to CP10 and CP11 */ |
| |
| regval = getreg32(NVIC_CPACR); |
| regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); |
| putreg32(regval, NVIC_CPACR); |
| } |
| |
| #endif |
| |
| #else |
| # define gd32_fpuconfig() |
| #endif |
| |
| /**************************************************************************** |
| * Public Functions |
| ****************************************************************************/ |
| |
| /**************************************************************************** |
| * Name: _start |
| * |
| * Description: |
| * This is the reset entry point. |
| * |
| ****************************************************************************/ |
| |
| void __start(void) |
| { |
| const uint32_t *src; |
| uint32_t *dest; |
| |
| #ifdef CONFIG_ARMV7M_STACKCHECK |
| /* Set the stack limit before we attempt to call any functions */ |
| |
| __asm__ volatile("sub r10, sp, %0" : : |
| "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); |
| #endif |
| |
| /* Clear .bss. We'll do this inline (vs. calling memset) just to be |
| * certain that there are no issues with the state of global variables. |
| */ |
| |
| for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) |
| { |
| *dest++ = 0; |
| } |
| |
| /* Move the initialized data section from his temporary holding spot in |
| * FLASH into the correct place in SRAM. The correct place in SRAM is |
| * give by _sdata and _edata. The temporary location is in FLASH at the |
| * end of all of the other read-only data (.text, .rodata) at _eronly. |
| */ |
| |
| for (src = (const uint32_t *)_eronly, |
| dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; |
| ) |
| { |
| *dest++ = *src++; |
| } |
| |
| /* Configure the UART so that we can get debug output as soon as possible */ |
| |
| gd32_clockconfig(); |
| gd32_fpuconfig(); |
| gd32_lowsetup(); |
| showprogress('A'); |
| |
| #ifdef CONFIG_ARMV7M_ITMSYSLOG |
| /* Perform ARMv7-M ITM SYSLOG initialization */ |
| |
| itm_syslog_initialize(); |
| #endif |
| |
| /* Perform early serial initialization */ |
| |
| #ifdef USE_EARLYSERIALINIT |
| arm_earlyserialinit(); |
| #endif |
| showprogress('B'); |
| |
| /* For the case of the separate user-/kernel-space build, perform whatever |
| * platform specific initialization of the user memory is required. |
| * Normally this just means initializing the user space .data and .bss |
| * segments. |
| */ |
| |
| #ifdef CONFIG_BUILD_PROTECTED |
| gd32_userspace(); |
| showprogress('C'); |
| #endif |
| |
| /* Initialize onboard resources */ |
| |
| gd32_boardinitialize(); |
| showprogress('D'); |
| |
| /* Then start NuttX */ |
| |
| showprogress('\r'); |
| showprogress('\n'); |
| |
| nx_start(); |
| |
| /* Shouldn't get here */ |
| |
| for (; ; ); |
| } |