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   <section id="coresight-hw-assisted-tracing-on-arm">
 <h1>Coresight - HW Assisted Tracing on ARM<a class="headerlink" href="#coresight-hw-assisted-tracing-on-arm" title="Permalink to this heading"></a></h1>
 <section id="overview">
 <h2>Overview<a class="headerlink" href="#overview" title="Permalink to this heading"></a></h2>
 <p>Coresight is an umbrella of technologies allowing for the debugging of ARM
 based SoC.  It includes solutions for JTAG and HW assisted tracing.  This
 document is concerned with the latter.</p>
 <p>HW assisted tracing is becoming increasingly useful when dealing with systems
 that have many SoCs and other components like GPU and DMA engines. Developers
 can monitor the behavior of their software as it runs on the device, view
 real-time data about its execution, and identify and debug issues quickly.</p>
 <p>Coresight omponents are generally categorised as source, link and sinks.
 The source devices generates a compressed stream representing the processor
 instruction path based on tracing scenarios. The link devices are responsible
 for transferring the stream from the source device to the sink device. The sink
 devices serve as as endpoints to the coresight implementation, either storing
 the compressed stream in a memory buffer or creating an interface to the
 outside world where data can be transferred to a host without fear of filling
 up the onboard coresight memory buffer.</p>
 <p>refer to the following document for more details:
 <a class="reference external" href="https://developer.arm.com/documentation/102520/latest/">https://developer.arm.com/documentation/102520/latest/</a></p>
 </section>
 <section id="acronyms-and-classification">
 <h2>Acronyms and Classification<a class="headerlink" href="#acronyms-and-classification" title="Permalink to this heading"></a></h2>
 <p>Acronyms:</p>
 <dl class="simple">
 <dt>PTM:</dt><dd><p>Program Trace Macrocell</p>
 </dd>
 <dt>ETM:</dt><dd><p>Embedded Trace Macrocell</p>
 </dd>
 <dt>STM:</dt><dd><p>System trace Macrocell</p>
 </dd>
 <dt>ETB:</dt><dd><p>Embedded Trace Buffer</p>
 </dd>
 <dt>ITM:</dt><dd><p>Instrumentation Trace Macrocell</p>
 </dd>
 <dt>TPIU:</dt><dd><p>Trace Port Interface Unit</p>
 </dd>
 <dt>TMC-ETR:</dt><dd><p>Trace Memory Controller, configured as Embedded Trace Router</p>
 </dd>
 <dt>TMC-ETF:</dt><dd><p>Trace Memory Controller, configured as Embedded Trace FIFO</p>
 </dd>
 </dl>
 <p>Classification:</p>
 <dl class="simple">
 <dt>Source:</dt><dd><p>ETM, STM, ITM</p>
 </dd>
 <dt>Link:</dt><dd><p>Funnel, replicator, TMC-ETF</p>
 </dd>
 <dt>Sinks:</dt><dd><p>ETB, TPIU, TMC-ETR</p>
 </dd>
 </dl>
 </section>
 <section id="framework-and-implementation">
 <h2>Framework and implementation<a class="headerlink" href="#framework-and-implementation" title="Permalink to this heading"></a></h2>
 <p>The coresight framework provides a central point to represent, configure and
 manage coresight devices on a platform.  Any coresight compliant device can
 register with the framework for as long as they use the right APIs:</p>
 <dl class="c function">
 <dt class="sig sig-object c" id="c.coresight_register">
 <span class="kt"><span class="pre">int</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_register</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">csdev</span></span>, <span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">const</span></span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_desc_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">desc</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_register" title="Permalink to this definition"></a><br /></dt>
 <dd></dd></dl>

 <dl class="c function">
 <dt class="sig sig-object c" id="c.coresight_unregister">
 <span class="kt"><span class="pre">void</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_unregister</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">csdev</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_unregister" title="Permalink to this definition"></a><br /></dt>
 <dd></dd></dl>

 <p><code class="docutils literal notranslate"><span class="pre">struct</span> <span class="pre">coresight_desc</span> <span class="pre">*desc</span></code> describes the type of current coresight device
 and where it connects to. When all the coresight devices are registered,
 devices through the tracing stream path can be enabled by calling:</p>
 <dl class="c function">
 <dt class="sig sig-object c" id="c.coresight_enable">
 <span class="kt"><span class="pre">int</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_enable</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">srcdev</span></span>, <span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">destdev</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_enable" title="Permalink to this definition"></a><br /></dt>
 <dd></dd></dl>

 <p>The <code class="docutils literal notranslate"><span class="pre">coresight_enable</span></code> function will build the path through srcdev and
 destdev according the <code class="docutils literal notranslate"><span class="pre">struct</span> <span class="pre">coresight_desc</span> <span class="pre">*desc</span></code>.</p>
 </section>
 </section>


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	<section id="coresight-hw-assisted-tracing-on-arm">
	<h1>Coresight - HW Assisted Tracing on ARM<a class="headerlink" href="#coresight-hw-assisted-tracing-on-arm" title="Permalink to this heading"></a></h1>
	<section id="overview">
	<h2>Overview<a class="headerlink" href="#overview" title="Permalink to this heading"></a></h2>
	<p>Coresight is an umbrella of technologies allowing for the debugging of ARM
	based SoC. It includes solutions for JTAG and HW assisted tracing. This
	document is concerned with the latter.</p>
	<p>HW assisted tracing is becoming increasingly useful when dealing with systems
	that have many SoCs and other components like GPU and DMA engines. Developers
	can monitor the behavior of their software as it runs on the device, view
	real-time data about its execution, and identify and debug issues quickly.</p>
	<p>Coresight omponents are generally categorised as source, link and sinks.
	The source devices generates a compressed stream representing the processor
	instruction path based on tracing scenarios. The link devices are responsible
	for transferring the stream from the source device to the sink device. The sink
	devices serve as as endpoints to the coresight implementation, either storing
	the compressed stream in a memory buffer or creating an interface to the
	outside world where data can be transferred to a host without fear of filling
	up the onboard coresight memory buffer.</p>
	<p>refer to the following document for more details:
	<a class="reference external" href="https://developer.arm.com/documentation/102520/latest/">https://developer.arm.com/documentation/102520/latest/</a></p>
	</section>
	<section id="acronyms-and-classification">
	<h2>Acronyms and Classification<a class="headerlink" href="#acronyms-and-classification" title="Permalink to this heading"></a></h2>
	<p>Acronyms:</p>
	<dl class="simple">
	<dt>PTM:</dt><dd><p>Program Trace Macrocell</p>
	</dd>
	<dt>ETM:</dt><dd><p>Embedded Trace Macrocell</p>
	</dd>
	<dt>STM:</dt><dd><p>System trace Macrocell</p>
	</dd>
	<dt>ETB:</dt><dd><p>Embedded Trace Buffer</p>
	</dd>
	<dt>ITM:</dt><dd><p>Instrumentation Trace Macrocell</p>
	</dd>
	<dt>TPIU:</dt><dd><p>Trace Port Interface Unit</p>
	</dd>
	<dt>TMC-ETR:</dt><dd><p>Trace Memory Controller, configured as Embedded Trace Router</p>
	</dd>
	<dt>TMC-ETF:</dt><dd><p>Trace Memory Controller, configured as Embedded Trace FIFO</p>
	</dd>
	</dl>
	<p>Classification:</p>
	<dl class="simple">
	<dt>Source:</dt><dd><p>ETM, STM, ITM</p>
	</dd>
	<dt>Link:</dt><dd><p>Funnel, replicator, TMC-ETF</p>
	</dd>
	<dt>Sinks:</dt><dd><p>ETB, TPIU, TMC-ETR</p>
	</dd>
	</dl>
	</section>
	<section id="framework-and-implementation">
	<h2>Framework and implementation<a class="headerlink" href="#framework-and-implementation" title="Permalink to this heading"></a></h2>
	<p>The coresight framework provides a central point to represent, configure and
	manage coresight devices on a platform. Any coresight compliant device can
	register with the framework for as long as they use the right APIs:</p>
	<dl class="c function">
	<dt class="sig sig-object c" id="c.coresight_register">
	<span class="kt"><span class="pre">int</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_register</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre"></span></span><span class="n"><span class="pre">csdev</span></span>, <span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">const</span></span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_desc_s</span></span><span class="w"> </span><span class="p"><span class="pre"></span></span><span class="n"><span class="pre">desc</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_register" title="Permalink to this definition"></a><br /></dt>
	<dd></dd></dl>

	<dl class="c function">
	<dt class="sig sig-object c" id="c.coresight_unregister">
	<span class="kt"><span class="pre">void</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_unregister</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre">*</span></span><span class="n"><span class="pre">csdev</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_unregister" title="Permalink to this definition"></a><br /></dt>
	<dd></dd></dl>

	<p><code class="docutils literal notranslate"><span class="pre">struct</span> <span class="pre">coresight_desc</span> <span class="pre">*desc</span></code> describes the type of current coresight device
	and where it connects to. When all the coresight devices are registered,
	devices through the tracing stream path can be enabled by calling:</p>
	<dl class="c function">
	<dt class="sig sig-object c" id="c.coresight_enable">
	<span class="kt"><span class="pre">int</span></span><span class="w"> </span><span class="sig-name descname"><span class="n"><span class="pre">coresight_enable</span></span></span><span class="sig-paren">(</span><span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre"></span></span><span class="n"><span class="pre">srcdev</span></span>, <span class="pre">FAR</span><span class="w"> </span><span class="k"><span class="pre">struct</span></span><span class="w"> </span><span class="n"><span class="pre">coresight_dev_s</span></span><span class="w"> </span><span class="p"><span class="pre"></span></span><span class="n"><span class="pre">destdev</span></span><span class="sig-paren">)</span><span class="p"><span class="pre">;</span></span><a class="headerlink" href="#c.coresight_enable" title="Permalink to this definition"></a><br /></dt>
	<dd></dd></dl>

	<p>The <code class="docutils literal notranslate"><span class="pre">coresight_enable</span></code> function will build the path through srcdev and
	destdev according the <code class="docutils literal notranslate"><span class="pre">struct</span> <span class="pre">coresight_desc</span> <span class="pre">*desc</span></code>.</p>
	</section>
	</section>


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