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<li class="toctree-l3 current"><a class="current reference internal" href="#">STM32WL5</a><ul>
<li class="toctree-l4"><a class="reference internal" href="#supported-mcus">Supported MCUs</a></li>
<li class="toctree-l4"><a class="reference internal" href="#peripheral-support">Peripheral Support</a><ul>
<li class="toctree-l5"><a class="reference internal" href="#pll">PLL</a></li>
<li class="toctree-l5"><a class="reference internal" href="#lse">LSE</a></li>
<li class="toctree-l5"><a class="reference internal" href="#hsi">HSI</a></li>
<li class="toctree-l5"><a class="reference internal" href="#msi">MSI</a></li>
<li class="toctree-l5"><a class="reference internal" href="#hse">HSE</a></li>
<li class="toctree-l5"><a class="reference internal" href="#rcc">RCC</a></li>
<li class="toctree-l5"><a class="reference internal" href="#syscfg">SYSCFG</a></li>
<li class="toctree-l5"><a class="reference internal" href="#gpio">GPIO</a></li>
<li class="toctree-l5"><a class="reference internal" href="#uart">UART</a></li>
<li class="toctree-l5"><a class="reference internal" href="#ipcc">IPCC</a></li>
<li class="toctree-l5"><a class="reference internal" href="#exti">EXTI</a></li>
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<section id="stm32wl5">
<h1>STM32WL5<a class="headerlink" href="#stm32wl5" title="Permalink to this headline"></a></h1>
<p>The STM32WL5 is a dual CPU (not core!) chip based on ARM Cortex-M4 and
Cortex-M0 with integrated sub-GHz radio for LoRa (G)FSK, (G)MSK and BPSK
modulations.</p>
<p>Only Cortex-M0 has access to radio peripheral. Pipe between CPUs exists
so that radio packets can be exchanged between CPUs. Chip was designed
so that Cortex-M0 cpu handles radio traffic while Cortex-M4 cpu handles
actions based on traffic received. All other peripherals are shared
(like uart, spi, i2c) and both CPUs can initiate them, but it’s required
to be done only by one of them.</p>
<section id="supported-mcus">
<h2>Supported MCUs<a class="headerlink" href="#supported-mcus" title="Permalink to this headline"></a></h2>
<p>STM32WL5 has only two chips in family. STM32WL55 and STM32WL54. Only
difference between them is that STM32WL55 has support for LoRa while
Stm32WL54 does not.</p>
</section>
<section id="peripheral-support">
<h2>Peripheral Support<a class="headerlink" href="#peripheral-support" title="Permalink to this headline"></a></h2>
<p>The following list indicates peripherals supported in NuttX:</p>
<table class="docutils align-default">
<colgroup>
<col style="width: 12%" />
<col style="width: 8%" />
<col style="width: 80%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Peripheral</p></th>
<th class="head"><p>Support</p></th>
<th class="head"><p>Notes</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>IRQs</p></td>
<td><p>Yes</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>GPIO</p></td>
<td><p>Yes</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>EXTI</p></td>
<td><p>Yes</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>HSE</p></td>
<td><p>Yes</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>PLL</p></td>
<td><p>Yes</p></td>
<td><p>Tested &#64; 48MHz</p></td>
</tr>
<tr class="row-odd"><td><p>HSI</p></td>
<td><p>Yes</p></td>
<td><p>Not tested</p></td>
</tr>
<tr class="row-even"><td><p>MSI</p></td>
<td><p>Yes</p></td>
<td><p>Not tested</p></td>
</tr>
<tr class="row-odd"><td><p>LSE</p></td>
<td><p>Yes</p></td>
<td><p>Not tested</p></td>
</tr>
<tr class="row-even"><td><p>RCC</p></td>
<td><p>Yes</p></td>
<td><p>All registers defined, not all peripherals enabled</p></td>
</tr>
<tr class="row-odd"><td><p>SYSCFG</p></td>
<td><p>Yes</p></td>
<td><p>All registers defined, GPIO EXTI works, remapping not tested</p></td>
</tr>
<tr class="row-even"><td><p>USART</p></td>
<td><p>Yes</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>LPUART</p></td>
<td><p>Yes</p></td>
<td><p>full speed with HSE works, low power mode with LSE not implemented</p></td>
</tr>
<tr class="row-even"><td><p>FLASH</p></td>
<td><p>Yes</p></td>
<td><p>Progmem implementation - mtd filesystems like smartfs or nxffs work</p></td>
</tr>
<tr class="row-odd"><td><p>DMA</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>SRAM2</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>SPI</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>I2C</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>RTC</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>Timers</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>PM</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>AES</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>RNG</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>CRC</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>WWDG</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>IWDG</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>ADC</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p>DAC</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-odd"><td><p>IPCC</p></td>
<td><p>No</p></td>
<td></td>
</tr>
<tr class="row-even"><td><p><a class="reference external" href="mailto:Radio&#37;&#52;&#48;CPU0">Radio<span>&#64;</span>CPU0</a></p></td>
<td><p>No</p></td>
<td></td>
</tr>
</tbody>
</table>
<section id="pll">
<h3>PLL<a class="headerlink" href="#pll" title="Permalink to this headline"></a></h3>
<p>PLL is a module that allows MCU to generate higher (or lower) clocks than
provided by the source. For example it can be used to drive system clock
with 48MHz when 8MHz HSE crystal is installed.</p>
</section>
<section id="lse">
<h3>LSE<a class="headerlink" href="#lse" title="Permalink to this headline"></a></h3>
<p>Low speed external crystal. Can be used to clock RTC and/or independent
watchdog (IWDG). LSE is usually 32768Hz high precision crystal.</p>
</section>
<section id="hsi">
<h3>HSI<a class="headerlink" href="#hsi" title="Permalink to this headline"></a></h3>
<p>High speed internal clock. Can be used as a source for sysclk and
internal buses (APB, AHB). This clock source is not as precise or
as stable as HSE, but it cuts down costs by avoiding external
hardware (crystal and capacitors) and is usually good enough if
operating temperatures are stable. It’s clock is fixed at 16MHz.</p>
</section>
<section id="msi">
<h3>MSI<a class="headerlink" href="#msi" title="Permalink to this headline"></a></h3>
<p>Adjustable internal clock. Can be adjusted by software, but it’s
accuracy and stability is even lower than HSI.</p>
</section>
<section id="hse">
<h3>HSE<a class="headerlink" href="#hse" title="Permalink to this headline"></a></h3>
<p>High speed external crystal. Can be used to clock sysclk and internal
buses (APB, AHB). External crystal is more precise and more stable
than HSI.</p>
</section>
<section id="rcc">
<h3>RCC<a class="headerlink" href="#rcc" title="Permalink to this headline"></a></h3>
<p>Reset and clock control. Enables or disables specific peripherals.</p>
</section>
<section id="syscfg">
<h3>SYSCFG<a class="headerlink" href="#syscfg" title="Permalink to this headline"></a></h3>
<p>System configuration controller. Can be used to remap memory or
manage GPIO multiplexer for EXTI.</p>
</section>
<section id="gpio">
<h3>GPIO<a class="headerlink" href="#gpio" title="Permalink to this headline"></a></h3>
<p>Pins can be configured using <code class="xref c c-func docutils literal notranslate"><span class="pre">stm32wl5_configgpio()</span></code> function. Writing
to pins is done by <code class="xref c c-func docutils literal notranslate"><span class="pre">stm32wl5_gpiowrite()</span></code> function and reading is done
by <code class="xref c c-func docutils literal notranslate"><span class="pre">stm32wl5_gpioread()</span></code>.</p>
</section>
<section id="uart">
<h3>UART<a class="headerlink" href="#uart" title="Permalink to this headline"></a></h3>
<p>Universal Asynchronous Receiver/Transmitter module. UART is initialized
automatically during MCU boot.</p>
</section>
<section id="ipcc">
<h3>IPCC<a class="headerlink" href="#ipcc" title="Permalink to this headline"></a></h3>
<p>Inter-processor communication controller. IPCC is used to exchange data
between Cortex-M4 and Cortex-M0 CPUs.</p>
</section>
<section id="exti">
<h3>EXTI<a class="headerlink" href="#exti" title="Permalink to this headline"></a></h3>
<p>Extended interrupts and event controller. Extends interrupts not provided
by NVIC. For example, there is only one interrupt for GPIO5..9 in NVIC,
but thanks to EXTI we can differentiate which GPIO caused interrupt. Such
interrupt first goes through EXTI and is then forwarded to main NVIC.</p>
<p>EXTI for gpio can be enabled via <cite>stm32wl5_gpiosetevent</cite> function.</p>
</section>
<section id="flash">
<h3>FLASH<a class="headerlink" href="#flash" title="Permalink to this headline"></a></h3>
<p>Place where program code lives. Part of flash can also be used to create
small filesystems like nxffs or smartfs to hold persistent data between
reboots without the need of attaching external flash or mmc card. Since
flash has limited number of erases (writes) it’s best to hold there only
data that is no frequently updated (so, configuration is ok, logs are not).</p>
</section>
</section>
<section id="supported-boards">
<h2>Supported Boards<a class="headerlink" href="#supported-boards" title="Permalink to this headline"></a></h2>
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