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| <section id="st-stm32f2"> |
| <h1>ST STM32F2<a class="headerlink" href="#st-stm32f2" title="Permalink to this heading"></a></h1> |
| <section id="supported-mcus"> |
| <h2>Supported MCUs<a class="headerlink" href="#supported-mcus" title="Permalink to this heading"></a></h2> |
| <p>TODO</p> |
| </section> |
| <section id="peripheral-support"> |
| <h2>Peripheral Support<a class="headerlink" href="#peripheral-support" title="Permalink to this heading"></a></h2> |
| <p>The following list indicates peripherals supported in NuttX:</p> |
| <table class="docutils align-default"> |
| <thead> |
| <tr class="row-odd"><th class="head"><p>Peripheral</p></th> |
| <th class="head"><p>Support</p></th> |
| <th class="head"><p>Notes</p></th> |
| </tr> |
| </thead> |
| <tbody> |
| <tr class="row-even"><td><p>FLASH</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>CRC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>PM</p></td> |
| <td><p>?</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>RCC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>GPIO</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>SYSCFG</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>EXTI</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>DMA</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>ADC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>DAC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>DCMI</p></td> |
| <td><p>No</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>TIM</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>IWDG</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>WWDG</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>CRYP</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>RNG</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>HASH</p></td> |
| <td><p>?</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>RTC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>I2C</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>USART</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>SPI</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>SDIO</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>CAN</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>ETH</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>OTG_FS</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-odd"><td><p>OTG_HS</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| <tr class="row-even"><td><p>FSMC</p></td> |
| <td><p>Yes</p></td> |
| <td></td> |
| </tr> |
| </tbody> |
| </table> |
| <section id="memory"> |
| <h3>Memory<a class="headerlink" href="#memory" title="Permalink to this heading"></a></h3> |
| <ul class="simple"> |
| <li><p>CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)</p></li> |
| <li><p>CONFIG_RAM_START - The start address of installed DRAM</p></li> |
| </ul> |
| <p>In addition to internal SRAM, SRAM may also be available through the FSMC. |
| In order to use FSMC SRAM, the following additional things need to be |
| present in the NuttX configuration file:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the |
| FSMC (as opposed to an LCD or FLASH).</p></li> |
| <li><p>CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)</p></li> |
| <li><p>CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)</p></li> |
| <li><p>CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs</p></li> |
| <li><p>CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt |
| stack. If defined, this symbol is the size of the interrupt |
| stack in bytes. If not defined, the user task stacks will be |
| used during interrupt handling.</p></li> |
| <li><p>CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions</p></li> |
| <li><p>CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.</p></li> |
| </ul> |
| </section> |
| <section id="clock"> |
| <h3>Clock<a class="headerlink" href="#clock" title="Permalink to this heading"></a></h3> |
| <ul> |
| <li><p>CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock |
| configuration features.:</p> |
| <div class="highlight-none notranslate"><div class="highlight"><pre><span></span>CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n |
| </pre></div> |
| </div> |
| </li> |
| <li><p>CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation |
| of delay loops</p></li> |
| </ul> |
| </section> |
| <section id="can"> |
| <h3>CAN<a class="headerlink" href="#can" title="Permalink to this heading"></a></h3> |
| <ul class="simple"> |
| <li><p>CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or |
| CONFIG_STM32_CAN2 must also be defined)</p></li> |
| <li><p>CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. |
| Default Standard 11-bit IDs.</p></li> |
| <li><p>CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. |
| Default: 8</p></li> |
| <li><p>CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. |
| Default: 4</p></li> |
| <li><p>CONFIG_STM32_CAN1 - Enable support for CAN1</p></li> |
| <li><p>CONFIG_STM32_CAN2 - Enable support for CAN2</p></li> |
| <li><p>CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. |
| Required if CONFIG_STM32_CAN1 is defined.</p></li> |
| <li><p>CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. |
| Required if CONFIG_STM32_CAN2 is defined.</p></li> |
| <li><p>CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. |
| Default: 6</p></li> |
| <li><p>CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. |
| Default: 7</p></li> |
| <li><p>CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an |
| dump of all CAN registers.</p></li> |
| </ul> |
| </section> |
| <section id="fsmc-sram"> |
| <h3>FSMC SRAM<a class="headerlink" href="#fsmc-sram" title="Permalink to this heading"></a></h3> |
| <p>Internal SRAM is available in all members of the STM32 family. In addition |
| to internal SRAM, SRAM may also be available through the FSMC. In order to |
| use FSMC SRAM, the following additional things need to be present in the |
| NuttX configuration file:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_FSMC=y - Enables the FSMC</p></li> |
| <li><p>CONFIG_STM32_EXTERNAL_RAM=y - Indicates that SRAM is available via the |
| FSMC (as opposed to an LCD or FLASH).</p></li> |
| <li><p>CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC |
| address space</p></li> |
| <li><p>CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC |
| address space</p></li> |
| <li><p>CONFIG_MM_REGIONS - Must be set to a large enough value to |
| include the FSMC SRAM</p></li> |
| </ul> |
| </section> |
| <section id="timers"> |
| <h3>Timers<a class="headerlink" href="#timers" title="Permalink to this heading"></a></h3> |
| <p>Timer devices may be used for different purposes. One special purpose is |
| to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn |
| is defined (as above) then the following may also be defined to indicate that |
| the timer is intended to be used for pulsed output modulation, ADC conversion, |
| or DAC conversion. Note that ADC/DAC require two definition: Not only do you have |
| to assign the timer (n) for used by the ADC or DAC, but then you also have to |
| configure which ADC or DAC (m) it is assigned to.:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14</p></li> |
| <li><p>CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14</p></li> |
| <li><p>CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3</p></li> |
| <li><p>CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14</p></li> |
| <li><p>CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2</p></li> |
| </ul> |
| <p>For each timer that is enabled for PWM usage, we need the following additional |
| configuration settings:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}</p></li> |
| </ul> |
| <p>NOTE: The STM32 timers are each capable of generating different signals on |
| each of the four channels with different duty cycles. That capability is |
| not supported by this driver: Only one output channel per timer.</p> |
| </section> |
| <section id="jtag"> |
| <h3>JTAG<a class="headerlink" href="#jtag" title="Permalink to this heading"></a></h3> |
| <p>JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)</p></li> |
| <li><p>CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) |
| but without JNTRST.</p></li> |
| <li><p>CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled</p></li> |
| </ul> |
| </section> |
| <section id="usart"> |
| <h3>USART<a class="headerlink" href="#usart" title="Permalink to this heading"></a></h3> |
| <p>Options:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UARTm (m=4,5) |
| for the console and ttys0 (default is the USART1).</p></li> |
| <li><p>CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. |
| This specific the size of the receive buffer</p></li> |
| <li><p>CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before |
| being sent. This specific the size of the transmit buffer</p></li> |
| <li><p>CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be</p></li> |
| <li><p>CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.</p></li> |
| <li><p>CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity</p></li> |
| <li><p>CONFIG_U[S]ARTn_2STOP - Two stop bits</p></li> |
| </ul> |
| </section> |
| <section id="spi"> |
| <h3>SPI<a class="headerlink" href="#spi" title="Permalink to this heading"></a></h3> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI |
| support. Non-interrupt-driven, poll-waiting is recommended if the |
| interrupt rate would be to high in the interrupt driven case.</p></li> |
| <li><p>CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance. |
| Cannot be used with CONFIG_STM32_SPI_INTERRUPT.</p></li> |
| </ul> |
| </section> |
| <section id="sdio"> |
| <h3>SDIO<a class="headerlink" href="#sdio" title="Permalink to this heading"></a></h3> |
| <p>Options:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO |
| and CONFIG_STM32_DMA2.</p></li> |
| <li><p>CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128</p></li> |
| <li><p>CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. |
| Default: Medium</p></li> |
| <li><p>CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: |
| 4-bit transfer mode.</p></li> |
| </ul> |
| </section> |
| <section id="eth"> |
| <h3>ETH<a class="headerlink" href="#eth" title="Permalink to this heading"></a></h3> |
| <p>Options:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board</p></li> |
| <li><p>CONFIG_STM32_MII - Support Ethernet MII interface</p></li> |
| <li><p>CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface</p></li> |
| <li><p>CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface</p></li> |
| <li><p>CONFIG_STM32_RMII - Support Ethernet RMII interface</p></li> |
| <li><p>CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode</p></li> |
| <li><p>CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this |
| may be defined to select full duplex mode. Default: half-duplex</p></li> |
| <li><p>CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this |
| may be defined to select 100 MBps speed. Default: 10 Mbps</p></li> |
| <li><p>CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is |
| defined. The PHY status register address may diff from PHY to PHY. This |
| configuration sets the address of the PHY status register.</p></li> |
| <li><p>CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is |
| defined. This provides bit mask indicating 10 or 100MBps speed.</p></li> |
| <li><p>CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is |
| defined. This provides the value of the speed bit(s) indicating 100MBps speed.</p></li> |
| <li><p>CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is |
| defined. This provide bit mask indicating full or half duplex modes.</p></li> |
| <li><p>CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is |
| defined. This provides the value of the mode bits indicating full duplex mode.</p></li> |
| <li><p>CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported |
| but some hooks are indicated with this condition.</p></li> |
| </ul> |
| </section> |
| <section id="usb-otg-fs"> |
| <h3>USB OTG FS<a class="headerlink" href="#usb-otg-fs" title="Permalink to this heading"></a></h3> |
| <p>STM32 USB OTG FS Host Driver Support</p> |
| <p>Pre-requisites:</p> |
| <ul class="simple"> |
| <li><p>CONFIG_USBHOST - Enable general USB host support</p></li> |
| <li><p>CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block</p></li> |
| <li><p>CONFIG_STM32_SYSCFG - Needed</p></li> |
| <li><p>CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. |
| Default 128 (512 bytes)</p></li> |
| <li><p>CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO |
| in 32-bit words. Default 96 (384 bytes)</p></li> |
| <li><p>CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit |
| words. Default 96 (384 bytes)</p></li> |
| <li><p>CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128</p></li> |
| <li><p>CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever |
| want to do that?</p></li> |
| <li><p>CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access |
| debug. Depends on CONFIG_DEBUG_FEATURES.</p></li> |
| <li><p>CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB |
| packets. Depends on CONFIG_DEBUG_FEATURES.</p></li> |
| </ul> |
| </section> |
| </section> |
| <section id="supported-boards"> |
| <h2>Supported Boards<a class="headerlink" href="#supported-boards" title="Permalink to this heading"></a></h2> |
| <div class="toctree-wrapper compound"> |
| <ul> |
| <li class="toctree-l1"><a class="reference internal" href="boards/emw3162/index.html">emw3162</a></li> |
| <li class="toctree-l1"><a class="reference internal" href="boards/nucleo-f207zg/index.html">ST Nucleo F207ZG</a></li> |
| <li class="toctree-l1"><a class="reference internal" href="boards/olimex-stm32-p207/index.html">Olimex STM32-P207</a></li> |
| <li class="toctree-l1"><a class="reference internal" href="boards/photon/index.html">Particle.io Photon</a></li> |
| <li class="toctree-l1"><a class="reference internal" href="boards/stm3220g-eval/index.html">ST STM3220G-EVAL</a></li> |
| </ul> |
| </div> |
| </section> |
| </section> |
| |
| |
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