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| <li class="toctree-l3 current"><a class="current reference internal" href="#">Enjoy Digital LiteX FPGA’s</a><ul> |
| <li class="toctree-l4"><a class="reference internal" href="#toolchain">Toolchain</a><ul> |
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| |
| <section id="enjoy-digital-litex-fpga-s"> |
| <h1>Enjoy Digital LiteX FPGA’s<a class="headerlink" href="#enjoy-digital-litex-fpga-s" title="Permalink to this heading"></a></h1> |
| <p>The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.</p> |
| <p>Information specific to Litex and supported boards can be found on the project’s homepage: <a class="reference external" href="https://github.com/enjoy-digital/litex">https://github.com/enjoy-digital/litex</a></p> |
| <p>Nuttx has basic support for two softcores</p> |
| <blockquote> |
| <div><ul class="simple"> |
| <li><p>vexriscv: FPGA friendly RISC-V ISA CPU implementation</p></li> |
| <li><p>vexriscv_smp: A more fully featured, Linux compatible core.</p></li> |
| </ul> |
| </div></blockquote> |
| <p>Currently, the only configured development board in the Arty A7 <a class="reference external" href="https://digilent.com/reference/programmable-logic/arty-a7/start">https://digilent.com/reference/programmable-logic/arty-a7/start</a>. However, many Litex supported boards |
| should work with either core, requiring minimal adjustment to the configuration.</p> |
| <section id="toolchain"> |
| <h2>Toolchain<a class="headerlink" href="#toolchain" title="Permalink to this heading"></a></h2> |
| <p>Litex projects can be built with a generic RISC-V GCC toolchain. There are currently two options.</p> |
| <section id="prebuilt-toolchain"> |
| <h3>Prebuilt toolchain<a class="headerlink" href="#prebuilt-toolchain" title="Permalink to this heading"></a></h3> |
| <p>A prebuilt RISC-V toolchain from SiFive can be used to build Litex projects:</p> |
| <div class="highlight-none notranslate"><div class="highlight"><pre><span></span># Download the prebuilt toolchain |
| $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz \ |
| > riscv64-unknown-elf-gcc.tar.gz |
| |
| # Unpack the archive |
| $ tar -xf riscv64-unknown-elf-gcc.tar.gz |
| |
| # Add to path |
| $ export PATH="$HOME/path/to/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin:$PATH |
| </pre></div> |
| </div> |
| </section> |
| <section id="custom-built-toolchain"> |
| <h3>Custom built toolchain<a class="headerlink" href="#custom-built-toolchain" title="Permalink to this heading"></a></h3> |
| <p>The toolchain needs to be compiled locally in order to use a more modern version. At the time of writing, |
| the source can be obtained from <a class="reference external" href="https://github.com/riscv-collab/riscv-gnu-toolchain">https://github.com/riscv-collab/riscv-gnu-toolchain</a> and built with the following configuration:</p> |
| <div class="highlight-none notranslate"><div class="highlight"><pre><span></span>$ CFLAGS="-g0 -Os" |
| $ CXXFLAGS="-g0 -Os" |
| $ LDFLAGS="-s" |
| |
| $ ./configure \ |
| CFLAGS_FOR_TARGET='-O2 -mcmodel=medany' \ |
| CXXFLAGS_FOR_TARGET='-O2 -mcmodel=medany' \ |
| --prefix=path/to/install/to \ |
| --with-system-zlib \ |
| --with-arch=rv32ima \ |
| --with-abi=ilp32 |
| |
| $ make |
| </pre></div> |
| </div> |
| <div class="admonition important"> |
| <p class="admonition-title">Important</p> |
| <p>The vexriscv_smp core requires <cite>with-arch=rv32imac</cite>.</p> |
| </div> |
| <p>Check the linked github repository for other options, including building with multilib enabled.</p> |
| </section> |
| </section> |
| <section id="core-specific-information"> |
| <h2>Core specific information<a class="headerlink" href="#core-specific-information" title="Permalink to this heading"></a></h2> |
| <div class="toctree-wrapper compound"> |
| <ul> |
| <li class="toctree-l1"><a class="reference internal" href="cores/vexriscv/index.html">Vexriscv Core</a></li> |
| <li class="toctree-l1"><a class="reference internal" href="cores/vexriscv_smp/index.html">VexRISCV_SMP Core</a></li> |
| </ul> |
| </div> |
| </section> |
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| <h2>Supported Boards<a class="headerlink" href="#supported-boards" title="Permalink to this heading"></a></h2> |
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