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/*
* Copyright (C) 2015-2017, Ambiq Micro
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of itscontributors may be used to endorse
* or promote products derived from thissoftware without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* @file apollo2.h
* @brief CMSIS HeaderFile
* @version 1.0
* @date 13. March 2017
* @note Generated by SVDConv V3.2.53 on Monday, 13.03.2017 18:37:05
* from File 'apollo2.svd',
* last modified on Monday, 13.03.2017 23:37:02
*/
/** @addtogroup Ambiq Micro
* @{
*/
/** @addtogroup apollo2
* @{
*/
#ifndef APOLLO2_H
#define APOLLO2_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum {
/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== apollo2 Specific Interrupt Numbers =========================================== */
BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */
WDT_IRQn = 1, /*!< 1 WDT */
CLKGEN_RTC_IRQn = 2, /*!< 2 CLKGEN_RTC */
VCOMP_IRQn = 3, /*!< 3 VCOMP */
IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */
IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */
IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */
IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */
IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 */
IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 */
IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 */
IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 */
GPIO_IRQn = 12, /*!< 12 GPIO */
CTIMER_IRQn = 13, /*!< 13 CTIMER */
UART0_IRQn = 14, /*!< 14 UART0 */
UART1_IRQn = 15, /*!< 15 UART1 */
ADC_IRQn = 16, /*!< 16 ADC */
PDM_IRQn = 17, /*!< 17 PDM */
STIMER_IRQn = 18, /*!< 18 STIMER */
STIMER_CMPR0_IRQn = 19, /*!< 19 STIMER_CMPR0 */
STIMER_CMPR1_IRQn = 20, /*!< 20 STIMER_CMPR1 */
STIMER_CMPR2_IRQn = 21, /*!< 21 STIMER_CMPR2 */
STIMER_CMPR3_IRQn = 22, /*!< 22 STIMER_CMPR3 */
STIMER_CMPR4_IRQn = 23, /*!< 23 STIMER_CMPR4 */
STIMER_CMPR5_IRQn = 24, /*!< 24 STIMER_CMPR5 */
STIMER_CMPR6_IRQn = 25, /*!< 25 STIMER_CMPR6 */
STIMER_CMPR7_IRQn = 26 /*!< 26 STIMER_CMPR7 */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0100U /*!< CM4 Core Revision */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __FPU_PRESENT 1 /*!< FPU present or not */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
#include "system_apollo2.h" /*!< apollo2 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
#endif
#ifndef __OM /*!< Fallback for older CMSIS versions */
#define __OM __O
#endif
#ifndef __IOM /*!< Fallback for older CMSIS versions */
#define __IOM __IO
#endif
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/**
* @brief Analog Digital Converter Control (ADC)
*/
typedef struct { /*!< (@ 0x50010000) ADC Structure */
union {
__IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */
struct {
__IOM uint32_t ADCEN : 1; /*!< (@ 0x00000000) This bit enables the ADC module. While the ADC
is enabled, the ADCCFG and SLOT Configuration
regsiter settings must remain stable and
unchanged. All configuration register settings,
slot configuration settings and window
comparison settings should be written prior
to setting the ADCEN bit to '1'. */
__IM uint32_t : 1;
__IOM uint32_t RPTEN : 1; /*!< (@ 0x00000002) This bit enables Repeating Scan Mode. */
__IOM uint32_t LPMODE : 1; /*!< (@ 0x00000003) Select power mode to enter between active scans. */
__IOM uint32_t CKMODE : 1; /*!< (@ 0x00000004) Clock mode register */
__IM uint32_t : 3;
__IOM uint32_t REFSEL : 2; /*!< (@ 0x00000008) Select the ADC reference voltage. */
__IM uint32_t : 6;
__IOM uint32_t TRIGSEL : 3; /*!< (@ 0x00000010) Select the ADC trigger source. */
__IOM uint32_t TRIGPOL : 1; /*!< (@ 0x00000013) This bit selects the ADC trigger polarity for
external off chip triggers. */
__IM uint32_t : 4;
__IOM uint32_t CLKSEL : 2; /*!< (@ 0x00000018) Select the source and frequency for the ADC clock.
All values not enumerated below are undefined. */
} CFG_b;
} ;
union {
__IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */
struct {
__IOM uint32_t PWDSTAT : 1; /*!< (@ 0x00000000) Indicates the power-status of the ADC. */
} STAT_b;
} ;
union {
__IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */
struct {
__IOM uint32_t SWT : 8; /*!< (@ 0x00000000) Writing 0x37 to this register generates a software
trigger. */
} SWT_b;
} ;
union {
__IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */
struct {
__IOM uint32_t SLEN0 : 1; /*!< (@ 0x00000000) This bit enables slot 0 for ADC conversions. */
__IOM uint32_t WCEN0 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 0. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL0 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE0 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL0 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL0CFG_b;
} ;
union {
__IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */
struct {
__IOM uint32_t SLEN1 : 1; /*!< (@ 0x00000000) This bit enables slot 1 for ADC conversions. */
__IOM uint32_t WCEN1 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 1. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL1 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE1 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL1 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL1CFG_b;
} ;
union {
__IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */
struct {
__IOM uint32_t SLEN2 : 1; /*!< (@ 0x00000000) This bit enables slot 2 for ADC conversions. */
__IOM uint32_t WCEN2 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 2. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL2 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE2 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL2 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL2CFG_b;
} ;
union {
__IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */
struct {
__IOM uint32_t SLEN3 : 1; /*!< (@ 0x00000000) This bit enables slot 3 for ADC conversions. */
__IOM uint32_t WCEN3 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 3. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL3 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE3 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL3 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL3CFG_b;
} ;
union {
__IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */
struct {
__IOM uint32_t SLEN4 : 1; /*!< (@ 0x00000000) This bit enables slot 4 for ADC conversions. */
__IOM uint32_t WCEN4 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 4. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL4 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE4 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL4 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL4CFG_b;
} ;
union {
__IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */
struct {
__IOM uint32_t SLEN5 : 1; /*!< (@ 0x00000000) This bit enables slot 5 for ADC conversions. */
__IOM uint32_t WCEN5 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 5. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL5 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE5 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL5 : 3; /*!< (@ 0x00000018) Select number of measurements to average in the
accumulate divide module for this slot. */
} SL5CFG_b;
} ;
union {
__IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */
struct {
__IOM uint32_t SLEN6 : 1; /*!< (@ 0x00000000) This bit enables slot 6 for ADC conversions. */
__IOM uint32_t WCEN6 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 6. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL6 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE6 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL6 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL6CFG_b;
} ;
union {
__IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */
struct {
__IOM uint32_t SLEN7 : 1; /*!< (@ 0x00000000) This bit enables slot 7 for ADC conversions. */
__IOM uint32_t WCEN7 : 1; /*!< (@ 0x00000001) This bit enables the window compare function
for slot 7. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL7 : 4; /*!< (@ 0x00000008) Select one of the 14 channel inputs for this
slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE7 : 2; /*!< (@ 0x00000010) Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL7 : 3; /*!< (@ 0x00000018) Select the number of measurements to average
in the accumulate divide module for this
slot. */
} SL7CFG_b;
} ;
union {
__IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */
struct {
__IOM uint32_t ULIM : 20; /*!< (@ 0x00000000) Sets the upper limit for the wondow comparator. */
} WULIM_b;
} ;
union {
__IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */
struct {
__IOM uint32_t LLIM : 20; /*!< (@ 0x00000000) Sets the lower limit for the wondow comparator. */
} WLLIM_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t FIFO; /*!< (@ 0x00000038) FIFO Data and Valid Count Register */
struct {
__IOM uint32_t DATA : 20; /*!< (@ 0x00000000) Oldest data in the FIFO. */
__IOM uint32_t COUNT : 8; /*!< (@ 0x00000014) Number of valid entries in the ADC FIFO. */
__IOM uint32_t SLOTNUM : 3; /*!< (@ 0x0000001C) Slot number associated with this FIFO data. */
__IOM uint32_t RSVD : 1; /*!< (@ 0x0000001F) RESERVED. */
} FIFO_b;
} ;
__IM uint32_t RESERVED1[113];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */
struct {
__IOM uint32_t CNVCMP : 1; /*!< (@ 0x00000000) ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< (@ 0x00000001) ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< (@ 0x00000002) FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< (@ 0x00000003) FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< (@ 0x00000004) Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< (@ 0x00000005) Window comparator voltage incursion interrupt. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */
struct {
__IOM uint32_t CNVCMP : 1; /*!< (@ 0x00000000) ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< (@ 0x00000001) ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< (@ 0x00000002) FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< (@ 0x00000003) FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< (@ 0x00000004) Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< (@ 0x00000005) Window comparator voltage incursion interrupt. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */
struct {
__IOM uint32_t CNVCMP : 1; /*!< (@ 0x00000000) ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< (@ 0x00000001) ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< (@ 0x00000002) FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< (@ 0x00000003) FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< (@ 0x00000004) Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< (@ 0x00000005) Window comparator voltage incursion interrupt. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */
struct {
__IOM uint32_t CNVCMP : 1; /*!< (@ 0x00000000) ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< (@ 0x00000001) ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< (@ 0x00000002) FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< (@ 0x00000003) FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< (@ 0x00000004) Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< (@ 0x00000005) Window comparator voltage incursion interrupt. */
} INTSET_b;
} ;
} ADC_Type; /*!< Size = 528 (0x210) */
/* =========================================================================================================================== */
/* ================ CACHECTRL ================ */
/* =========================================================================================================================== */
/**
* @brief Flash Cache Controller (CACHECTRL)
*/
typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */
union {
__IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */
struct {
__IOM uint32_t ENABLE : 1; /*!< (@ 0x00000000) Enables the flash cache controller. I/D caching
enabled independently. */
__IOM uint32_t LRU : 1; /*!< (@ 0x00000001) Sets the cache replacement policy. 0=LRR (least
recently replaced), 1=LRU (least recently
used). LRR minimizes writes to the TAG
SRAM. */
__IOM uint32_t ENABLE_NC0 : 1; /*!< (@ 0x00000002) Enable Non-cacheable region 0 */
__IOM uint32_t ENABLE_NC1 : 1; /*!< (@ 0x00000003) Enable Non-cacheable region 1 */
__IOM uint32_t CONFIG : 3; /*!< (@ 0x00000004) Sets the cache configuration */
__IOM uint32_t SERIAL : 1; /*!< (@ 0x00000007) Bitfield should always be programmed to 0. */
__IOM uint32_t ICACHE_ENABLE : 1; /*!< (@ 0x00000008) Enable Flash Instruction Caching */
__IOM uint32_t DCACHE_ENABLE : 1; /*!< (@ 0x00000009) Enable Flash Instruction Caching */
__IOM uint32_t CACHE_CLKGATE : 1; /*!< (@ 0x0000000A) Enable clock gating of cache RAMs */
__IOM uint32_t CACHE_LS : 1; /*!< (@ 0x0000000B) Enable LS (light sleep) of cache RAMs. When this
bit is set, the cache's RAMS will be put
into light sleep mode while inactive. NOTE:
if the cache is actively used, this may
have an adverse affect on power since entering/exiting
LS mode may consume more power than would
be saved. */
__IOM uint32_t DLY : 4; /*!< (@ 0x0000000C) Data RAM delay */
__IOM uint32_t SMDLY : 4; /*!< (@ 0x00000010) Data RAM delay */
__IOM uint32_t DATA_CLKGATE : 1; /*!< (@ 0x00000014) Enable clock gating of entire data array */
__IM uint32_t : 3;
__IOM uint32_t ENABLE_MONITOR : 1; /*!< (@ 0x00000018) Enable Cache Monitoring Stats */
} CACHECFG_b;
} ;
union {
__IOM uint32_t FLASHCFG; /*!< (@ 0x00000004) Flash Control Register */
struct {
__IOM uint32_t RD_WAIT : 3; /*!< (@ 0x00000000) Sets read waitstates (HCLK cycles) */
} FLASHCFG_b;
} ;
union {
__IOM uint32_t CACHECTRL; /*!< (@ 0x00000008) Cache Control */
struct {
__IOM uint32_t INVALIDATE : 1; /*!< (@ 0x00000000) Writing a 1 to this bitfield invalidates the
flash cache contents. */
__IOM uint32_t RESET_STAT : 1; /*!< (@ 0x00000001) Writing a 1 to this bitfield will reset the cache
monitor statistics (DMON0-3, IMON0-3).
Statistic gathering can be paused/stopped
by disabling the MONITOR_ENABLE bit in
CACHECFG, which will maintain the count
values until the stats are reset by writing
this bitfield. */
__IOM uint32_t CACHE_READY : 1; /*!< (@ 0x00000002) Cache Ready Status (enabled and not processing
an invalidate operation) */
__IM uint32_t : 1;
__IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< (@ 0x00000004) Flash Sleep Mode Status */
__IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< (@ 0x00000005) Disable Flash Sleep Mode */
__IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< (@ 0x00000006) Enable Flash Sleep Mode */
__IM uint32_t : 1;
__IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< (@ 0x00000008) Flash Sleep Mode Status */
__IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< (@ 0x00000009) Disable Flash Sleep Mode */
__IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< (@ 0x0000000A) Enable Flash Sleep Mode */
} CACHECTRL_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start Address. */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 16; /*!< (@ 0x00000004) Start address for non-cacheable region 0. The
physical address of the start of this region
should be programmed to this register and
must be aligned to a 16-byte boundary (thus
the lower 4 address bits are unused). */
} NCR0START_b;
} ;
union {
__IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 16; /*!< (@ 0x00000004) End address for non-cacheable region 0. The physical
address of the end of this region should
be programmed to this register and must
be aligned to a 16-byte boundary (thus
the lower 4 address bits are unused). */
} NCR0END_b;
} ;
union {
__IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 16; /*!< (@ 0x00000004) Start address for non-cacheable region 1. The
physical address of the start of this region
should be programmed to this register and
must be aligned to a 16-byte boundary (thus
the lower 4 address bits are unused). */
} NCR1START_b;
} ;
union {
__IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 16; /*!< (@ 0x00000004) End address for non-cacheable region 1. The physical
address of the end of this region should
be programmed to this register and must
be aligned to a 16-byte boundary (thus
the lower 4 address bits are unused). */
} NCR1END_b;
} ;
__IM uint32_t RESERVED1[4];
union {
__IOM uint32_t CACHEMODE; /*!< (@ 0x00000030) Flash Cache Mode Register. Used to trim performance/power. */
struct {
__IOM uint32_t THROTTLE1 : 1; /*!< (@ 0x00000000) Disallow cache data RAM writes on tag RAM fill
cycles */
__IOM uint32_t THROTTLE2 : 1; /*!< (@ 0x00000001) Disallow cache data RAM writes on tag RAM read
cycles */
__IOM uint32_t THROTTLE3 : 1; /*!< (@ 0x00000002) Disallow cache data RAM writes on data RAM read
cycles */
__IOM uint32_t THROTTLE4 : 1; /*!< (@ 0x00000003) Disallow Data RAM reads (from line hits) on tag
RAM fill cycles */
__IOM uint32_t THROTTLE5 : 1; /*!< (@ 0x00000004) Disallow Data RAM reads (from line hits) during
lookup read ops */
__IOM uint32_t THROTTLE6 : 1; /*!< (@ 0x00000005) Disallow Simultaneous Data RAM reads (from 2
line hits on each bus) */
} CACHEMODE_b;
} ;
__IM uint32_t RESERVED2[3];
union {
__IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */
struct {
__IOM uint32_t DACCESS_COUNT : 32; /*!< (@ 0x00000000) Total accesses to data cache */
} DMON0_b;
} ;
union {
__IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */
struct {
__IOM uint32_t DLOOKUP_COUNT : 32; /*!< (@ 0x00000000) Total tag lookups from data cache */
} DMON1_b;
} ;
union {
__IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */
struct {
__IOM uint32_t DHIT_COUNT : 32; /*!< (@ 0x00000000) Cache hits from lookup operations */
} DMON2_b;
} ;
union {
__IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */
struct {
__IOM uint32_t DLINE_COUNT : 32; /*!< (@ 0x00000000) Cache hits from line cache */
} DMON3_b;
} ;
union {
__IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */
struct {
__IOM uint32_t IACCESS_COUNT : 32; /*!< (@ 0x00000000) Total accesses to Instruction cache */
} IMON0_b;
} ;
union {
__IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */
struct {
__IOM uint32_t ILOOKUP_COUNT : 32; /*!< (@ 0x00000000) Total tag lookups from Instruction cache */
} IMON1_b;
} ;
union {
__IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */
struct {
__IOM uint32_t IHIT_COUNT : 32; /*!< (@ 0x00000000) Cache hits from lookup operations */
} IMON2_b;
} ;
union {
__IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */
struct {
__IOM uint32_t ILINE_COUNT : 32; /*!< (@ 0x00000000) Cache hits from line cache */
} IMON3_b;
} ;
} CACHECTRL_Type; /*!< Size = 96 (0x60) */
/* =========================================================================================================================== */
/* ================ CTIMER ================ */
/* =========================================================================================================================== */
/**
* @brief Counter/Timer (CTIMER)
*/
typedef struct { /*!< (@ 0x40008000) CTIMER Structure */
union {
__IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA0 : 16; /*!< (@ 0x00000000) Counter/Timer A0. */
__IOM uint32_t CTTMRB0 : 16; /*!< (@ 0x00000010) Counter/Timer B0. */
} TMR0_b;
} ;
union {
__IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */
struct {
__IOM uint32_t CMPR0A0 : 16; /*!< (@ 0x00000000) Counter/Timer A0 Compare Register 0. Holds the
lower limit for timer half A. */
__IOM uint32_t CMPR1A0 : 16; /*!< (@ 0x00000010) Counter/Timer A0 Compare Register 1. Holds the
upper limit for timer half A. */
} CMPRA0_b;
} ;
union {
__IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */
struct {
__IOM uint32_t CMPR0B0 : 16; /*!< (@ 0x00000000) Counter/Timer B0 Compare Register 0. Holds the
lower limit for timer half B. */
__IOM uint32_t CMPR1B0 : 16; /*!< (@ 0x00000010) Counter/Timer B0 Compare Register 1. Holds the
upper limit for timer half B. */
} CMPRB0_b;
} ;
union {
__IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */
struct {
__IOM uint32_t TMRA0EN : 1; /*!< (@ 0x00000000) Counter/Timer A0 Enable bit. */
__IOM uint32_t TMRA0CLK : 5; /*!< (@ 0x00000001) Counter/Timer A0 Clock Select. */
__IOM uint32_t TMRA0FN : 3; /*!< (@ 0x00000006) Counter/Timer A0 Function Select. */
__IOM uint32_t TMRA0IE0 : 1; /*!< (@ 0x00000009) Counter/Timer A0 Interrupt Enable bit based on
COMPR0. */
__IOM uint32_t TMRA0IE1 : 1; /*!< (@ 0x0000000A) Counter/Timer A0 Interrupt Enable bit based on
COMPR1. */
__IOM uint32_t TMRA0CLR : 1; /*!< (@ 0x0000000B) Counter/Timer A0 Clear bit. */
__IOM uint32_t TMRA0POL : 1; /*!< (@ 0x0000000C) Counter/Timer A0 output polarity. */
__IOM uint32_t TMRA0PE : 1; /*!< (@ 0x0000000D) Counter/Timer A0 Output Enable bit. */
__IM uint32_t : 2;
__IOM uint32_t TMRB0EN : 1; /*!< (@ 0x00000010) Counter/Timer B0 Enable bit. */
__IOM uint32_t TMRB0CLK : 5; /*!< (@ 0x00000011) Counter/Timer B0 Clock Select. */
__IOM uint32_t TMRB0FN : 3; /*!< (@ 0x00000016) Counter/Timer B0 Function Select. */
__IOM uint32_t TMRB0IE0 : 1; /*!< (@ 0x00000019) Counter/Timer B0 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB0IE1 : 1; /*!< (@ 0x0000001A) Counter/Timer B0 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB0CLR : 1; /*!< (@ 0x0000001B) Counter/Timer B0 Clear bit. */
__IOM uint32_t TMRB0POL : 1; /*!< (@ 0x0000001C) Counter/Timer B0 output polarity. */
__IOM uint32_t TMRB0PE : 1; /*!< (@ 0x0000001D) Counter/Timer B0 Output Enable bit. */
__IM uint32_t : 1;
__IOM uint32_t CTLINK0 : 1; /*!< (@ 0x0000001F) Counter/Timer A0/B0 Link bit. */
} CTRL0_b;
} ;
union {
__IOM uint32_t TMR1; /*!< (@ 0x00000010) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA1 : 16; /*!< (@ 0x00000000) Counter/Timer A1. */
__IOM uint32_t CTTMRB1 : 16; /*!< (@ 0x00000010) Counter/Timer B1. */
} TMR1_b;
} ;
union {
__IOM uint32_t CMPRA1; /*!< (@ 0x00000014) Counter/Timer A1 Compare Registers */
struct {
__IOM uint32_t CMPR0A1 : 16; /*!< (@ 0x00000000) Counter/Timer A1 Compare Register 0. */
__IOM uint32_t CMPR1A1 : 16; /*!< (@ 0x00000010) Counter/Timer A1 Compare Register 1. */
} CMPRA1_b;
} ;
union {
__IOM uint32_t CMPRB1; /*!< (@ 0x00000018) Counter/Timer B1 Compare Registers */
struct {
__IOM uint32_t CMPR0B1 : 16; /*!< (@ 0x00000000) Counter/Timer B1 Compare Register 0. */
__IOM uint32_t CMPR1B1 : 16; /*!< (@ 0x00000010) Counter/Timer B1 Compare Register 1. */
} CMPRB1_b;
} ;
union {
__IOM uint32_t CTRL1; /*!< (@ 0x0000001C) Counter/Timer Control */
struct {
__IOM uint32_t TMRA1EN : 1; /*!< (@ 0x00000000) Counter/Timer A1 Enable bit. */
__IOM uint32_t TMRA1CLK : 5; /*!< (@ 0x00000001) Counter/Timer A1 Clock Select. */
__IOM uint32_t TMRA1FN : 3; /*!< (@ 0x00000006) Counter/Timer A1 Function Select. */
__IOM uint32_t TMRA1IE0 : 1; /*!< (@ 0x00000009) Counter/Timer A1 Interrupt Enable bit based on
COMPR0. */
__IOM uint32_t TMRA1IE1 : 1; /*!< (@ 0x0000000A) Counter/Timer A1 Interrupt Enable bit based on
COMPR1. */
__IOM uint32_t TMRA1CLR : 1; /*!< (@ 0x0000000B) Counter/Timer A1 Clear bit. */
__IOM uint32_t TMRA1POL : 1; /*!< (@ 0x0000000C) Counter/Timer A1 output polarity. */
__IOM uint32_t TMRA1PE : 1; /*!< (@ 0x0000000D) Counter/Timer A1 Output Enable bit. */
__IM uint32_t : 2;
__IOM uint32_t TMRB1EN : 1; /*!< (@ 0x00000010) Counter/Timer B1 Enable bit. */
__IOM uint32_t TMRB1CLK : 5; /*!< (@ 0x00000011) Counter/Timer B1 Clock Select. */
__IOM uint32_t TMRB1FN : 3; /*!< (@ 0x00000016) Counter/Timer B1 Function Select. */
__IOM uint32_t TMRB1IE0 : 1; /*!< (@ 0x00000019) Counter/Timer B1 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB1IE1 : 1; /*!< (@ 0x0000001A) Counter/Timer B1 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB1CLR : 1; /*!< (@ 0x0000001B) Counter/Timer B1 Clear bit. */
__IOM uint32_t TMRB1POL : 1; /*!< (@ 0x0000001C) Counter/Timer B1 output polarity. */
__IOM uint32_t TMRB1PE : 1; /*!< (@ 0x0000001D) Counter/Timer B1 Output Enable bit. */
__IM uint32_t : 1;
__IOM uint32_t CTLINK1 : 1; /*!< (@ 0x0000001F) Counter/Timer A1/B1 Link bit. */
} CTRL1_b;
} ;
union {
__IOM uint32_t TMR2; /*!< (@ 0x00000020) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA2 : 16; /*!< (@ 0x00000000) Counter/Timer A2. */
__IOM uint32_t CTTMRB2 : 16; /*!< (@ 0x00000010) Counter/Timer B2. */
} TMR2_b;
} ;
union {
__IOM uint32_t CMPRA2; /*!< (@ 0x00000024) Counter/Timer A2 Compare Registers */
struct {
__IOM uint32_t CMPR0A2 : 16; /*!< (@ 0x00000000) Counter/Timer A2 Compare Register 0. */
__IOM uint32_t CMPR1A2 : 16; /*!< (@ 0x00000010) Counter/Timer A2 Compare Register 1. */
} CMPRA2_b;
} ;
union {
__IOM uint32_t CMPRB2; /*!< (@ 0x00000028) Counter/Timer B2 Compare Registers */
struct {
__IOM uint32_t CMPR0B2 : 16; /*!< (@ 0x00000000) Counter/Timer B2 Compare Register 0. */
__IOM uint32_t CMPR1B2 : 16; /*!< (@ 0x00000010) Counter/Timer B2 Compare Register 1. */
} CMPRB2_b;
} ;
union {
__IOM uint32_t CTRL2; /*!< (@ 0x0000002C) Counter/Timer Control */
struct {
__IOM uint32_t TMRA2EN : 1; /*!< (@ 0x00000000) Counter/Timer A2 Enable bit. */
__IOM uint32_t TMRA2CLK : 5; /*!< (@ 0x00000001) Counter/Timer A2 Clock Select. */
__IOM uint32_t TMRA2FN : 3; /*!< (@ 0x00000006) Counter/Timer A2 Function Select. */
__IOM uint32_t TMRA2IE0 : 1; /*!< (@ 0x00000009) Counter/Timer A2 Interrupt Enable bit based on
COMPR0. */
__IOM uint32_t TMRA2IE1 : 1; /*!< (@ 0x0000000A) Counter/Timer A2 Interrupt Enable bit based on
COMPR1. */
__IOM uint32_t TMRA2CLR : 1; /*!< (@ 0x0000000B) Counter/Timer A2 Clear bit. */
__IOM uint32_t TMRA2POL : 1; /*!< (@ 0x0000000C) Counter/Timer A2 output polarity. */
__IOM uint32_t TMRA2PE : 1; /*!< (@ 0x0000000D) Counter/Timer A2 Output Enable bit. */
__IM uint32_t : 2;
__IOM uint32_t TMRB2EN : 1; /*!< (@ 0x00000010) Counter/Timer B2 Enable bit. */
__IOM uint32_t TMRB2CLK : 5; /*!< (@ 0x00000011) Counter/Timer B2 Clock Select. */
__IOM uint32_t TMRB2FN : 3; /*!< (@ 0x00000016) Counter/Timer B2 Function Select. */
__IOM uint32_t TMRB2IE0 : 1; /*!< (@ 0x00000019) Counter/Timer B2 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB2IE1 : 1; /*!< (@ 0x0000001A) Counter/Timer B2 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB2CLR : 1; /*!< (@ 0x0000001B) Counter/Timer B2 Clear bit. */
__IOM uint32_t TMRB2POL : 1; /*!< (@ 0x0000001C) Counter/Timer B2 output polarity. */
__IOM uint32_t TMRB2PE : 1; /*!< (@ 0x0000001D) Counter/Timer B2 Output Enable bit. */
__IM uint32_t : 1;
__IOM uint32_t CTLINK2 : 1; /*!< (@ 0x0000001F) Counter/Timer A2/B2 Link bit. */
} CTRL2_b;
} ;
union {
__IOM uint32_t TMR3; /*!< (@ 0x00000030) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA3 : 16; /*!< (@ 0x00000000) Counter/Timer A3. */
__IOM uint32_t CTTMRB3 : 16; /*!< (@ 0x00000010) Counter/Timer B3. */
} TMR3_b;
} ;
union {
__IOM uint32_t CMPRA3; /*!< (@ 0x00000034) Counter/Timer A3 Compare Registers */
struct {
__IOM uint32_t CMPR0A3 : 16; /*!< (@ 0x00000000) Counter/Timer A3 Compare Register 0. */
__IOM uint32_t CMPR1A3 : 16; /*!< (@ 0x00000010) Counter/Timer A3 Compare Register 1. */
} CMPRA3_b;
} ;
union {
__IOM uint32_t CMPRB3; /*!< (@ 0x00000038) Counter/Timer B3 Compare Registers */
struct {
__IOM uint32_t CMPR0B3 : 16; /*!< (@ 0x00000000) Counter/Timer B3 Compare Register 0. */
__IOM uint32_t CMPR1B3 : 16; /*!< (@ 0x00000010) Counter/Timer B3 Compare Register 1. */
} CMPRB3_b;
} ;
union {
__IOM uint32_t CTRL3; /*!< (@ 0x0000003C) Counter/Timer Control */
struct {
__IOM uint32_t TMRA3EN : 1; /*!< (@ 0x00000000) Counter/Timer A3 Enable bit. */
__IOM uint32_t TMRA3CLK : 5; /*!< (@ 0x00000001) Counter/Timer A3 Clock Select. */
__IOM uint32_t TMRA3FN : 3; /*!< (@ 0x00000006) Counter/Timer A3 Function Select. */
__IOM uint32_t TMRA3IE0 : 1; /*!< (@ 0x00000009) Counter/Timer A3 Interrupt Enable bit based on
COMPR0. */
__IOM uint32_t TMRA3IE1 : 1; /*!< (@ 0x0000000A) Counter/Timer A3 Interrupt Enable bit based on
COMPR1. */
__IOM uint32_t TMRA3CLR : 1; /*!< (@ 0x0000000B) Counter/Timer A3 Clear bit. */
__IOM uint32_t TMRA3POL : 1; /*!< (@ 0x0000000C) Counter/Timer A3 output polarity. */
__IOM uint32_t TMRA3PE : 1; /*!< (@ 0x0000000D) Counter/Timer A3 Output Enable bit. */
__IM uint32_t : 1;
__IOM uint32_t ADCEN : 1; /*!< (@ 0x0000000F) Special Timer A3 enable for ADC function. */
__IOM uint32_t TMRB3EN : 1; /*!< (@ 0x00000010) Counter/Timer B3 Enable bit. */
__IOM uint32_t TMRB3CLK : 5; /*!< (@ 0x00000011) Counter/Timer B3 Clock Select. */
__IOM uint32_t TMRB3FN : 3; /*!< (@ 0x00000016) Counter/Timer B3 Function Select. */
__IOM uint32_t TMRB3IE0 : 1; /*!< (@ 0x00000019) Counter/Timer B3 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB3IE1 : 1; /*!< (@ 0x0000001A) Counter/Timer B3 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB3CLR : 1; /*!< (@ 0x0000001B) Counter/Timer B3 Clear bit. */
__IOM uint32_t TMRB3POL : 1; /*!< (@ 0x0000001C) Counter/Timer B3 output polarity. */
__IOM uint32_t TMRB3PE : 1; /*!< (@ 0x0000001D) Counter/Timer B3 Output Enable bit. */
__IM uint32_t : 1;
__IOM uint32_t CTLINK3 : 1; /*!< (@ 0x0000001F) Counter/Timer A3/B3 Link bit. */
} CTRL3_b;
} ;
__IM uint32_t RESERVED[48];
union {
__IOM uint32_t STCFG; /*!< (@ 0x00000100) Configuration Register */
struct {
__IOM uint32_t CLKSEL : 4; /*!< (@ 0x00000000) Selects an appropriate clock source and divider
to use for the System Timer clock. */
__IM uint32_t : 4;
__IOM uint32_t COMPARE_A_EN : 1; /*!< (@ 0x00000008) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_B_EN : 1; /*!< (@ 0x00000009) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_C_EN : 1; /*!< (@ 0x0000000A) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_D_EN : 1; /*!< (@ 0x0000000B) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_E_EN : 1; /*!< (@ 0x0000000C) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_F_EN : 1; /*!< (@ 0x0000000D) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_G_EN : 1; /*!< (@ 0x0000000E) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IOM uint32_t COMPARE_H_EN : 1; /*!< (@ 0x0000000F) Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled,
the interrupt status is set once the comparision
is met. */
__IM uint32_t : 14;
__IOM uint32_t CLEAR : 1; /*!< (@ 0x0000001E) Set this bit to one to clear the System Timer
register. If this bit is set to '1', the
system timer register will stay cleared.
It needs to be set to '0' for the system
timer to start running. */
__IOM uint32_t FREEZE : 1; /*!< (@ 0x0000001F) Set this bit to one to freeze the clock input
to the COUNTER register. Once frozen, the
value can be safely written from the MCU.
Unfreeze to resume. */
} STCFG_b;
} ;
union {
__IOM uint32_t STTMR; /*!< (@ 0x00000104) System Timer Count Register (Real Time Counter) */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Value of the 32-bit counter as it ticks over. */
} STTMR_b;
} ;
union {
__IOM uint32_t CAPTURE_CONTROL; /*!< (@ 0x00000108) Capture Control Register */
struct {
__IOM uint32_t CAPTURE_A : 1; /*!< (@ 0x00000000) Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE_B : 1; /*!< (@ 0x00000001) Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE_C : 1; /*!< (@ 0x00000002) Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE_D : 1; /*!< (@ 0x00000003) Selects whether capture is enabled for the specified
capture register. */
} CAPTURE_CONTROL_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t SCMPR0; /*!< (@ 0x00000110) Compare Register A */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_A_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR0_b;
} ;
union {
__IOM uint32_t SCMPR1; /*!< (@ 0x00000114) Compare Register B */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_B_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR1_b;
} ;
union {
__IOM uint32_t SCMPR2; /*!< (@ 0x00000118) Compare Register C */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_C_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR2_b;
} ;
union {
__IOM uint32_t SCMPR3; /*!< (@ 0x0000011C) Compare Register D */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_D_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR3_b;
} ;
union {
__IOM uint32_t SCMPR4; /*!< (@ 0x00000120) Compare Register E */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_E_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR4_b;
} ;
union {
__IOM uint32_t SCMPR5; /*!< (@ 0x00000124) Compare Register F */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_F_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR5_b;
} ;
union {
__IOM uint32_t SCMPR6; /*!< (@ 0x00000128) Compare Register G */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_G_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR6_b;
} ;
union {
__IOM uint32_t SCMPR7; /*!< (@ 0x0000012C) Compare Register H */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Compare this value to the value in the COUNTER
register according to the match criterion,
as selected in the COMPARE_H_EN bit in
the REG_CTIMER_STCGF register. */
} SCMPR7_b;
} ;
__IM uint32_t RESERVED2[44];
union {
__IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) Capture Register A */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Whenever the event is detected, the value in
the COUNTER is copied into this register
and the corresponding interrupt status
bit is set. */
} SCAPT0_b;
} ;
union {
__IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) Capture Register B */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Whenever the event is detected, the value in
the COUNTER is copied into this register
and the corresponding interrupt status
bit is set. */
} SCAPT1_b;
} ;
union {
__IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) Capture Register C */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Whenever the event is detected, the value in
the COUNTER is copied into this register
and the corresponding interrupt status
bit is set. */
} SCAPT2_b;
} ;
union {
__IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) Capture Register D */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Whenever the event is detected, the value in
the COUNTER is copied into this register
and the corresponding interrupt status
bit is set. */
} SCAPT3_b;
} ;
union {
__IOM uint32_t SNVR0; /*!< (@ 0x000001F0) System Timer NVRAM_A Register */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Value of the 32-bit counter as it ticks over. */
} SNVR0_b;
} ;
union {
__IOM uint32_t SNVR1; /*!< (@ 0x000001F4) System Timer NVRAM_B Register */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Value of the 32-bit counter as it ticks over. */
} SNVR1_b;
} ;
union {
__IOM uint32_t SNVR2; /*!< (@ 0x000001F8) System Timer NVRAM_C Register */
struct {
__IOM uint32_t VALUE : 32; /*!< (@ 0x00000000) Value of the 32-bit counter as it ticks over. */
} SNVR2_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< (@ 0x00000000) Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< (@ 0x00000001) Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< (@ 0x00000002) Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< (@ 0x00000003) Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< (@ 0x00000004) Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< (@ 0x00000005) Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< (@ 0x00000006) Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< (@ 0x00000007) Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< (@ 0x00000008) Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< (@ 0x00000009) Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< (@ 0x0000000A) Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< (@ 0x0000000B) Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< (@ 0x0000000C) Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< (@ 0x0000000D) Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< (@ 0x0000000E) Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< (@ 0x0000000F) Counter/Timer B3 interrupt based on COMPR1. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< (@ 0x00000000) Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< (@ 0x00000001) Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< (@ 0x00000002) Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< (@ 0x00000003) Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< (@ 0x00000004) Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< (@ 0x00000005) Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< (@ 0x00000006) Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< (@ 0x00000007) Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< (@ 0x00000008) Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< (@ 0x00000009) Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< (@ 0x0000000A) Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< (@ 0x0000000B) Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< (@ 0x0000000C) Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< (@ 0x0000000D) Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< (@ 0x0000000E) Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< (@ 0x0000000F) Counter/Timer B3 interrupt based on COMPR1. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< (@ 0x00000000) Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< (@ 0x00000001) Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< (@ 0x00000002) Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< (@ 0x00000003) Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< (@ 0x00000004) Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< (@ 0x00000005) Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< (@ 0x00000006) Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< (@ 0x00000007) Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< (@ 0x00000008) Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< (@ 0x00000009) Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< (@ 0x0000000A) Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< (@ 0x0000000B) Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< (@ 0x0000000C) Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< (@ 0x0000000D) Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< (@ 0x0000000E) Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< (@ 0x0000000F) Counter/Timer B3 interrupt based on COMPR1. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< (@ 0x00000000) Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< (@ 0x00000001) Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< (@ 0x00000002) Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< (@ 0x00000003) Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< (@ 0x00000004) Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< (@ 0x00000005) Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< (@ 0x00000006) Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< (@ 0x00000007) Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< (@ 0x00000008) Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< (@ 0x00000009) Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< (@ 0x0000000A) Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< (@ 0x0000000B) Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< (@ 0x0000000C) Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< (@ 0x0000000D) Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< (@ 0x0000000E) Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< (@ 0x0000000F) Counter/Timer B3 interrupt based on COMPR1. */
} INTSET_b;
} ;
__IM uint32_t RESERVED4[60];
union {
__IOM uint32_t STMINTEN; /*!< (@ 0x00000300) STIMER Interrupt registers: Enable */
struct {
__IOM uint32_t COMPAREA : 1; /*!< (@ 0x00000000) COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< (@ 0x00000001) COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< (@ 0x00000002) COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< (@ 0x00000003) COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< (@ 0x00000004) COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< (@ 0x00000005) COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< (@ 0x00000006) COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< (@ 0x00000007) COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< (@ 0x00000008) COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< (@ 0x00000009) CAPTURE register A has grabbed the value in the
counter */
__IOM uint32_t CAPTUREB : 1; /*!< (@ 0x0000000A) CAPTURE register B has grabbed the value in the
counter */
__IOM uint32_t CAPTUREC : 1; /*!< (@ 0x0000000B) CAPTURE register C has grabbed the value in the
counter */
__IOM uint32_t CAPTURED : 1; /*!< (@ 0x0000000C) CAPTURE register D has grabbed the value in the
counter */
} STMINTEN_b;
} ;
union {
__IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) STIMER Interrupt registers: Status */
struct {
__IOM uint32_t COMPAREA : 1; /*!< (@ 0x00000000) COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< (@ 0x00000001) COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< (@ 0x00000002) COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< (@ 0x00000003) COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< (@ 0x00000004) COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< (@ 0x00000005) COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< (@ 0x00000006) COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< (@ 0x00000007) COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< (@ 0x00000008) COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< (@ 0x00000009) CAPTURE register A has grabbed the value in the
counter */
__IOM uint32_t CAPTUREB : 1; /*!< (@ 0x0000000A) CAPTURE register B has grabbed the value in the
counter */
__IOM uint32_t CAPTUREC : 1; /*!< (@ 0x0000000B) CAPTURE register C has grabbed the value in the
counter */
__IOM uint32_t CAPTURED : 1; /*!< (@ 0x0000000C) CAPTURE register D has grabbed the value in the
counter */
} STMINTSTAT_b;
} ;
union {
__IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) STIMER Interrupt registers: Clear */
struct {
__IOM uint32_t COMPAREA : 1; /*!< (@ 0x00000000) COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< (@ 0x00000001) COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< (@ 0x00000002) COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< (@ 0x00000003) COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< (@ 0x00000004) COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< (@ 0x00000005) COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< (@ 0x00000006) COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< (@ 0x00000007) COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< (@ 0x00000008) COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< (@ 0x00000009) CAPTURE register A has grabbed the value in the
counter */
__IOM uint32_t CAPTUREB : 1; /*!< (@ 0x0000000A) CAPTURE register B has grabbed the value in the
counter */
__IOM uint32_t CAPTUREC : 1; /*!< (@ 0x0000000B) CAPTURE register C has grabbed the value in the
counter */
__IOM uint32_t CAPTURED : 1; /*!< (@ 0x0000000C) CAPTURE register D has grabbed the value in the
counter */
} STMINTCLR_b;
} ;
union {
__IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) STIMER Interrupt registers: Set */
struct {
__IOM uint32_t COMPAREA : 1; /*!< (@ 0x00000000) COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< (@ 0x00000001) COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< (@ 0x00000002) COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< (@ 0x00000003) COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< (@ 0x00000004) COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< (@ 0x00000005) COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< (@ 0x00000006) COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< (@ 0x00000007) COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< (@ 0x00000008) COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< (@ 0x00000009) CAPTURE register A has grabbed the value in the
counter */
__IOM uint32_t CAPTUREB : 1; /*!< (@ 0x0000000A) CAPTURE register B has grabbed the value in the
counter */
__IOM uint32_t CAPTUREC : 1; /*!< (@ 0x0000000B) CAPTURE register C has grabbed the value in the
counter */
__IOM uint32_t CAPTURED : 1; /*!< (@ 0x0000000C) CAPTURE register D has grabbed the value in the
counter */
} STMINTSET_b;
} ;
} CTIMER_Type; /*!< Size = 784 (0x310) */
/* =========================================================================================================================== */
/* ================ GPIO ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose IO (GPIO)
*/
typedef struct { /*!< (@ 0x40010000) GPIO Structure */
union {
__IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A */
struct {
__IOM uint32_t PAD0PULL : 1; /*!< (@ 0x00000000) Pad 0 pullup enable */
__IOM uint32_t PAD0INPEN : 1; /*!< (@ 0x00000001) Pad 0 input enable */
__IOM uint32_t PAD0STRNG : 1; /*!< (@ 0x00000002) Pad 0 drive strength */
__IOM uint32_t PAD0FNCSEL : 3; /*!< (@ 0x00000003) Pad 0 function select */
__IOM uint32_t PAD0RSEL : 2; /*!< (@ 0x00000006) Pad 0 pullup resistor selection. */
__IOM uint32_t PAD1PULL : 1; /*!< (@ 0x00000008) Pad 1 pullup enable */
__IOM uint32_t PAD1INPEN : 1; /*!< (@ 0x00000009) Pad 1 input enable */
__IOM uint32_t PAD1STRNG : 1; /*!< (@ 0x0000000A) Pad 1 drive strength */
__IOM uint32_t PAD1FNCSEL : 3; /*!< (@ 0x0000000B) Pad 1 function select */
__IOM uint32_t PAD1RSEL : 2; /*!< (@ 0x0000000E) Pad 1 pullup resistor selection. */
__IOM uint32_t PAD2PULL : 1; /*!< (@ 0x00000010) Pad 2 pullup enable */
__IOM uint32_t PAD2INPEN : 1; /*!< (@ 0x00000011) Pad 2 input enable */
__IOM uint32_t PAD2STRNG : 1; /*!< (@ 0x00000012) Pad 2 drive strength */
__IOM uint32_t PAD2FNCSEL : 3; /*!< (@ 0x00000013) Pad 2 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD3PULL : 1; /*!< (@ 0x00000018) Pad 3 pullup enable */
__IOM uint32_t PAD3INPEN : 1; /*!< (@ 0x00000019) Pad 3 input enable. */
__IOM uint32_t PAD3STRNG : 1; /*!< (@ 0x0000001A) Pad 3 drive strength. */
__IOM uint32_t PAD3FNCSEL : 3; /*!< (@ 0x0000001B) Pad 3 function select */
} PADREGA_b;
} ;
union {
__IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B */
struct {
__IOM uint32_t PAD4PULL : 1; /*!< (@ 0x00000000) Pad 4 pullup enable */
__IOM uint32_t PAD4INPEN : 1; /*!< (@ 0x00000001) Pad 4 input enable */
__IOM uint32_t PAD4STRNG : 1; /*!< (@ 0x00000002) Pad 4 drive strength */
__IOM uint32_t PAD4FNCSEL : 3; /*!< (@ 0x00000003) Pad 4 function select */
__IM uint32_t : 1;
__IOM uint32_t PAD4PWRDN : 1; /*!< (@ 0x00000007) Pad 4 VSS power switch enable */
__IOM uint32_t PAD5PULL : 1; /*!< (@ 0x00000008) Pad 5 pullup enable */
__IOM uint32_t PAD5INPEN : 1; /*!< (@ 0x00000009) Pad 5 input enable */
__IOM uint32_t PAD5STRNG : 1; /*!< (@ 0x0000000A) Pad 5 drive strength */
__IOM uint32_t PAD5FNCSEL : 3; /*!< (@ 0x0000000B) Pad 5 function select */
__IOM uint32_t PAD5RSEL : 2; /*!< (@ 0x0000000E) Pad 5 pullup resistor selection. */
__IOM uint32_t PAD6PULL : 1; /*!< (@ 0x00000010) Pad 6 pullup enable */
__IOM uint32_t PAD6INPEN : 1; /*!< (@ 0x00000011) Pad 6 input enable */
__IOM uint32_t PAD6STRNG : 1; /*!< (@ 0x00000012) Pad 6 drive strength */
__IOM uint32_t PAD6FNCSEL : 3; /*!< (@ 0x00000013) Pad 6 function select */
__IOM uint32_t PAD6RSEL : 2; /*!< (@ 0x00000016) Pad 6 pullup resistor selection. */
__IOM uint32_t PAD7PULL : 1; /*!< (@ 0x00000018) Pad 7 pullup enable */
__IOM uint32_t PAD7INPEN : 1; /*!< (@ 0x00000019) Pad 7 input enable */
__IOM uint32_t PAD7STRNG : 1; /*!< (@ 0x0000001A) Pad 7 drive strentgh */
__IOM uint32_t PAD7FNCSEL : 3; /*!< (@ 0x0000001B) Pad 7 function select */
} PADREGB_b;
} ;
union {
__IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C */
struct {
__IOM uint32_t PAD8PULL : 1; /*!< (@ 0x00000000) Pad 8 pullup enable */
__IOM uint32_t PAD8INPEN : 1; /*!< (@ 0x00000001) Pad 8 input enable */
__IOM uint32_t PAD8STRNG : 1; /*!< (@ 0x00000002) Pad 8 drive strength */
__IOM uint32_t PAD8FNCSEL : 3; /*!< (@ 0x00000003) Pad 8 function select */
__IOM uint32_t PAD8RSEL : 2; /*!< (@ 0x00000006) Pad 8 pullup resistor selection. */
__IOM uint32_t PAD9PULL : 1; /*!< (@ 0x00000008) Pad 9 pullup enable */
__IOM uint32_t PAD9INPEN : 1; /*!< (@ 0x00000009) Pad 9 input enable */
__IOM uint32_t PAD9STRNG : 1; /*!< (@ 0x0000000A) Pad 9 drive strength */
__IOM uint32_t PAD9FNCSEL : 3; /*!< (@ 0x0000000B) Pad 9 function select */
__IOM uint32_t PAD9RSEL : 2; /*!< (@ 0x0000000E) Pad 9 pullup resistor selection */
__IOM uint32_t PAD10PULL : 1; /*!< (@ 0x00000010) Pad 10 pullup enable */
__IOM uint32_t PAD10INPEN : 1; /*!< (@ 0x00000011) Pad 10 input enable */
__IOM uint32_t PAD10STRNG : 1; /*!< (@ 0x00000012) Pad 10 drive strength */
__IOM uint32_t PAD10FNCSEL : 3; /*!< (@ 0x00000013) Pad 10 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD11PULL : 1; /*!< (@ 0x00000018) Pad 11 pullup enable */
__IOM uint32_t PAD11INPEN : 1; /*!< (@ 0x00000019) Pad 11 input enable */
__IOM uint32_t PAD11STRNG : 1; /*!< (@ 0x0000001A) Pad 11 drive strentgh */
__IOM uint32_t PAD11FNCSEL : 3; /*!< (@ 0x0000001B) Pad 11 function select */
} PADREGC_b;
} ;
union {
__IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D */
struct {
__IOM uint32_t PAD12PULL : 1; /*!< (@ 0x00000000) Pad 12 pullup enable */
__IOM uint32_t PAD12INPEN : 1; /*!< (@ 0x00000001) Pad 12 input enable */
__IOM uint32_t PAD12STRNG : 1; /*!< (@ 0x00000002) Pad 12 drive strength */
__IOM uint32_t PAD12FNCSEL : 3; /*!< (@ 0x00000003) Pad 12 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD13PULL : 1; /*!< (@ 0x00000008) Pad 13 pullup enable */
__IOM uint32_t PAD13INPEN : 1; /*!< (@ 0x00000009) Pad 13 input enable */
__IOM uint32_t PAD13STRNG : 1; /*!< (@ 0x0000000A) Pad 13 drive strength */
__IOM uint32_t PAD13FNCSEL : 3; /*!< (@ 0x0000000B) Pad 13 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD14PULL : 1; /*!< (@ 0x00000010) Pad 14 pullup enable */
__IOM uint32_t PAD14INPEN : 1; /*!< (@ 0x00000011) Pad 14 input enable */
__IOM uint32_t PAD14STRNG : 1; /*!< (@ 0x00000012) Pad 14 drive strength */
__IOM uint32_t PAD14FNCSEL : 3; /*!< (@ 0x00000013) Pad 14 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD15PULL : 1; /*!< (@ 0x00000018) Pad 15 pullup enable */
__IOM uint32_t PAD15INPEN : 1; /*!< (@ 0x00000019) Pad 15 input enable */
__IOM uint32_t PAD15STRNG : 1; /*!< (@ 0x0000001A) Pad 15 drive strentgh */
__IOM uint32_t PAD15FNCSEL : 3; /*!< (@ 0x0000001B) Pad 15 function select */
} PADREGD_b;
} ;
union {
__IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E */
struct {
__IOM uint32_t PAD16PULL : 1; /*!< (@ 0x00000000) Pad 16 pullup enable */
__IOM uint32_t PAD16INPEN : 1; /*!< (@ 0x00000001) Pad 16 input enable */
__IOM uint32_t PAD16STRNG : 1; /*!< (@ 0x00000002) Pad 16 drive strength */
__IOM uint32_t PAD16FNCSEL : 3; /*!< (@ 0x00000003) Pad 16 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD17PULL : 1; /*!< (@ 0x00000008) Pad 17 pullup enable */
__IOM uint32_t PAD17INPEN : 1; /*!< (@ 0x00000009) Pad 17 input enable */
__IOM uint32_t PAD17STRNG : 1; /*!< (@ 0x0000000A) Pad 17 drive strength */
__IOM uint32_t PAD17FNCSEL : 3; /*!< (@ 0x0000000B) Pad 17 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD18PULL : 1; /*!< (@ 0x00000010) Pad 18 pullup enable */
__IOM uint32_t PAD18INPEN : 1; /*!< (@ 0x00000011) Pad 18 input enable */
__IOM uint32_t PAD18STRNG : 1; /*!< (@ 0x00000012) Pad 18 drive strength */
__IOM uint32_t PAD18FNCSEL : 3; /*!< (@ 0x00000013) Pad 18 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD19PULL : 1; /*!< (@ 0x00000018) Pad 19 pullup enable */
__IOM uint32_t PAD19INPEN : 1; /*!< (@ 0x00000019) Pad 19 input enable */
__IOM uint32_t PAD19STRNG : 1; /*!< (@ 0x0000001A) Pad 19 drive strentgh */
__IOM uint32_t PAD19FNCSEL : 3; /*!< (@ 0x0000001B) Pad 19 function select */
} PADREGE_b;
} ;
union {
__IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F */
struct {
__IOM uint32_t PAD20PULL : 1; /*!< (@ 0x00000000) Pad 20 pulldown enable */
__IOM uint32_t PAD20INPEN : 1; /*!< (@ 0x00000001) Pad 20 input enable */
__IOM uint32_t PAD20STRNG : 1; /*!< (@ 0x00000002) Pad 20 drive strength */
__IOM uint32_t PAD20FNCSEL : 3; /*!< (@ 0x00000003) Pad 20 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD21PULL : 1; /*!< (@ 0x00000008) Pad 21 pullup enable */
__IOM uint32_t PAD21INPEN : 1; /*!< (@ 0x00000009) Pad 21 input enable */
__IOM uint32_t PAD21STRNG : 1; /*!< (@ 0x0000000A) Pad 21 drive strength */
__IOM uint32_t PAD21FNCSEL : 3; /*!< (@ 0x0000000B) Pad 21 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD22PULL : 1; /*!< (@ 0x00000010) Pad 22 pullup enable */
__IOM uint32_t PAD22INPEN : 1; /*!< (@ 0x00000011) Pad 22 input enable */
__IOM uint32_t PAD22STRNG : 1; /*!< (@ 0x00000012) Pad 22 drive strength */
__IOM uint32_t PAD22FNCSEL : 3; /*!< (@ 0x00000013) Pad 22 function select */
__IM uint32_t : 1;
__IOM uint32_t PAD22PWRUP : 1; /*!< (@ 0x00000017) Pad 22 upper power switch enable */
__IOM uint32_t PAD23PULL : 1; /*!< (@ 0x00000018) Pad 23 pullup enable */
__IOM uint32_t PAD23INPEN : 1; /*!< (@ 0x00000019) Pad 23 input enable */
__IOM uint32_t PAD23STRNG : 1; /*!< (@ 0x0000001A) Pad 23 drive strentgh */
__IOM uint32_t PAD23FNCSEL : 3; /*!< (@ 0x0000001B) Pad 23 function select */
} PADREGF_b;
} ;
union {
__IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G */
struct {
__IOM uint32_t PAD24PULL : 1; /*!< (@ 0x00000000) Pad 24 pullup enable */
__IOM uint32_t PAD24INPEN : 1; /*!< (@ 0x00000001) Pad 24 input enable */
__IOM uint32_t PAD24STRNG : 1; /*!< (@ 0x00000002) Pad 24 drive strength */
__IOM uint32_t PAD24FNCSEL : 3; /*!< (@ 0x00000003) Pad 24 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD25PULL : 1; /*!< (@ 0x00000008) Pad 25 pullup enable */
__IOM uint32_t PAD25INPEN : 1; /*!< (@ 0x00000009) Pad 25 input enable */
__IOM uint32_t PAD25STRNG : 1; /*!< (@ 0x0000000A) Pad 25 drive strength */
__IOM uint32_t PAD25FNCSEL : 3; /*!< (@ 0x0000000B) Pad 25 function select */
__IOM uint32_t PAD25RSEL : 2; /*!< (@ 0x0000000E) Pad 25 pullup resistor selection. */
__IOM uint32_t PAD26PULL : 1; /*!< (@ 0x00000010) Pad 26 pullup enable */
__IOM uint32_t PAD26INPEN : 1; /*!< (@ 0x00000011) Pad 26 input enable */
__IOM uint32_t PAD26STRNG : 1; /*!< (@ 0x00000012) Pad 26 drive strength */
__IOM uint32_t PAD26FNCSEL : 3; /*!< (@ 0x00000013) Pad 26 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD27PULL : 1; /*!< (@ 0x00000018) Pad 27 pullup enable */
__IOM uint32_t PAD27INPEN : 1; /*!< (@ 0x00000019) Pad 27 input enable */
__IOM uint32_t PAD27STRNG : 1; /*!< (@ 0x0000001A) Pad 27 drive strentgh */
__IOM uint32_t PAD27FNCSEL : 3; /*!< (@ 0x0000001B) Pad 27 function select */
__IOM uint32_t PAD27RSEL : 2; /*!< (@ 0x0000001E) Pad 27 pullup resistor selection. */
} PADREGG_b;
} ;
union {
__IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H */
struct {
__IOM uint32_t PAD28PULL : 1; /*!< (@ 0x00000000) Pad 28 pullup enable */
__IOM uint32_t PAD28INPEN : 1; /*!< (@ 0x00000001) Pad 28 input enable */
__IOM uint32_t PAD28STRNG : 1; /*!< (@ 0x00000002) Pad 28 drive strength */
__IOM uint32_t PAD28FNCSEL : 3; /*!< (@ 0x00000003) Pad 28 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD29PULL : 1; /*!< (@ 0x00000008) Pad 29 pullup enable */
__IOM uint32_t PAD29INPEN : 1; /*!< (@ 0x00000009) Pad 29 input enable */
__IOM uint32_t PAD29STRNG : 1; /*!< (@ 0x0000000A) Pad 29 drive strength */
__IOM uint32_t PAD29FNCSEL : 3; /*!< (@ 0x0000000B) Pad 29 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD30PULL : 1; /*!< (@ 0x00000010) Pad 30 pullup enable */
__IOM uint32_t PAD30INPEN : 1; /*!< (@ 0x00000011) Pad 30 input enable */
__IOM uint32_t PAD30STRNG : 1; /*!< (@ 0x00000012) Pad 30 drive strength */
__IOM uint32_t PAD30FNCSEL : 3; /*!< (@ 0x00000013) Pad 30 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD31PULL : 1; /*!< (@ 0x00000018) Pad 31 pullup enable */
__IOM uint32_t PAD31INPEN : 1; /*!< (@ 0x00000019) Pad 31 input enable */
__IOM uint32_t PAD31STRNG : 1; /*!< (@ 0x0000001A) Pad 31 drive strentgh */
__IOM uint32_t PAD31FNCSEL : 3; /*!< (@ 0x0000001B) Pad 31 function select */
} PADREGH_b;
} ;
union {
__IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I */
struct {
__IOM uint32_t PAD32PULL : 1; /*!< (@ 0x00000000) Pad 32 pullup enable */
__IOM uint32_t PAD32INPEN : 1; /*!< (@ 0x00000001) Pad 32 input enable */
__IOM uint32_t PAD32STRNG : 1; /*!< (@ 0x00000002) Pad 32 drive strength */
__IOM uint32_t PAD32FNCSEL : 3; /*!< (@ 0x00000003) Pad 32 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD33PULL : 1; /*!< (@ 0x00000008) Pad 33 pullup enable */
__IOM uint32_t PAD33INPEN : 1; /*!< (@ 0x00000009) Pad 33 input enable */
__IOM uint32_t PAD33STRNG : 1; /*!< (@ 0x0000000A) Pad 33 drive strength */
__IOM uint32_t PAD33FNCSEL : 3; /*!< (@ 0x0000000B) Pad 33 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD34PULL : 1; /*!< (@ 0x00000010) Pad 34 pullup enable */
__IOM uint32_t PAD34INPEN : 1; /*!< (@ 0x00000011) Pad 34 input enable */
__IOM uint32_t PAD34STRNG : 1; /*!< (@ 0x00000012) Pad 34 drive strength */
__IOM uint32_t PAD34FNCSEL : 3; /*!< (@ 0x00000013) Pad 34 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD35PULL : 1; /*!< (@ 0x00000018) Pad 35 pullup enable */
__IOM uint32_t PAD35INPEN : 1; /*!< (@ 0x00000019) Pad 35 input enable */
__IOM uint32_t PAD35STRNG : 1; /*!< (@ 0x0000001A) Pad 35 drive strentgh */
__IOM uint32_t PAD35FNCSEL : 3; /*!< (@ 0x0000001B) Pad 35 function select */
} PADREGI_b;
} ;
union {
__IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J */
struct {
__IOM uint32_t PAD36PULL : 1; /*!< (@ 0x00000000) Pad 36 pullup enable */
__IOM uint32_t PAD36INPEN : 1; /*!< (@ 0x00000001) Pad 36 input enable */
__IOM uint32_t PAD36STRNG : 1; /*!< (@ 0x00000002) Pad 36 drive strength */
__IOM uint32_t PAD36FNCSEL : 3; /*!< (@ 0x00000003) Pad 36 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD37PULL : 1; /*!< (@ 0x00000008) Pad 37 pullup enable */
__IOM uint32_t PAD37INPEN : 1; /*!< (@ 0x00000009) Pad 37 input enable */
__IOM uint32_t PAD37STRNG : 1; /*!< (@ 0x0000000A) Pad 37 drive strength */
__IOM uint32_t PAD37FNCSEL : 3; /*!< (@ 0x0000000B) Pad 37 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD38PULL : 1; /*!< (@ 0x00000010) Pad 38 pullup enable */
__IOM uint32_t PAD38INPEN : 1; /*!< (@ 0x00000011) Pad 38 input enable */
__IOM uint32_t PAD38STRNG : 1; /*!< (@ 0x00000012) Pad 38 drive strength */
__IOM uint32_t PAD38FNCSEL : 3; /*!< (@ 0x00000013) Pad 38 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD39PULL : 1; /*!< (@ 0x00000018) Pad 39 pullup enable */
__IOM uint32_t PAD39INPEN : 1; /*!< (@ 0x00000019) Pad 39 input enable */
__IOM uint32_t PAD39STRNG : 1; /*!< (@ 0x0000001A) Pad 39 drive strentgh */
__IOM uint32_t PAD39FNCSEL : 3; /*!< (@ 0x0000001B) Pad 39 function select */
__IOM uint32_t PAD39RSEL : 2; /*!< (@ 0x0000001E) Pad 39 pullup resistor selection. */
} PADREGJ_b;
} ;
union {
__IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K */
struct {
__IOM uint32_t PAD40PULL : 1; /*!< (@ 0x00000000) Pad 40 pullup enable */
__IOM uint32_t PAD40INPEN : 1; /*!< (@ 0x00000001) Pad 40 input enable */
__IOM uint32_t PAD40STRNG : 1; /*!< (@ 0x00000002) Pad 40 drive strength */
__IOM uint32_t PAD40FNCSEL : 3; /*!< (@ 0x00000003) Pad 40 function select */
__IOM uint32_t PAD40RSEL : 2; /*!< (@ 0x00000006) Pad 40 pullup resistor selection. */
__IOM uint32_t PAD41PULL : 1; /*!< (@ 0x00000008) Pad 41 pullup enable */
__IOM uint32_t PAD41INPEN : 1; /*!< (@ 0x00000009) Pad 41 input enable */
__IOM uint32_t PAD41STRNG : 1; /*!< (@ 0x0000000A) Pad 41 drive strength */
__IOM uint32_t PAD41FNCSEL : 3; /*!< (@ 0x0000000B) Pad 41 function select */
__IM uint32_t : 1;
__IOM uint32_t PAD41PWRUP : 1; /*!< (@ 0x0000000F) Pad 41 upper power switch enable */
__IOM uint32_t PAD42PULL : 1; /*!< (@ 0x00000010) Pad 42 pullup enable */
__IOM uint32_t PAD42INPEN : 1; /*!< (@ 0x00000011) Pad 42 input enable */
__IOM uint32_t PAD42STRNG : 1; /*!< (@ 0x00000012) Pad 42 drive strength */
__IOM uint32_t PAD42FNCSEL : 3; /*!< (@ 0x00000013) Pad 42 function select */
__IOM uint32_t PAD42RSEL : 2; /*!< (@ 0x00000016) Pad 42 pullup resistor selection. */
__IOM uint32_t PAD43PULL : 1; /*!< (@ 0x00000018) Pad 43 pullup enable */
__IOM uint32_t PAD43INPEN : 1; /*!< (@ 0x00000019) Pad 43 input enable */
__IOM uint32_t PAD43STRNG : 1; /*!< (@ 0x0000001A) Pad 43 drive strentgh */
__IOM uint32_t PAD43FNCSEL : 3; /*!< (@ 0x0000001B) Pad 43 function select */
__IOM uint32_t PAD43RSEL : 2; /*!< (@ 0x0000001E) Pad 43 pullup resistor selection. */
} PADREGK_b;
} ;
union {
__IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L */
struct {
__IOM uint32_t PAD44PULL : 1; /*!< (@ 0x00000000) Pad 44 pullup enable */
__IOM uint32_t PAD44INPEN : 1; /*!< (@ 0x00000001) Pad 44 input enable */
__IOM uint32_t PAD44STRNG : 1; /*!< (@ 0x00000002) Pad 44 drive strength */
__IOM uint32_t PAD44FNCSEL : 3; /*!< (@ 0x00000003) Pad 44 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD45PULL : 1; /*!< (@ 0x00000008) Pad 45 pullup enable */
__IOM uint32_t PAD45INPEN : 1; /*!< (@ 0x00000009) Pad 45 input enable */
__IOM uint32_t PAD45STRNG : 1; /*!< (@ 0x0000000A) Pad 45 drive strength */
__IOM uint32_t PAD45FNCSEL : 3; /*!< (@ 0x0000000B) Pad 45 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD46PULL : 1; /*!< (@ 0x00000010) Pad 46 pullup enable */
__IOM uint32_t PAD46INPEN : 1; /*!< (@ 0x00000011) Pad 46 input enable */
__IOM uint32_t PAD46STRNG : 1; /*!< (@ 0x00000012) Pad 46 drive strength */
__IOM uint32_t PAD46FNCSEL : 3; /*!< (@ 0x00000013) Pad 46 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD47PULL : 1; /*!< (@ 0x00000018) Pad 47 pullup enable */
__IOM uint32_t PAD47INPEN : 1; /*!< (@ 0x00000019) Pad 47 input enable */
__IOM uint32_t PAD47STRNG : 1; /*!< (@ 0x0000001A) Pad 47 drive strentgh */
__IOM uint32_t PAD47FNCSEL : 3; /*!< (@ 0x0000001B) Pad 47 function select */
} PADREGL_b;
} ;
union {
__IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M */
struct {
__IOM uint32_t PAD48PULL : 1; /*!< (@ 0x00000000) Pad 48 pullup enable */
__IOM uint32_t PAD48INPEN : 1; /*!< (@ 0x00000001) Pad 48 input enable */
__IOM uint32_t PAD48STRNG : 1; /*!< (@ 0x00000002) Pad 48 drive strength */
__IOM uint32_t PAD48FNCSEL : 3; /*!< (@ 0x00000003) Pad 48 function select */
__IOM uint32_t PAD48RSEL : 2; /*!< (@ 0x00000006) Pad 48 pullup resistor selection. */
__IOM uint32_t PAD49PULL : 1; /*!< (@ 0x00000008) Pad 49 pullup enable */
__IOM uint32_t PAD49INPEN : 1; /*!< (@ 0x00000009) Pad 49 input enable */
__IOM uint32_t PAD49STRNG : 1; /*!< (@ 0x0000000A) Pad 49 drive strength */
__IOM uint32_t PAD49FNCSEL : 3; /*!< (@ 0x0000000B) Pad 49 function select */
__IOM uint32_t PAD49RSEL : 2; /*!< (@ 0x0000000E) Pad 49 pullup resistor selection. */
} PADREGM_b;
} ;
__IM uint32_t RESERVED[3];
union {
__IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO Configuration Register A */
struct {
__IOM uint32_t GPIO0INCFG : 1; /*!< (@ 0x00000000) GPIO0 input enable. */
__IOM uint32_t GPIO0OUTCFG : 2; /*!< (@ 0x00000001) GPIO0 output configuration. */
__IOM uint32_t GPIO0INTD : 1; /*!< (@ 0x00000003) GPIO0 interrupt direction. */
__IOM uint32_t GPIO1INCFG : 1; /*!< (@ 0x00000004) GPIO1 input enable. */
__IOM uint32_t GPIO1OUTCFG : 2; /*!< (@ 0x00000005) GPIO1 output configuration. */
__IOM uint32_t GPIO1INTD : 1; /*!< (@ 0x00000007) GPIO1 interrupt direction. */
__IOM uint32_t GPIO2INCFG : 1; /*!< (@ 0x00000008) GPIO2 input enable. */
__IOM uint32_t GPIO2OUTCFG : 2; /*!< (@ 0x00000009) GPIO2 output configuration. */
__IOM uint32_t GPIO2INTD : 1; /*!< (@ 0x0000000B) GPIO2 interrupt direction. */
__IOM uint32_t GPIO3INCFG : 1; /*!< (@ 0x0000000C) GPIO3 input enable. */
__IOM uint32_t GPIO3OUTCFG : 2; /*!< (@ 0x0000000D) GPIO3 output configuration. */
__IOM uint32_t GPIO3INTD : 1; /*!< (@ 0x0000000F) GPIO3 interrupt direction. */
__IOM uint32_t GPIO4INCFG : 1; /*!< (@ 0x00000010) GPIO4 input enable. */
__IOM uint32_t GPIO4OUTCFG : 2; /*!< (@ 0x00000011) GPIO4 output configuration. */
__IOM uint32_t GPIO4INTD : 1; /*!< (@ 0x00000013) GPIO4 interrupt direction. */
__IOM uint32_t GPIO5INCFG : 1; /*!< (@ 0x00000014) GPIO5 input enable. */
__IOM uint32_t GPIO5OUTCFG : 2; /*!< (@ 0x00000015) GPIO5 output configuration. */
__IOM uint32_t GPIO5INTD : 1; /*!< (@ 0x00000017) GPIO5 interrupt direction. */
__IOM uint32_t GPIO6INCFG : 1; /*!< (@ 0x00000018) GPIO6 input enable. */
__IOM uint32_t GPIO6OUTCFG : 2; /*!< (@ 0x00000019) GPIO6 output configuration. */
__IOM uint32_t GPIO6INTD : 1; /*!< (@ 0x0000001B) GPIO6 interrupt direction. */
__IOM uint32_t GPIO7INCFG : 1; /*!< (@ 0x0000001C) GPIO7 input enable. */
__IOM uint32_t GPIO7OUTCFG : 2; /*!< (@ 0x0000001D) GPIO7 output configuration. */
__IOM uint32_t GPIO7INTD : 1; /*!< (@ 0x0000001F) GPIO7 interrupt direction. */
} CFGA_b;
} ;
union {
__IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO Configuration Register B */
struct {
__IOM uint32_t GPIO8INCFG : 1; /*!< (@ 0x00000000) GPIO8 input enable. */
__IOM uint32_t GPIO8OUTCFG : 2; /*!< (@ 0x00000001) GPIO8 output configuration. */
__IOM uint32_t GPIO8INTD : 1; /*!< (@ 0x00000003) GPIO8 interrupt direction. */
__IOM uint32_t GPIO9INCFG : 1; /*!< (@ 0x00000004) GPIO9 input enable. */
__IOM uint32_t GPIO9OUTCFG : 2; /*!< (@ 0x00000005) GPIO9 output configuration. */
__IOM uint32_t GPIO9INTD : 1; /*!< (@ 0x00000007) GPIO9 interrupt direction. */
__IOM uint32_t GPIO10INCFG : 1; /*!< (@ 0x00000008) GPIO10 input enable. */
__IOM uint32_t GPIO10OUTCFG : 2; /*!< (@ 0x00000009) GPIO10 output configuration. */
__IOM uint32_t GPIO10INTD : 1; /*!< (@ 0x0000000B) GPIO10 interrupt direction. */
__IOM uint32_t GPIO11INCFG : 1; /*!< (@ 0x0000000C) GPIO11 input enable. */
__IOM uint32_t GPIO11OUTCFG : 2; /*!< (@ 0x0000000D) GPIO11 output configuration. */
__IOM uint32_t GPIO11INTD : 1; /*!< (@ 0x0000000F) GPIO11 interrupt direction. */
__IOM uint32_t GPIO12INCFG : 1; /*!< (@ 0x00000010) GPIO12 input enable. */
__IOM uint32_t GPIO12OUTCFG : 2; /*!< (@ 0x00000011) GPIO12 output configuration. */
__IOM uint32_t GPIO12INTD : 1; /*!< (@ 0x00000013) GPIO12 interrupt direction. */
__IOM uint32_t GPIO13INCFG : 1; /*!< (@ 0x00000014) GPIO13 input enable. */
__IOM uint32_t GPIO13OUTCFG : 2; /*!< (@ 0x00000015) GPIO13 output configuration. */
__IOM uint32_t GPIO13INTD : 1; /*!< (@ 0x00000017) GPIO13 interrupt direction. */
__IOM uint32_t GPIO14INCFG : 1; /*!< (@ 0x00000018) GPIO14 input enable. */
__IOM uint32_t GPIO14OUTCFG : 2; /*!< (@ 0x00000019) GPIO14 output configuration. */
__IOM uint32_t GPIO14INTD : 1; /*!< (@ 0x0000001B) GPIO14 interrupt direction. */
__IOM uint32_t GPIO15INCFG : 1; /*!< (@ 0x0000001C) GPIO15 input enable. */
__IOM uint32_t GPIO15OUTCFG : 2; /*!< (@ 0x0000001D) GPIO15 output configuration. */
__IOM uint32_t GPIO15INTD : 1; /*!< (@ 0x0000001F) GPIO15 interrupt direction. */
} CFGB_b;
} ;
union {
__IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO Configuration Register C */
struct {
__IOM uint32_t GPIO16INCFG : 1; /*!< (@ 0x00000000) GPIO16 input enable. */
__IOM uint32_t GPIO16OUTCFG : 2; /*!< (@ 0x00000001) GPIO16 output configuration. */
__IOM uint32_t GPIO16INTD : 1; /*!< (@ 0x00000003) GPIO16 interrupt direction. */
__IOM uint32_t GPIO17INCFG : 1; /*!< (@ 0x00000004) GPIO17 input enable. */
__IOM uint32_t GPIO17OUTCFG : 2; /*!< (@ 0x00000005) GPIO17 output configuration. */
__IOM uint32_t GPIO17INTD : 1; /*!< (@ 0x00000007) GPIO17 interrupt direction. */
__IOM uint32_t GPIO18INCFG : 1; /*!< (@ 0x00000008) GPIO18 input enable. */
__IOM uint32_t GPIO18OUTCFG : 2; /*!< (@ 0x00000009) GPIO18 output configuration. */
__IOM uint32_t GPIO18INTD : 1; /*!< (@ 0x0000000B) GPIO18 interrupt direction. */
__IOM uint32_t GPIO19INCFG : 1; /*!< (@ 0x0000000C) GPIO19 input enable. */
__IOM uint32_t GPIO19OUTCFG : 2; /*!< (@ 0x0000000D) GPIO19 output configuration. */
__IOM uint32_t GPIO19INTD : 1; /*!< (@ 0x0000000F) GPIO19 interrupt direction. */
__IOM uint32_t GPIO20INCFG : 1; /*!< (@ 0x00000010) GPIO20 input enable. */
__IOM uint32_t GPIO20OUTCFG : 2; /*!< (@ 0x00000011) GPIO20 output configuration. */
__IOM uint32_t GPIO20INTD : 1; /*!< (@ 0x00000013) GPIO20 interrupt direction. */
__IOM uint32_t GPIO21INCFG : 1; /*!< (@ 0x00000014) GPIO21 input enable. */
__IOM uint32_t GPIO21OUTCFG : 2; /*!< (@ 0x00000015) GPIO21 output configuration. */
__IOM uint32_t GPIO21INTD : 1; /*!< (@ 0x00000017) GPIO21 interrupt direction. */
__IOM uint32_t GPIO22INCFG : 1; /*!< (@ 0x00000018) GPIO22 input enable. */
__IOM uint32_t GPIO22OUTCFG : 2; /*!< (@ 0x00000019) GPIO22 output configuration. */
__IOM uint32_t GPIO22INTD : 1; /*!< (@ 0x0000001B) GPIO22 interrupt direction. */
__IOM uint32_t GPIO23INCFG : 1; /*!< (@ 0x0000001C) GPIO23 input enable. */
__IOM uint32_t GPIO23OUTCFG : 2; /*!< (@ 0x0000001D) GPIO23 output configuration. */
__IOM uint32_t GPIO23INTD : 1; /*!< (@ 0x0000001F) GPIO23 interrupt direction. */
} CFGC_b;
} ;
union {
__IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO Configuration Register D */
struct {
__IOM uint32_t GPIO24INCFG : 1; /*!< (@ 0x00000000) GPIO24 input enable. */
__IOM uint32_t GPIO24OUTCFG : 2; /*!< (@ 0x00000001) GPIO24 output configuration. */
__IOM uint32_t GPIO24INTD : 1; /*!< (@ 0x00000003) GPIO24 interrupt direction. */
__IOM uint32_t GPIO25INCFG : 1; /*!< (@ 0x00000004) GPIO25 input enable. */
__IOM uint32_t GPIO25OUTCFG : 2; /*!< (@ 0x00000005) GPIO25 output configuration. */
__IOM uint32_t GPIO25INTD : 1; /*!< (@ 0x00000007) GPIO25 interrupt direction. */
__IOM uint32_t GPIO26INCFG : 1; /*!< (@ 0x00000008) GPIO26 input enable. */
__IOM uint32_t GPIO26OUTCFG : 2; /*!< (@ 0x00000009) GPIO26 output configuration. */
__IOM uint32_t GPIO26INTD : 1; /*!< (@ 0x0000000B) GPIO26 interrupt direction. */
__IOM uint32_t GPIO27INCFG : 1; /*!< (@ 0x0000000C) GPIO27 input enable. */
__IOM uint32_t GPIO27OUTCFG : 2; /*!< (@ 0x0000000D) GPIO27 output configuration. */
__IOM uint32_t GPIO27INTD : 1; /*!< (@ 0x0000000F) GPIO27 interrupt direction. */
__IOM uint32_t GPIO28INCFG : 1; /*!< (@ 0x00000010) GPIO28 input enable. */
__IOM uint32_t GPIO28OUTCFG : 2; /*!< (@ 0x00000011) GPIO28 output configuration. */
__IOM uint32_t GPIO28INTD : 1; /*!< (@ 0x00000013) GPIO28 interrupt direction. */
__IOM uint32_t GPIO29INCFG : 1; /*!< (@ 0x00000014) GPIO29 input enable. */
__IOM uint32_t GPIO29OUTCFG : 2; /*!< (@ 0x00000015) GPIO29 output configuration. */
__IOM uint32_t GPIO29INTD : 1; /*!< (@ 0x00000017) GPIO29 interrupt direction. */
__IOM uint32_t GPIO30INCFG : 1; /*!< (@ 0x00000018) GPIO30 input enable. */
__IOM uint32_t GPIO30OUTCFG : 2; /*!< (@ 0x00000019) GPIO30 output configuration. */
__IOM uint32_t GPIO30INTD : 1; /*!< (@ 0x0000001B) GPIO30 interrupt direction. */
__IOM uint32_t GPIO31INCFG : 1; /*!< (@ 0x0000001C) GPIO31 input enable. */
__IOM uint32_t GPIO31OUTCFG : 2; /*!< (@ 0x0000001D) GPIO31 output configuration. */
__IOM uint32_t GPIO31INTD : 1; /*!< (@ 0x0000001F) GPIO31 interrupt direction. */
} CFGD_b;
} ;
union {
__IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO Configuration Register E */
struct {
__IOM uint32_t GPIO32INCFG : 1; /*!< (@ 0x00000000) GPIO32 input enable. */
__IOM uint32_t GPIO32OUTCFG : 2; /*!< (@ 0x00000001) GPIO32 output configuration. */
__IOM uint32_t GPIO32INTD : 1; /*!< (@ 0x00000003) GPIO32 interrupt direction. */
__IOM uint32_t GPIO33INCFG : 1; /*!< (@ 0x00000004) GPIO33 input enable. */
__IOM uint32_t GPIO33OUTCFG : 2; /*!< (@ 0x00000005) GPIO33 output configuration. */
__IOM uint32_t GPIO33INTD : 1; /*!< (@ 0x00000007) GPIO33 interrupt direction. */
__IOM uint32_t GPIO34INCFG : 1; /*!< (@ 0x00000008) GPIO34 input enable. */
__IOM uint32_t GPIO34OUTCFG : 2; /*!< (@ 0x00000009) GPIO34 output configuration. */
__IOM uint32_t GPIO34INTD : 1; /*!< (@ 0x0000000B) GPIO34 interrupt direction. */
__IOM uint32_t GPIO35INCFG : 1; /*!< (@ 0x0000000C) GPIO35 input enable. */
__IOM uint32_t GPIO35OUTCFG : 2; /*!< (@ 0x0000000D) GPIO35 output configuration. */
__IOM uint32_t GPIO35INTD : 1; /*!< (@ 0x0000000F) GPIO35 interrupt direction. */
__IOM uint32_t GPIO36INCFG : 1; /*!< (@ 0x00000010) GPIO36 input enable. */
__IOM uint32_t GPIO36OUTCFG : 2; /*!< (@ 0x00000011) GPIO36 output configuration. */
__IOM uint32_t GPIO36INTD : 1; /*!< (@ 0x00000013) GPIO36 interrupt direction. */
__IOM uint32_t GPIO37INCFG : 1; /*!< (@ 0x00000014) GPIO37 input enable. */
__IOM uint32_t GPIO37OUTCFG : 2; /*!< (@ 0x00000015) GPIO37 output configuration. */
__IOM uint32_t GPIO37INTD : 1; /*!< (@ 0x00000017) GPIO37 interrupt direction. */
__IOM uint32_t GPIO38INCFG : 1; /*!< (@ 0x00000018) GPIO38 input enable. */
__IOM uint32_t GPIO38OUTCFG : 2; /*!< (@ 0x00000019) GPIO38 output configuration. */
__IOM uint32_t GPIO38INTD : 1; /*!< (@ 0x0000001B) GPIO38 interrupt direction. */
__IOM uint32_t GPIO39INCFG : 1; /*!< (@ 0x0000001C) GPIO39 input enable. */
__IOM uint32_t GPIO39OUTCFG : 2; /*!< (@ 0x0000001D) GPIO39 output configuration. */
__IOM uint32_t GPIO39INTD : 1; /*!< (@ 0x0000001F) GPIO39 interrupt direction. */
} CFGE_b;
} ;
union {
__IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO Configuration Register F */
struct {
__IOM uint32_t GPIO40INCFG : 1; /*!< (@ 0x00000000) GPIO40 input enable. */
__IOM uint32_t GPIO40OUTCFG : 2; /*!< (@ 0x00000001) GPIO40 output configuration. */
__IOM uint32_t GPIO40INTD : 1; /*!< (@ 0x00000003) GPIO40 interrupt direction. */
__IOM uint32_t GPIO41INCFG : 1; /*!< (@ 0x00000004) GPIO41 input enable. */
__IOM uint32_t GPIO41OUTCFG : 2; /*!< (@ 0x00000005) GPIO41 output configuration. */
__IOM uint32_t GPIO41INTD : 1; /*!< (@ 0x00000007) GPIO41 interrupt direction. */
__IOM uint32_t GPIO42INCFG : 1; /*!< (@ 0x00000008) GPIO42 input enable. */
__IOM uint32_t GPIO42OUTCFG : 2; /*!< (@ 0x00000009) GPIO42 output configuration. */
__IOM uint32_t GPIO42INTD : 1; /*!< (@ 0x0000000B) GPIO42 interrupt direction. */
__IOM uint32_t GPIO43INCFG : 1; /*!< (@ 0x0000000C) GPIO43 input enable. */
__IOM uint32_t GPIO43OUTCFG : 2; /*!< (@ 0x0000000D) GPIO43 output configuration. */
__IOM uint32_t GPIO43INTD : 1; /*!< (@ 0x0000000F) GPIO43 interrupt direction. */
__IOM uint32_t GPIO44INCFG : 1; /*!< (@ 0x00000010) GPIO44 input enable. */
__IOM uint32_t GPIO44OUTCFG : 2; /*!< (@ 0x00000011) GPIO44 output configuration. */
__IOM uint32_t GPIO44INTD : 1; /*!< (@ 0x00000013) GPIO44 interrupt direction. */
__IOM uint32_t GPIO45INCFG : 1; /*!< (@ 0x00000014) GPIO45 input enable. */
__IOM uint32_t GPIO45OUTCFG : 2; /*!< (@ 0x00000015) GPIO45 output configuration. */
__IOM uint32_t GPIO45INTD : 1; /*!< (@ 0x00000017) GPIO45 interrupt direction. */
__IOM uint32_t GPIO46INCFG : 1; /*!< (@ 0x00000018) GPIO46 input enable. */
__IOM uint32_t GPIO46OUTCFG : 2; /*!< (@ 0x00000019) GPIO46 output configuration. */
__IOM uint32_t GPIO46INTD : 1; /*!< (@ 0x0000001B) GPIO46 interrupt direction. */
__IOM uint32_t GPIO47INCFG : 1; /*!< (@ 0x0000001C) GPIO47 input enable. */
__IOM uint32_t GPIO47OUTCFG : 2; /*!< (@ 0x0000001D) GPIO47 output configuration. */
__IOM uint32_t GPIO47INTD : 1; /*!< (@ 0x0000001F) GPIO47 interrupt direction. */
} CFGF_b;
} ;
union {
__IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO Configuration Register G */
struct {
__IOM uint32_t GPIO48INCFG : 1; /*!< (@ 0x00000000) GPIO48 input enable. */
__IOM uint32_t GPIO48OUTCFG : 2; /*!< (@ 0x00000001) GPIO48 output configuration. */
__IOM uint32_t GPIO48INTD : 1; /*!< (@ 0x00000003) GPIO48 interrupt direction. */
__IOM uint32_t GPIO49INCFG : 1; /*!< (@ 0x00000004) GPIO49 input enable. */
__IOM uint32_t GPIO49OUTCFG : 2; /*!< (@ 0x00000005) GPIO49 output configuration. */
__IOM uint32_t GPIO49INTD : 1; /*!< (@ 0x00000007) GPIO49 interrupt direction. */
} CFGG_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t PADKEY; /*!< (@ 0x00000060) Key Register for all pad configuration registers */
struct {
__IOM uint32_t PADKEY : 32; /*!< (@ 0x00000000) Key register value. */
} PADKEY_b;
} ;
__IM uint32_t RESERVED2[7];
union {
__IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */
struct {
__IOM uint32_t RDA : 32; /*!< (@ 0x00000000) GPIO31-0 read data. */
} RDA_b;
} ;
union {
__IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */
struct {
__IOM uint32_t RDB : 18; /*!< (@ 0x00000000) GPIO49-32 read data. */
} RDB_b;
} ;
union {
__IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A */
struct {
__IOM uint32_t WTA : 32; /*!< (@ 0x00000000) GPIO31-0 write data. */
} WTA_b;
} ;
union {
__IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B */
struct {
__IOM uint32_t WTB : 18; /*!< (@ 0x00000000) GPIO49-32 write data. */
} WTB_b;
} ;
union {
__IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set */
struct {
__IOM uint32_t WTSA : 32; /*!< (@ 0x00000000) Set the GPIO31-0 write data. */
} WTSA_b;
} ;
union {
__IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set */
struct {
__IOM uint32_t WTSB : 18; /*!< (@ 0x00000000) Set the GPIO49-32 write data. */
} WTSB_b;
} ;
union {
__IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear */
struct {
__IOM uint32_t WTCA : 32; /*!< (@ 0x00000000) Clear the GPIO31-0 write data. */
} WTCA_b;
} ;
union {
__IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear */
struct {
__IOM uint32_t WTCB : 18; /*!< (@ 0x00000000) Clear the GPIO49-32 write data. */
} WTCB_b;
} ;
union {
__IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A */
struct {
__IOM uint32_t ENA : 32; /*!< (@ 0x00000000) GPIO31-0 output enables */
} ENA_b;
} ;
union {
__IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B */
struct {
__IOM uint32_t ENB : 18; /*!< (@ 0x00000000) GPIO49-32 output enables */
} ENB_b;
} ;
union {
__IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set */
struct {
__IOM uint32_t ENSA : 32; /*!< (@ 0x00000000) Set the GPIO31-0 output enables */
} ENSA_b;
} ;
union {
__IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set */
struct {
__IOM uint32_t ENSB : 18; /*!< (@ 0x00000000) Set the GPIO49-32 output enables */
} ENSB_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear */
struct {
__IOM uint32_t ENCA : 32; /*!< (@ 0x00000000) Clear the GPIO31-0 output enables */
} ENCA_b;
} ;
union {
__IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear */
struct {
__IOM uint32_t ENCB : 18; /*!< (@ 0x00000000) Clear the GPIO49-32 output enables */
} ENCB_b;
} ;
union {
__IOM uint32_t STMRCAP; /*!< (@ 0x000000BC) STIMER Capture Control */
struct {
__IOM uint32_t STSEL0 : 6; /*!< (@ 0x00000000) STIMER Capture 0 Select. */
__IOM uint32_t STPOL0 : 1; /*!< (@ 0x00000006) STIMER Capture 0 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL1 : 6; /*!< (@ 0x00000008) STIMER Capture 1 Select. */
__IOM uint32_t STPOL1 : 1; /*!< (@ 0x0000000E) STIMER Capture 1 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL2 : 6; /*!< (@ 0x00000010) STIMER Capture 2 Select. */
__IOM uint32_t STPOL2 : 1; /*!< (@ 0x00000016) STIMER Capture 2 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL3 : 6; /*!< (@ 0x00000018) STIMER Capture 3 Select. */
__IOM uint32_t STPOL3 : 1; /*!< (@ 0x0000001E) STIMER Capture 3 Polarity. */
} STMRCAP_b;
} ;
union {
__IOM uint32_t IOM0IRQ; /*!< (@ 0x000000C0) IOM0 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM0IRQ : 6; /*!< (@ 0x00000000) IOMSTR0 IRQ pad select. */
} IOM0IRQ_b;
} ;
union {
__IOM uint32_t IOM1IRQ; /*!< (@ 0x000000C4) IOM1 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM1IRQ : 6; /*!< (@ 0x00000000) IOMSTR1 IRQ pad select. */
} IOM1IRQ_b;
} ;
union {
__IOM uint32_t IOM2IRQ; /*!< (@ 0x000000C8) IOM2 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM2IRQ : 6; /*!< (@ 0x00000000) IOMSTR2 IRQ pad select. */
} IOM2IRQ_b;
} ;
union {
__IOM uint32_t IOM3IRQ; /*!< (@ 0x000000CC) IOM3 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM3IRQ : 6; /*!< (@ 0x00000000) IOMSTR3 IRQ pad select. */
} IOM3IRQ_b;
} ;
union {
__IOM uint32_t IOM4IRQ; /*!< (@ 0x000000D0) IOM4 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM4IRQ : 6; /*!< (@ 0x00000000) IOMSTR4 IRQ pad select. */
} IOM4IRQ_b;
} ;
union {
__IOM uint32_t IOM5IRQ; /*!< (@ 0x000000D4) IOM5 Flow Control IRQ Select */
struct {
__IOM uint32_t IOM5IRQ : 6; /*!< (@ 0x00000000) IOMSTR5 IRQ pad select. */
} IOM5IRQ_b;
} ;
union {
__IOM uint32_t LOOPBACK; /*!< (@ 0x000000D8) IOM to IOS Loopback Control */
struct {
__IOM uint32_t LOOPBACK : 3; /*!< (@ 0x00000000) IOM to IOS loopback control. */
} LOOPBACK_b;
} ;
union {
__IOM uint32_t GPIOOBS; /*!< (@ 0x000000DC) GPIO Observation Mode Sample register */
struct {
__IOM uint32_t OBS_DATA : 16; /*!< (@ 0x00000000) Sample of the data output on the GPIO observation
port. May have async sampling issues, as
the data is not synronized to the read
operation. Intended for debug purposes
only */
} GPIOOBS_b;
} ;
union {
__IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000E0) Alternate Pad Configuration reg0 (Pads 3,2,1,0) */
struct {
__IOM uint32_t PAD0_DS1 : 1; /*!< (@ 0x00000000) Pad 0 high order drive strength selection. Used
in conjunction with PAD0STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD0_SR : 1; /*!< (@ 0x00000004) Pad 0 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD1_DS1 : 1; /*!< (@ 0x00000008) Pad 1 high order drive strength selection. Used
in conjunction with PAD1STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD1_SR : 1; /*!< (@ 0x0000000C) Pad 1 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD2_DS1 : 1; /*!< (@ 0x00000010) Pad 2 high order drive strength selection. Used
in conjunction with PAD2STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD2_SR : 1; /*!< (@ 0x00000014) Pad 2 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD3_DS1 : 1; /*!< (@ 0x00000018) Pad 3 high order drive strength selection. Used
in conjunction with PAD3STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD3_SR : 1; /*!< (@ 0x0000001C) Pad 3 slew rate selection. */
} ALTPADCFGA_b;
} ;
union {
__IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000E4) Alternate Pad Configuration reg1 (Pads 7,6,5,4) */
struct {
__IOM uint32_t PAD4_DS1 : 1; /*!< (@ 0x00000000) Pad 4 high order drive strength selection. Used
in conjunction with PAD4STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD4_SR : 1; /*!< (@ 0x00000004) Pad 4 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD5_DS1 : 1; /*!< (@ 0x00000008) Pad 5 high order drive strength selection. Used
in conjunction with PAD5STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD5_SR : 1; /*!< (@ 0x0000000C) Pad 5 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD6_DS1 : 1; /*!< (@ 0x00000010) Pad 6 high order drive strength selection. Used
in conjunction with PAD6STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD6_SR : 1; /*!< (@ 0x00000014) Pad 6 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD7_DS1 : 1; /*!< (@ 0x00000018) Pad 7 high order drive strength selection. Used
in conjunction with PAD7STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD7_SR : 1; /*!< (@ 0x0000001C) Pad 7 slew rate selection. */
} ALTPADCFGB_b;
} ;
union {
__IOM uint32_t ALTPADCFGC; /*!< (@ 0x000000E8) Alternate Pad Configuration reg2 (Pads 11,10,9,8) */
struct {
__IOM uint32_t PAD8_DS1 : 1; /*!< (@ 0x00000000) Pad 8 high order drive strength selection. Used
in conjunction with PAD8STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD8_SR : 1; /*!< (@ 0x00000004) Pad 8 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD9_DS1 : 1; /*!< (@ 0x00000008) Pad 9 high order drive strength selection. Used
in conjunction with PAD9STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD9_SR : 1; /*!< (@ 0x0000000C) Pad 9 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD10_DS1 : 1; /*!< (@ 0x00000010) Pad 10 high order drive strength selection. Used
in conjunction with PAD10STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD10_SR : 1; /*!< (@ 0x00000014) Pad 10 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD11_DS1 : 1; /*!< (@ 0x00000018) Pad 11 high order drive strength selection. Used
in conjunction with PAD11STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD11_SR : 1; /*!< (@ 0x0000001C) Pad 11 slew rate selection. */
} ALTPADCFGC_b;
} ;
union {
__IOM uint32_t ALTPADCFGD; /*!< (@ 0x000000EC) Alternate Pad Configuration reg3 (Pads 15,14,13,12) */
struct {
__IOM uint32_t PAD12_DS1 : 1; /*!< (@ 0x00000000) Pad 12 high order drive strength selection. Used
in conjunction with PAD12STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD12_SR : 1; /*!< (@ 0x00000004) Pad 12 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD13_DS1 : 1; /*!< (@ 0x00000008) Pad 13 high order drive strength selection. Used
in conjunction with PAD13STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD13_SR : 1; /*!< (@ 0x0000000C) Pad 13 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD14_DS1 : 1; /*!< (@ 0x00000010) Pad 14 high order drive strength selection. Used
in conjunction with PAD14STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD14_SR : 1; /*!< (@ 0x00000014) Pad 14 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD15_DS1 : 1; /*!< (@ 0x00000018) Pad 15 high order drive strength selection. Used
in conjunction with PAD15STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD15_SR : 1; /*!< (@ 0x0000001C) Pad 15 slew rate selection. */
} ALTPADCFGD_b;
} ;
union {
__IOM uint32_t ALTPADCFGE; /*!< (@ 0x000000F0) Alternate Pad Configuration reg4 (Pads 19,18,17,16) */
struct {
__IOM uint32_t PAD16_DS1 : 1; /*!< (@ 0x00000000) Pad 16 high order drive strength selection. Used
in conjunction with PAD16STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD16_SR : 1; /*!< (@ 0x00000004) Pad 16 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD17_DS1 : 1; /*!< (@ 0x00000008) Pad 17 high order drive strength selection. Used
in conjunction with PAD17STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD17_SR : 1; /*!< (@ 0x0000000C) Pad 17 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD18_DS1 : 1; /*!< (@ 0x00000010) Pad 18 high order drive strength selection. Used
in conjunction with PAD18STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD18_SR : 1; /*!< (@ 0x00000014) Pad 18 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD19_DS1 : 1; /*!< (@ 0x00000018) Pad 19 high order drive strength selection. Used
in conjunction with PAD19STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD19_SR : 1; /*!< (@ 0x0000001C) Pad 19 slew rate selection. */
} ALTPADCFGE_b;
} ;
union {
__IOM uint32_t ALTPADCFGF; /*!< (@ 0x000000F4) Alternate Pad Configuration reg5 (Pads 23,22,21,20) */
struct {
__IOM uint32_t PAD20_DS1 : 1; /*!< (@ 0x00000000) Pad 20 high order drive strength selection. Used
in conjunction with PAD20STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD20_SR : 1; /*!< (@ 0x00000004) Pad 20 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD21_DS1 : 1; /*!< (@ 0x00000008) Pad 21 high order drive strength selection. Used
in conjunction with PAD21STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD21_SR : 1; /*!< (@ 0x0000000C) Pad 21 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD22_DS1 : 1; /*!< (@ 0x00000010) Pad 22 high order drive strength selection. Used
in conjunction with PAD22STRNG field to
set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD22_SR : 1; /*!< (@ 0x00000014) Pad 22 slew rate selection. */
__IM uint32_t : 3;