| # |
| # Licensed to the Apache Software Foundation (ASF) under one |
| # or more contributor license agreements. See the NOTICE file |
| # distributed with this work for additional information |
| # regarding copyright ownership. The ASF licenses this file |
| # to you under the Apache License, Version 2.0 (the |
| # "License"); you may not use this file except in compliance |
| # with the License. You may obtain a copy of the License at |
| # |
| # http://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, |
| # software distributed under the License is distributed on an |
| # "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY |
| # KIND, either express or implied. See the License for the |
| # specific language governing permissions and limitations |
| # under the License. |
| # |
| |
| syscfg.defs: |
| HARDFLOAT: |
| description: 'Whether to enable UART0 FPU context switch' |
| value: 1 |
| |
| CLOCK_FREQ: |
| description: 'System clock frequency, defined in hal_bsp.c' |
| value: 200000000 |
| range: 8000000, 24000000, 50000000, 100000000, 200000000 |
| |
| syscfg.vals: |
| TIMER_0: 1 |
| |
| # UART_1 available on UEXT header |
| UART_1: 1 |
| UART_1_PIN_TX: MCU_GPIO_PORTE(8) |
| UART_1_PIN_RX: MCU_GPIO_PORTE(9) |
| |
| # I2C_1 available on UEXT header |
| I2C_1: 1 |
| I2C_1_FREQ_KHZ: 400 |
| |
| # SPI_0 available on UEXT header |
| SPI_0_MASTER: 1 |
| SPI_0_MASTER_PIN_MOSI: MCU_GPIO_PORTD(15) |
| SPI_0_MASTER_PIN_MISO: MCU_GPIO_PORTD(14) |
| |
| CONSOLE_UART_DEV: '"uart1"' |
| |
| CLOCK_FREQ: 200000000 |
| SYSTEM_CLOCK_SRC: POSC_PLL |
| SYSTEM_CLOCK_PLLIDIV: 3 |
| SYSTEM_CLOCK_PLLRANGE: 1 |
| SYSTEM_CLOCK_PLLMULT: 50 |
| SYSTEM_CLOCK_PLLODIV: 2 |
