hw/bsp/nucleo-l073rz: Update to use common startup
Local linker scripts removed.
BSP uses autogenerated linker script and cortex-m0
startup.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
diff --git a/hw/bsp/nucleo-l073rz/boot-nucleo-l073rz.ld b/hw/bsp/nucleo-l073rz/boot-nucleo-l073rz.ld
deleted file mode 100644
index b18ead5..0000000
--- a/hw/bsp/nucleo-l073rz/boot-nucleo-l073rz.ld
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 20K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
-}
-
-/* The bootloader does not contain an image header */
-_imghdr_size = 0x0;
diff --git a/hw/bsp/nucleo-l073rz/bsp.yml b/hw/bsp/nucleo-l073rz/bsp.yml
index 1c0852c..a116a95 100644
--- a/hw/bsp/nucleo-l073rz/bsp.yml
+++ b/hw/bsp/nucleo-l073rz/bsp.yml
@@ -22,12 +22,7 @@
bsp.maker: "STMicroelectronics"
bsp.arch: cortex_m0
bsp.compiler: "@apache-mynewt-core/compiler/arm-none-eabi-m0"
-bsp.linkerscript:
- - "hw/bsp/nucleo-l073rz/nucleo-l073rz.ld"
- - "@apache-mynewt-core/hw/mcu/stm/stm32l0xx/stm32l073.ld"
-bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- - "hw/bsp/nucleo-l073rz/boot-nucleo-l073rz.ld"
- - "@apache-mynewt-core/hw/mcu/stm/stm32l0xx/stm32l073.ld"
+bsp.linkerscript: autogenerated
bsp.downloadscript: "hw/scripts/download.sh"
bsp.debugscript: "hw/bsp/nucleo-l073rz/nucleo-l073rz_debug.sh"
diff --git a/hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h b/hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h
index 08c936f..00140ca 100644
--- a/hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h
+++ b/hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h
@@ -158,8 +158,8 @@
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
-#define INSTRUCTION_CACHE_ENABLE MYNEWT_VAL(STM32_INSTRUCTION_CACHE_ENABLE)
-#define DATA_CACHE_ENABLE MYNEWT_VAL(STM32_DATA_CACHE_ENABLE)
+#define PREREAD_ENABLE MYNEWT_VAL(STM32_FLASH_PREREAD_ENABLE)
+#define BUFFER_CACHE_DISABLE (MYNEWT_VAL(STM32_FLASH_CACHE_ENABLE) == 0)
/* ########################## Assert Selection ############################## */
/**
diff --git a/hw/bsp/nucleo-l073rz/nucleo-l073rz.ld b/hw/bsp/nucleo-l073rz/nucleo-l073rz.ld
deleted file mode 100644
index 0db6fd1..0000000
--- a/hw/bsp/nucleo-l073rz/nucleo-l073rz.ld
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 72K /* First image slot. */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
-}
-
-/* This linker script is used for images and thus contains an image header */
-_imghdr_size = 0x20;
diff --git a/hw/bsp/nucleo-l073rz/src/arch/cortex_m0/startup_stm32l073xx.s b/hw/bsp/nucleo-l073rz/src/arch/cortex_m0/startup_stm32l073xx.s
deleted file mode 100644
index cbd3ac2..0000000
--- a/hw/bsp/nucleo-l073rz/src/arch/cortex_m0/startup_stm32l073xx.s
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32l073xx.s
- * @author MCD Application Team
- * @brief STM32L073xx Devices vector table for GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0plus
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/*
- * mynewt specific corebss clearing.
- */
- ldr r2, =__corebss_start__
- b LoopFillZeroCoreBss
-
-/* Zero fill the bss segment. */
-FillZeroCoreBss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZeroCoreBss:
- ldr r3, =__corebss_end__
- cmp r2, r3
- bcc FillZeroCoreBss
-
- ldr r0, =__HeapBase
- ldr r1, =__HeapLimit
- bl _sbrkInit
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call the libc entry point.*/
- bl _start
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .globl __isr_vector
-__isr_vector:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word RTC_IRQHandler /* RTC through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_CRS_IRQHandler /* RCC and CRS */
- .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
- .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
- .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
- .word TSC_IRQHandler /* TSC */
- .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
- .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
- .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
- .word LPTIM1_IRQHandler /* LPTIM1 */
- .word USART4_5_IRQHandler /* USART4 and USART 5 */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
- .word TIM7_IRQHandler /* TIM7 */
- .word 0 /* Reserved */
- .word TIM21_IRQHandler /* TIM21 */
- .word I2C3_IRQHandler /* I2C3 */
- .word TIM22_IRQHandler /* TIM22 */
- .word I2C1_IRQHandler /* I2C1 */
- .word I2C2_IRQHandler /* I2C2 */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */
- .word LCD_IRQHandler /* LCD */
- .word USB_IRQHandler /* USB */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_CRS_IRQHandler
- .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak USART4_5_IRQHandler
- .thumb_set USART4_5_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak TIM21_IRQHandler
- .thumb_set TIM21_IRQHandler,Default_Handler
-
- .weak I2C3_IRQHandler
- .thumb_set I2C3_IRQHandler,Default_Handler
-
- .weak TIM22_IRQHandler
- .thumb_set TIM22_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak RNG_LPUART1_IRQHandler
- .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
- .weak LCD_IRQHandler
- .thumb_set LCD_IRQHandler,Default_Handler
-
- .weak USB_IRQHandler
- .thumb_set USB_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-l073rz/syscfg.yml b/hw/bsp/nucleo-l073rz/syscfg.yml
index 07dc322..992c81a 100644
--- a/hw/bsp/nucleo-l073rz/syscfg.yml
+++ b/hw/bsp/nucleo-l073rz/syscfg.yml
@@ -31,6 +31,8 @@
value: '"spi0"'
syscfg.vals:
+ MCU_RAM_START: 0x20000000
+ MCU_RAM_SIZE: 20K
REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
