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| </pre><pre class="rust"><code><span class="kw">use </span>core::fmt; |
| <span class="kw">use </span>core::ops::{Deref, DerefMut}; |
| |
| <span class="doccomment">/// Pads and aligns a value to the length of a cache line. |
| /// |
| /// In concurrent programming, sometimes it is desirable to make sure commonly accessed pieces of |
| /// data are not placed into the same cache line. Updating an atomic value invalidates the whole |
| /// cache line it belongs to, which makes the next access to the same cache line slower for other |
| /// CPU cores. Use `CachePadded` to ensure updating one piece of data doesn't invalidate other |
| /// cached data. |
| /// |
| /// # Size and alignment |
| /// |
| /// Cache lines are assumed to be N bytes long, depending on the architecture: |
| /// |
| /// * On x86-64, aarch64, and powerpc64, N = 128. |
| /// * On arm, mips, mips64, and riscv64, N = 32. |
| /// * On s390x, N = 256. |
| /// * On all others, N = 64. |
| /// |
| /// Note that N is just a reasonable guess and is not guaranteed to match the actual cache line |
| /// length of the machine the program is running on. On modern Intel architectures, spatial |
| /// prefetcher is pulling pairs of 64-byte cache lines at a time, so we pessimistically assume that |
| /// cache lines are 128 bytes long. |
| /// |
| /// The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate |
| /// a value of type `T`. |
| /// |
| /// The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`. |
| /// |
| /// # Examples |
| /// |
| /// Alignment and padding: |
| /// |
| /// ``` |
| /// use crossbeam_utils::CachePadded; |
| /// |
| /// let array = [CachePadded::new(1i8), CachePadded::new(2i8)]; |
| /// let addr1 = &*array[0] as *const i8 as usize; |
| /// let addr2 = &*array[1] as *const i8 as usize; |
| /// |
| /// assert!(addr2 - addr1 >= 32); |
| /// assert_eq!(addr1 % 32, 0); |
| /// assert_eq!(addr2 % 32, 0); |
| /// ``` |
| /// |
| /// When building a concurrent queue with a head and a tail index, it is wise to place them in |
| /// different cache lines so that concurrent threads pushing and popping elements don't invalidate |
| /// each other's cache lines: |
| /// |
| /// ``` |
| /// use crossbeam_utils::CachePadded; |
| /// use std::sync::atomic::AtomicUsize; |
| /// |
| /// struct Queue<T> { |
| /// head: CachePadded<AtomicUsize>, |
| /// tail: CachePadded<AtomicUsize>, |
| /// buffer: *mut T, |
| /// } |
| /// ``` |
| </span><span class="attribute">#[derive(Clone, Copy, Default, Hash, PartialEq, Eq)] |
| </span><span class="comment">// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache |
| // lines at a time, so we have to align to 128 bytes rather than 64. |
| // |
| // Sources: |
| // - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
| // - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107 |
| // |
| // ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size. |
| // |
| // Sources: |
| // - https://www.mono-project.com/news/2016/09/12/arm64-icache/ |
| // |
| // powerpc64 has 128-byte cache line size. |
| // |
| // Sources: |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9 |
| </span><span class="attribute">#[cfg_attr( |
| any( |
| target_arch = <span class="string">"x86_64"</span>, |
| target_arch = <span class="string">"aarch64"</span>, |
| target_arch = <span class="string">"powerpc64"</span>, |
| ), |
| repr(align(<span class="number">128</span>)) |
| )] |
| </span><span class="comment">// arm, mips, mips64, and riscv64 have 32-byte cache line size. |
| // |
| // Sources: |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7 |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7 |
| </span><span class="attribute">#[cfg_attr( |
| any( |
| target_arch = <span class="string">"arm"</span>, |
| target_arch = <span class="string">"mips"</span>, |
| target_arch = <span class="string">"mips64"</span>, |
| target_arch = <span class="string">"riscv64"</span>, |
| ), |
| repr(align(<span class="number">32</span>)) |
| )] |
| </span><span class="comment">// s390x has 256-byte cache line size. |
| // |
| // Sources: |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7 |
| </span><span class="attribute">#[cfg_attr(target_arch = <span class="string">"s390x"</span>, repr(align(<span class="number">256</span>)))] |
| </span><span class="comment">// x86 and wasm have 64-byte cache line size. |
| // |
| // Sources: |
| // - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 |
| // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 |
| // |
| // All others are assumed to have 64-byte cache line size. |
| </span><span class="attribute">#[cfg_attr( |
| not(any( |
| target_arch = <span class="string">"x86_64"</span>, |
| target_arch = <span class="string">"aarch64"</span>, |
| target_arch = <span class="string">"powerpc64"</span>, |
| target_arch = <span class="string">"arm"</span>, |
| target_arch = <span class="string">"mips"</span>, |
| target_arch = <span class="string">"mips64"</span>, |
| target_arch = <span class="string">"riscv64"</span>, |
| target_arch = <span class="string">"s390x"</span>, |
| )), |
| repr(align(<span class="number">64</span>)) |
| )] |
| </span><span class="kw">pub struct </span>CachePadded<T> { |
| value: T, |
| } |
| |
| <span class="kw">unsafe impl</span><T: Send> Send <span class="kw">for </span>CachePadded<T> {} |
| <span class="kw">unsafe impl</span><T: Sync> Sync <span class="kw">for </span>CachePadded<T> {} |
| |
| <span class="kw">impl</span><T> CachePadded<T> { |
| <span class="doccomment">/// Pads and aligns a value to the length of a cache line. |
| /// |
| /// # Examples |
| /// |
| /// ``` |
| /// use crossbeam_utils::CachePadded; |
| /// |
| /// let padded_value = CachePadded::new(1); |
| /// ``` |
| </span><span class="kw">pub const fn </span>new(t: T) -> CachePadded<T> { |
| CachePadded::<T> { value: t } |
| } |
| |
| <span class="doccomment">/// Returns the inner value. |
| /// |
| /// # Examples |
| /// |
| /// ``` |
| /// use crossbeam_utils::CachePadded; |
| /// |
| /// let padded_value = CachePadded::new(7); |
| /// let value = padded_value.into_inner(); |
| /// assert_eq!(value, 7); |
| /// ``` |
| </span><span class="kw">pub fn </span>into_inner(<span class="self">self</span>) -> T { |
| <span class="self">self</span>.value |
| } |
| } |
| |
| <span class="kw">impl</span><T> Deref <span class="kw">for </span>CachePadded<T> { |
| <span class="kw">type </span>Target = T; |
| |
| <span class="kw">fn </span>deref(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>T { |
| <span class="kw-2">&</span><span class="self">self</span>.value |
| } |
| } |
| |
| <span class="kw">impl</span><T> DerefMut <span class="kw">for </span>CachePadded<T> { |
| <span class="kw">fn </span>deref_mut(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="kw-2">&mut </span>T { |
| <span class="kw-2">&mut </span><span class="self">self</span>.value |
| } |
| } |
| |
| <span class="kw">impl</span><T: fmt::Debug> fmt::Debug <span class="kw">for </span>CachePadded<T> { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| f.debug_struct(<span class="string">"CachePadded"</span>) |
| .field(<span class="string">"value"</span>, <span class="kw-2">&</span><span class="self">self</span>.value) |
| .finish() |
| } |
| } |
| |
| <span class="kw">impl</span><T> From<T> <span class="kw">for </span>CachePadded<T> { |
| <span class="kw">fn </span>from(t: T) -> <span class="self">Self </span>{ |
| CachePadded::new(t) |
| } |
| } |
| </code></pre></div> |
| </section></div></main><div id="rustdoc-vars" data-root-path="../../" data-current-crate="crossbeam_utils" data-themes="ayu,dark,light" data-resource-suffix="" data-rustdoc-version="1.66.0-nightly (5c8bff74b 2022-10-21)" ></div></body></html> |
