| <!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Source of the Rust file `/root/sunhe/incubator-teaclave/third_party/rust-sgx-sdk/sgx_types/src/cpu_features.rs`."><meta name="keywords" content="rust, rustlang, rust-lang"><title>cpu_features.rs - source</title><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceSerif4-Regular.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../FiraSans-Regular.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../FiraSans-Medium.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceCodePro-Regular.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceSerif4-Bold.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceCodePro-Semibold.ttf.woff2"><link rel="stylesheet" href="../../normalize.css"><link rel="stylesheet" href="../../rustdoc.css" id="mainThemeStyle"><link rel="stylesheet" href="../../ayu.css" disabled><link rel="stylesheet" href="../../dark.css" disabled><link rel="stylesheet" href="../../light.css" id="themeStyle"><script id="default-settings" ></script><script src="../../storage.js"></script><script defer src="../../source-script.js"></script><script defer src="../../source-files.js"></script><script defer src="../../main.js"></script><noscript><link rel="stylesheet" href="../../noscript.css"></noscript><link rel="alternate icon" type="image/png" href="../../favicon-16x16.png"><link rel="alternate icon" type="image/png" href="../../favicon-32x32.png"><link rel="icon" type="image/svg+xml" href="../../favicon.svg"></head><body class="rustdoc source"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="sidebar"><a class="sidebar-logo" href="../../sgx_types/index.html"><div class="logo-container"><img class="rust-logo" src="../../rust-logo.svg" alt="logo"></div></a></nav><main><div class="width-limiter"><nav class="sub"><a class="sub-logo-container" href="../../sgx_types/index.html"><img class="rust-logo" src="../../rust-logo.svg" alt="logo"></a><form class="search-form"><div class="search-container"><span></span><input class="search-input" name="search" autocomplete="off" spellcheck="false" placeholder="Click or press ‘S’ to search, ‘?’ for more options…" type="search"><div id="help-button" title="help" tabindex="-1"><a href="../../help.html">?</a></div><div id="settings-menu" tabindex="-1"><a href="../../settings.html" title="settings"><img width="22" height="22" alt="Change settings" src="../../wheel.svg"></a></div></div></form></nav><section id="main-content" class="content"><div class="example-wrap"><pre class="src-line-numbers"><span id="1">1</span> |
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| </pre><pre class="rust"><code><span class="comment">// Licensed to the Apache Software Foundation (ASF) under one |
| // or more contributor license agreements. See the NOTICE file |
| // distributed with this work for additional information |
| // regarding copyright ownership. The ASF licenses this file |
| // to you under the Apache License, Version 2.0 (the |
| // "License"); you may not use this file except in compliance |
| // with the License. You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, |
| // software distributed under the License is distributed on an |
| // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY |
| // KIND, either express or implied. See the License for the |
| // specific language governing permissions and limitations |
| // under the License.. |
| |
| // |
| // The processor is a generic IA32 CPU |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_GENERIC_IA32: u64 = <span class="number">0x00000001</span>; |
| |
| <span class="comment">// |
| // Floating point unit is on-chip. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_FPU: u64 = <span class="number">0x00000002</span>; |
| |
| <span class="comment">// |
| // Conditional mov instructions are supported. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_CMOV: u64 = <span class="number">0x00000004</span>; |
| |
| <span class="comment">// |
| // The processor supports the MMX technology instruction set extensions |
| // to Intel Architecture. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_MMX: u64 = <span class="number">0x00000008</span>; |
| |
| <span class="comment">// |
| // The FXSAVE and FXRSTOR instructions are supported for fast |
| // save and restore of the floating point context. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_FXSAVE: u64 = <span class="number">0x00000010</span>; |
| |
| <span class="comment">// |
| // Indicates the processor supports the Streaming SIMD Extensions Instructions. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSE: u64 = <span class="number">0x00000020</span>; |
| |
| <span class="comment">// |
| // Indicates the processor supports the Streaming SIMD |
| // Extensions 2 Instructions. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSE2: u64 = <span class="number">0x00000040</span>; |
| |
| <span class="comment">// |
| // Indicates the processor supports the Streaming SIMD |
| // Extensions 3 Instructions. (PNI) |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSE3: u64 = <span class="number">0x00000080</span>; |
| |
| <span class="comment">// |
| // The processor supports the Supplemental Streaming SIMD Extensions 3 |
| // instructions. (MNI) |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSSE3: u64 = <span class="number">0x00000100</span>; |
| |
| <span class="comment">// |
| // The processor supports the Streaming SIMD Extensions 4.1 instructions.(SNI) |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSE4_1: u64 = <span class="number">0x00000200</span>; |
| |
| <span class="comment">// |
| // The processor supports the Streaming SIMD Extensions 4.1 instructions. |
| // (NNI + STTNI) |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_SSE4_2: u64 = <span class="number">0x00000400</span>; |
| |
| <span class="comment">// |
| // The processor supports MOVBE instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_MOVBE: u64 = <span class="number">0x00000800</span>; |
| |
| <span class="comment">// |
| // The processor supports POPCNT instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_POPCNT: u64 = <span class="number">0x00001000</span>; |
| |
| <span class="comment">// |
| // The processor supports PCLMULQDQ instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_PCLMULQDQ: u64 = <span class="number">0x00002000</span>; |
| |
| <span class="comment">// |
| // The processor supports instruction extension for encryption. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_AES: u64 = <span class="number">0x00004000</span>; |
| |
| <span class="comment">// |
| // The processor supports 16-bit floating-point conversions instructions. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_F16C: u64 = <span class="number">0x00008000</span>; |
| |
| <span class="comment">// |
| // The processor supports AVX instruction extension. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX: u64 = <span class="number">0x00010000</span>; |
| |
| <span class="comment">// |
| // The processor supports RDRND (read random value) instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_RDRND: u64 = <span class="number">0x00020000</span>; |
| |
| <span class="comment">// |
| // The processor supports FMA instructions. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_FMA: u64 = <span class="number">0x00040000</span>; |
| |
| <span class="comment">// |
| // The processor supports two groups of advanced bit manipulation extensions. - Haswell introduced, AVX2 related |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_BMI: u64 = <span class="number">0x00080000</span>; |
| |
| <span class="comment">// |
| // The processor supports LZCNT instruction (counts the number of leading zero |
| // bits). - Haswell introduced |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_LZCNT: u64 = <span class="number">0x00100000</span>; |
| |
| <span class="comment">// |
| // The processor supports HLE extension (hardware lock elision). - Haswell introduced |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_HLE: u64 = <span class="number">0x00200000</span>; |
| |
| <span class="comment">// |
| // The processor supports RTM extension (restricted transactional memory) - Haswell AVX2 related. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_RTM: u64 = <span class="number">0x00400000</span>; |
| |
| <span class="comment">// |
| // The processor supports AVX2 instruction extension. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX2: u64 = <span class="number">0x00800000</span>; |
| |
| <span class="comment">// |
| // The processor supports AVX512 dword/qword instruction extension. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512DQ: u64 = <span class="number">0x01000000</span>; |
| |
| <span class="comment">// |
| // The processor supports the PTWRITE instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_PTWRITE: u64 = <span class="number">0x02000000</span>; |
| |
| <span class="comment">// |
| // KNC instruction set |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_KNCNI: u64 = <span class="number">0x04000000</span>; |
| |
| <span class="comment">// |
| // AVX512 foundation instructions |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512F: u64 = <span class="number">0x08000000</span>; |
| |
| <span class="comment">// |
| // The processor supports uint add with OF or CF flags (ADOX, ADCX) |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_ADX: u64 = <span class="number">0x10000000</span>; |
| |
| <span class="comment">// |
| // The processor supports RDSEED instruction. |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_RDSEED: u64 = <span class="number">0x20000000</span>; |
| |
| <span class="comment">// AVX512IFMA52: vpmadd52huq and vpmadd52luq |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512IFMA52: u64 = <span class="number">0x40000000</span>; |
| |
| <span class="comment">// |
| // The processor is a full inorder (Silverthorne) processor |
| // |
| </span><span class="kw">pub const </span>CPU_FEATURE_F_INORDER: u64 = <span class="number">0x80000000</span>; |
| |
| <span class="comment">// AVX512 exponential and reciprocal instructions |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512ER: u64 = <span class="number">0x100000000</span>; |
| |
| <span class="comment">// AVX512 prefetch instructions |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512PF: u64 = <span class="number">0x200000000</span>; |
| |
| <span class="comment">// AVX-512 conflict detection instructions |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512CD: u64 = <span class="number">0x400000000</span>; |
| |
| <span class="comment">// Secure Hash Algorithm instructions (SHA) |
| </span><span class="kw">pub const </span>CPU_FEATURE_SHA: u64 = <span class="number">0x800000000</span>; |
| |
| <span class="comment">// Memory Protection Extensions (MPX) |
| </span><span class="kw">pub const </span>CPU_FEATURE_MPX: u64 = <span class="number">0x1000000000</span>; |
| |
| <span class="comment">// AVX512BW - AVX512 byte/word vector instruction set |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512BW: u64 = <span class="number">0x2000000000</span>; |
| |
| <span class="comment">// AVX512VL - 128/256-bit vector support of AVX512 instructions |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512VL: u64 = <span class="number">0x4000000000</span>; |
| |
| <span class="comment">// AVX512VBMI: vpermb, vpermi2b, vpermt2b and vpmultishiftqb |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512VBMI: u64 = <span class="number">0x8000000000</span>; |
| |
| <span class="comment">// AVX512_4FMAPS: Single Precision FMA for multivector(4 vector) operand. |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_4FMAPS: u64 = <span class="number">0x10000000000</span>; |
| |
| <span class="comment">// AVX512_4VNNIW: Vector Neural Network Instructions for multivector(4 vector) operand with word elements. |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_4VNNIW: u64 = <span class="number">0x20000000000</span>; |
| |
| <span class="comment">// AVX512_VPOPCNTDQ: 512-bit vector POPCNT instruction. |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_VPOPCNTDQ: u64 = <span class="number">0x40000000000</span>; |
| |
| <span class="comment">// AVX512_BITALG: vector bit algebra in AVX512 |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_BITALG: u64 = <span class="number">0x80000000000</span>; |
| |
| <span class="comment">// AVX512_VBMI2: additional byte, word, dword and qword capabilities |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_VBMI2: u64 = <span class="number">0x100000000000</span>; |
| |
| <span class="comment">// GFNI: Galois Field New Instructions. |
| </span><span class="kw">pub const </span>CPU_FEATURE_GFNI: u64 = <span class="number">0x200000000000</span>; |
| |
| <span class="comment">// VAES: vector AES instructions |
| </span><span class="kw">pub const </span>CPU_FEATURE_VAES: u64 = <span class="number">0x400000000000</span>; |
| |
| <span class="comment">// VPCLMULQDQ: Vector CLMUL instruction set. |
| </span><span class="kw">pub const </span>CPU_FEATURE_VPCLMULQDQ: u64 = <span class="number">0x800000000000</span>; |
| |
| <span class="comment">// AVX512_VNNI: vector Neural Network Instructions. |
| </span><span class="kw">pub const </span>CPU_FEATURE_AVX512_VNNI: u64 = <span class="number">0x1000000000000</span>; |
| |
| <span class="comment">// CLWB: Cache Line Write Back |
| </span><span class="kw">pub const </span>CPU_FEATURE_CLWB: u64 = <span class="number">0x2000000000000</span>; |
| |
| <span class="comment">// RDPID: Read Processor ID. |
| </span><span class="kw">pub const </span>CPU_FEATURE_RDPID: u64 = <span class="number">0x4000000000000</span>; |
| |
| <span class="comment">// IBT - Indirect branch tracking |
| </span><span class="kw">pub const </span>CPU_FEATURE_IBT: u64 = <span class="number">0x8000000000000</span>; |
| |
| <span class="comment">// Shadow stack |
| </span><span class="kw">pub const </span>CPU_FEATURE_SHSTK: u64 = <span class="number">0x10000000000000</span>; |
| |
| <span class="comment">// Intel Software Guard Extensions |
| </span><span class="kw">pub const </span>CPU_FEATURE_SGX: u64 = <span class="number">0x20000000000000</span>; |
| |
| <span class="comment">// Write back and do not invalidate cache |
| </span><span class="kw">pub const </span>CPU_FEATURE_WBNOINVD: u64 = <span class="number">0x40000000000000</span>; |
| |
| <span class="comment">// Platform configuration - 1 << 55 |
| </span><span class="kw">pub const </span>CPU_FEATURE_PCONFIG: u64 = <span class="number">0x80000000000000</span>; |
| |
| <span class="comment">// Reserved feature bits |
| </span><span class="kw">pub const </span>RESERVED_CPU_FEATURE_BIT: u64 = !(<span class="number">0x100000000000000 </span>- <span class="number">1</span>); |
| |
| <span class="comment">// Incompatible bits which we should unset in trts |
| </span><span class="kw">pub const </span>INCOMPAT_FEATURE_BIT: u64 = |
| (<span class="number">1 </span><< <span class="number">11</span>) | (<span class="number">1 </span><< <span class="number">12</span>) | (<span class="number">1 </span><< <span class="number">25</span>) | (<span class="number">1 </span><< <span class="number">26</span>) | (<span class="number">1 </span><< <span class="number">27</span>) | (<span class="number">1 </span><< <span class="number">28</span>); |
| </code></pre></div> |
| </section></div></main><div id="rustdoc-vars" data-root-path="../../" data-current-crate="sgx_types" data-themes="ayu,dark,light" data-resource-suffix="" data-rustdoc-version="1.66.0-nightly (5c8bff74b 2022-10-21)" ></div></body></html> |
