| <!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Source of the Rust file `/root/.cargo/registry/src/github.com-1ecc6299db9ec823/raw-cpuid-10.7.0/src/lib.rs`."><meta name="keywords" content="rust, rustlang, rust-lang"><title>lib.rs - source</title><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceSerif4-Regular.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../FiraSans-Regular.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../FiraSans-Medium.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceCodePro-Regular.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceSerif4-Bold.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../SourceCodePro-Semibold.ttf.woff2"><link rel="stylesheet" href="../../normalize.css"><link rel="stylesheet" href="../../rustdoc.css" id="mainThemeStyle"><link rel="stylesheet" href="../../ayu.css" disabled><link rel="stylesheet" href="../../dark.css" disabled><link rel="stylesheet" href="../../light.css" id="themeStyle"><script id="default-settings" ></script><script src="../../storage.js"></script><script defer src="../../source-script.js"></script><script defer src="../../source-files.js"></script><script defer src="../../main.js"></script><noscript><link rel="stylesheet" href="../../noscript.css"></noscript><link rel="alternate icon" type="image/png" href="../../favicon-16x16.png"><link rel="alternate icon" type="image/png" href="../../favicon-32x32.png"><link rel="icon" type="image/svg+xml" href="../../favicon.svg"></head><body class="rustdoc source"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="sidebar"><a class="sidebar-logo" href="../../raw_cpuid/index.html"><div class="logo-container"><img class="rust-logo" src="../../rust-logo.svg" alt="logo"></div></a></nav><main><div class="width-limiter"><nav class="sub"><a class="sub-logo-container" href="../../raw_cpuid/index.html"><img class="rust-logo" src="../../rust-logo.svg" alt="logo"></a><form class="search-form"><div class="search-container"><span></span><input class="search-input" name="search" autocomplete="off" spellcheck="false" placeholder="Click or press ‘S’ to search, ‘?’ for more options…" type="search"><div id="help-button" title="help" tabindex="-1"><a href="../../help.html">?</a></div><div id="settings-menu" tabindex="-1"><a href="../../settings.html" title="settings"><img width="22" height="22" alt="Change settings" src="../../wheel.svg"></a></div></div></form></nav><section id="main-content" class="content"><div class="example-wrap"><pre class="src-line-numbers"><span id="1">1</span> |
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| <span id="5460">5460</span> |
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| <span id="5471">5471</span> |
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| <span id="5473">5473</span> |
| <span id="5474">5474</span> |
| <span id="5475">5475</span> |
| <span id="5476">5476</span> |
| <span id="5477">5477</span> |
| <span id="5478">5478</span> |
| <span id="5479">5479</span> |
| <span id="5480">5480</span> |
| <span id="5481">5481</span> |
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| <span id="5488">5488</span> |
| <span id="5489">5489</span> |
| <span id="5490">5490</span> |
| <span id="5491">5491</span> |
| <span id="5492">5492</span> |
| <span id="5493">5493</span> |
| <span id="5494">5494</span> |
| <span id="5495">5495</span> |
| <span id="5496">5496</span> |
| <span id="5497">5497</span> |
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| <span id="5499">5499</span> |
| <span id="5500">5500</span> |
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| <span id="5502">5502</span> |
| <span id="5503">5503</span> |
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| <span id="5510">5510</span> |
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| <span id="5538">5538</span> |
| <span id="5539">5539</span> |
| <span id="5540">5540</span> |
| <span id="5541">5541</span> |
| <span id="5542">5542</span> |
| <span id="5543">5543</span> |
| <span id="5544">5544</span> |
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| <span id="5550">5550</span> |
| <span id="5551">5551</span> |
| <span id="5552">5552</span> |
| <span id="5553">5553</span> |
| <span id="5554">5554</span> |
| <span id="5555">5555</span> |
| <span id="5556">5556</span> |
| <span id="5557">5557</span> |
| <span id="5558">5558</span> |
| <span id="5559">5559</span> |
| <span id="5560">5560</span> |
| <span id="5561">5561</span> |
| <span id="5562">5562</span> |
| <span id="5563">5563</span> |
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| <span id="5570">5570</span> |
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| <span id="5578">5578</span> |
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| <span id="5581">5581</span> |
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| <span id="5583">5583</span> |
| <span id="5584">5584</span> |
| <span id="5585">5585</span> |
| <span id="5586">5586</span> |
| <span id="5587">5587</span> |
| <span id="5588">5588</span> |
| <span id="5589">5589</span> |
| <span id="5590">5590</span> |
| <span id="5591">5591</span> |
| <span id="5592">5592</span> |
| <span id="5593">5593</span> |
| <span id="5594">5594</span> |
| <span id="5595">5595</span> |
| <span id="5596">5596</span> |
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| <span id="5599">5599</span> |
| <span id="5600">5600</span> |
| <span id="5601">5601</span> |
| <span id="5602">5602</span> |
| <span id="5603">5603</span> |
| <span id="5604">5604</span> |
| <span id="5605">5605</span> |
| <span id="5606">5606</span> |
| <span id="5607">5607</span> |
| <span id="5608">5608</span> |
| <span id="5609">5609</span> |
| <span id="5610">5610</span> |
| <span id="5611">5611</span> |
| <span id="5612">5612</span> |
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| <span id="5635">5635</span> |
| <span id="5636">5636</span> |
| <span id="5637">5637</span> |
| <span id="5638">5638</span> |
| <span id="5639">5639</span> |
| <span id="5640">5640</span> |
| <span id="5641">5641</span> |
| <span id="5642">5642</span> |
| <span id="5643">5643</span> |
| <span id="5644">5644</span> |
| <span id="5645">5645</span> |
| <span id="5646">5646</span> |
| <span id="5647">5647</span> |
| <span id="5648">5648</span> |
| <span id="5649">5649</span> |
| <span id="5650">5650</span> |
| <span id="5651">5651</span> |
| <span id="5652">5652</span> |
| <span id="5653">5653</span> |
| <span id="5654">5654</span> |
| <span id="5655">5655</span> |
| <span id="5656">5656</span> |
| <span id="5657">5657</span> |
| <span id="5658">5658</span> |
| <span id="5659">5659</span> |
| <span id="5660">5660</span> |
| <span id="5661">5661</span> |
| <span id="5662">5662</span> |
| <span id="5663">5663</span> |
| </pre><pre class="rust"><code><span class="doccomment">//! A library to parse the x86 CPUID instruction, written in rust with no |
| //! external dependencies. The implementation closely resembles the Intel CPUID |
| //! manual description. The library works with no_std. |
| //! |
| //! ## Example |
| //! ```rust |
| //! use raw_cpuid::CpuId; |
| //! let cpuid = CpuId::new(); |
| //! |
| //! if let Some(vf) = cpuid.get_vendor_info() { |
| //! assert!(vf.as_str() == "GenuineIntel" || vf.as_str() == "AuthenticAMD"); |
| //! } |
| //! |
| //! let has_sse = cpuid.get_feature_info().map_or(false, |finfo| finfo.has_sse()); |
| //! if has_sse { |
| //! println!("CPU supports SSE!"); |
| //! } |
| //! |
| //! if let Some(cparams) = cpuid.get_cache_parameters() { |
| //! for cache in cparams { |
| //! let size = cache.associativity() * cache.physical_line_partitions() * cache.coherency_line_size() * cache.sets(); |
| //! println!("L{}-Cache size is {}", cache.level(), size); |
| //! } |
| //! } else { |
| //! println!("No cache parameter information available") |
| //! } |
| //! ``` |
| //! |
| //! # Platform support |
| //! |
| //! CPU vendors may choose to not support certain functions/leafs in cpuid or |
| //! only support them partially. We highlight this with the following emojis |
| //! throughout the documentation: |
| //! |
| //! - ✅: This struct/function is fully supported by the vendor. |
| //! - 🟡: This struct is partially supported by the vendor, refer to individual |
| //! functions for more information. |
| //! - ❌: This struct/function is not supported by the vendor. When queried on |
| //! this platform, we will return None/false/0 (or some other sane default). |
| //! - ❓: This struct/function is not supported by the vendor according to the |
| //! manual, but the in practice it still may return valid information. |
| //! |
| //! Note that the presence of a ✅ does not guarantee that a specific feature |
| //! will exist for your CPU -- just that it is potentially supported by the |
| //! vendor on some of its chips. You will still have to query it at runtime. |
| |
| </span><span class="attribute">#![cfg_attr(not(feature = <span class="string">"std"</span>), no_std)] |
| #![crate_name = <span class="string">"raw_cpuid"</span>] |
| #![crate_type = <span class="string">"lib"</span>] |
| |
| #[cfg(test)] |
| #[macro_use] |
| </span><span class="kw">extern crate </span>std; |
| |
| <span class="attribute">#[cfg(feature = <span class="string">"display"</span>)] |
| </span><span class="kw">pub mod </span>display; |
| <span class="kw">mod </span>extended; |
| <span class="attribute">#[cfg(test)] |
| </span><span class="kw">mod </span>tests; |
| <span class="attribute">#[cfg(feature = <span class="string">"serialize"</span>)] |
| #[macro_use] |
| </span><span class="kw">extern crate </span>serde_derive; |
| |
| <span class="attribute">#[cfg(feature = <span class="string">"serialize"</span>)] |
| </span><span class="kw">extern crate </span>serde; |
| |
| <span class="attribute">#[macro_use] |
| </span><span class="kw">extern crate </span>bitflags; |
| |
| <span class="attribute">#[cfg(all( |
| feature = <span class="string">"serialize"</span>, |
| not(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| )) |
| ))] |
| </span><span class="macro">core::compile_error!</span>(<span class="string">"Feature `serialize` is not supported on targets that do not have native cpuid. x86 and x86_64 targets with SGX and x86 targets without SSE are consider to not have native cpuid."</span>); |
| |
| <span class="doccomment">/// Uses Rust's `cpuid` function from the `arch` module. |
| </span><span class="attribute">#[cfg(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| ))] |
| </span><span class="kw">pub mod </span>native_cpuid { |
| <span class="kw">use </span><span class="kw">crate</span>::CpuIdResult; |
| |
| <span class="attribute">#[cfg(all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>))] |
| </span><span class="kw">use </span>core::arch::x86 <span class="kw">as </span>arch; |
| <span class="attribute">#[cfg(all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)))] |
| </span><span class="kw">use </span>core::arch::x86_64 <span class="kw">as </span>arch; |
| |
| <span class="kw">pub fn </span>cpuid_count(a: u32, c: u32) -> CpuIdResult { |
| <span class="comment">// Safety: CPUID is supported on all x86_64 CPUs and all x86 CPUs with |
| // SSE, but not by SGX. |
| </span><span class="kw">let </span>result = <span class="kw">unsafe </span>{ <span class="self">self</span>::arch::__cpuid_count(a, c) }; |
| |
| CpuIdResult { |
| eax: result.eax, |
| ebx: result.ebx, |
| ecx: result.ecx, |
| edx: result.edx, |
| } |
| } |
| } |
| |
| <span class="kw">use </span>core::fmt::{<span class="self">self</span>, Debug, Formatter}; |
| <span class="kw">use </span>core::mem::size_of; |
| <span class="kw">use </span>core::slice; |
| <span class="kw">use </span>core::str; |
| |
| <span class="kw">pub use </span>extended::<span class="kw-2">*</span>; |
| |
| <span class="attribute">#[cfg(not(test))] |
| </span><span class="kw">mod </span>std { |
| <span class="kw">pub use </span>core::ops; |
| <span class="kw">pub use </span>core::option; |
| } |
| |
| <span class="doccomment">/// Macro which queries cpuid directly. |
| /// |
| /// First parameter is cpuid leaf (EAX register value), |
| /// second optional parameter is the subleaf (ECX register value). |
| </span><span class="attribute">#[cfg(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| ))] |
| #[macro_export] |
| </span><span class="macro">macro_rules! </span>cpuid { |
| (<span class="macro-nonterminal">$eax</span>:expr) => { |
| <span class="macro-nonterminal">$crate::native_cpuid::cpuid_count</span>(<span class="macro-nonterminal">$eax </span><span class="kw">as </span>u32, <span class="number">0</span>) |
| }; |
| |
| (<span class="macro-nonterminal">$eax</span>:expr, <span class="macro-nonterminal">$ecx</span>:expr) => { |
| <span class="macro-nonterminal">$crate::native_cpuid::cpuid_count</span>(<span class="macro-nonterminal">$eax </span><span class="kw">as </span>u32, <span class="macro-nonterminal">$ecx </span><span class="kw">as </span>u32) |
| }; |
| } |
| |
| <span class="kw">fn </span>get_bits(r: u32, from: u32, to: u32) -> u32 { |
| <span class="macro">assert!</span>(from <= <span class="number">31</span>); |
| <span class="macro">assert!</span>(to <= <span class="number">31</span>); |
| <span class="macro">assert!</span>(from <= to); |
| |
| <span class="kw">let </span>mask = <span class="kw">match </span>to { |
| <span class="number">31 </span>=> <span class="number">0xffffffff</span>, |
| <span class="kw">_ </span>=> (<span class="number">1 </span><< (to + <span class="number">1</span>)) - <span class="number">1</span>, |
| }; |
| |
| (r & mask) >> from |
| } |
| |
| <span class="macro">macro_rules! </span>check_flag { |
| (<span class="macro-nonterminal">$doc</span>:meta, <span class="macro-nonterminal">$fun</span>:ident, <span class="macro-nonterminal">$flags</span>:ident, <span class="macro-nonterminal">$flag</span>:expr) => { |
| <span class="attribute">#[<span class="macro-nonterminal">$doc</span>] |
| </span><span class="kw">pub fn </span><span class="macro-nonterminal">$fun</span>(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.<span class="macro-nonterminal">$flags</span>.contains(<span class="macro-nonterminal">$flag</span>) |
| } |
| }; |
| } |
| |
| <span class="macro">macro_rules! </span>is_bit_set { |
| (<span class="macro-nonterminal">$field</span>:expr, <span class="macro-nonterminal">$bit</span>:expr) => { |
| <span class="macro-nonterminal">$field </span>& (<span class="number">1 </span><< <span class="macro-nonterminal">$bit</span>) > <span class="number">0 |
| </span>}; |
| } |
| |
| <span class="macro">macro_rules! </span>check_bit_fn { |
| (<span class="macro-nonterminal">$doc</span>:meta, <span class="macro-nonterminal">$fun</span>:ident, <span class="macro-nonterminal">$field</span>:ident, <span class="macro-nonterminal">$bit</span>:expr) => { |
| <span class="attribute">#[<span class="macro-nonterminal">$doc</span>] |
| </span><span class="kw">pub fn </span><span class="macro-nonterminal">$fun</span>(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="macro">is_bit_set!</span>(<span class="self">self</span>.<span class="macro-nonterminal">$field</span>, <span class="macro-nonterminal">$bit</span>) |
| } |
| }; |
| } |
| |
| <span class="doccomment">/// Implements function to read/write cpuid. |
| /// This allows to conveniently swap out the underlying cpuid implementation |
| /// with one that returns data that is deterministic (for unit-testing). |
| </span><span class="attribute">#[derive(Debug, Clone, Copy)] |
| </span><span class="kw">struct </span>CpuIdReader { |
| cpuid_fn: <span class="kw">fn</span>(u32, u32) -> CpuIdResult, |
| } |
| |
| <span class="kw">impl </span>CpuIdReader { |
| <span class="kw">fn </span>new(cpuid_fn: <span class="kw">fn</span>(u32, u32) -> CpuIdResult) -> <span class="self">Self </span>{ |
| <span class="self">Self </span>{ cpuid_fn } |
| } |
| |
| <span class="kw">fn </span>cpuid1(<span class="kw-2">&</span><span class="self">self</span>, eax: u32) -> CpuIdResult { |
| (<span class="self">self</span>.cpuid_fn)(eax, <span class="number">0</span>) |
| } |
| |
| <span class="kw">fn </span>cpuid2(<span class="kw-2">&</span><span class="self">self</span>, eax: u32, ecx: u32) -> CpuIdResult { |
| (<span class="self">self</span>.cpuid_fn)(eax, ecx) |
| } |
| } |
| |
| <span class="attribute">#[cfg(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| ))] |
| </span><span class="kw">impl </span>Default <span class="kw">for </span>CpuIdReader { |
| <span class="kw">fn </span>default() -> <span class="self">Self </span>{ |
| <span class="self">Self </span>{ |
| cpuid_fn: native_cpuid::cpuid_count, |
| } |
| } |
| } |
| |
| <span class="attribute">#[derive(Debug, Eq, PartialEq, Clone, Copy)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">enum </span>Vendor { |
| Intel, |
| Amd, |
| Unknown(u32, u32, u32), |
| } |
| |
| <span class="kw">impl </span>Vendor { |
| <span class="kw">fn </span>from_vendor_leaf(res: CpuIdResult) -> <span class="self">Self </span>{ |
| <span class="kw">let </span>vi = VendorInfo { |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }; |
| |
| <span class="kw">match </span>vi.as_str() { |
| <span class="string">"GenuineIntel" </span>=> Vendor::Intel, |
| <span class="string">"AuthenticAMD" </span>=> Vendor::Amd, |
| <span class="kw">_ </span>=> Vendor::Unknown(res.ebx, res.ecx, res.edx), |
| } |
| } |
| } |
| |
| <span class="doccomment">/// The main type used to query information about the CPU we're running on. |
| /// |
| /// Other structs can be accessed by going through this type. |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| #[derive(Clone, Copy)] |
| </span><span class="kw">pub struct </span>CpuId { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| <span class="doccomment">/// CPU vendor to differntiate cases where logic needs to differ in code . |
| </span>vendor: Vendor, |
| <span class="doccomment">/// How many basic leafs are supported (EAX < EAX_HYPERVISOR_INFO) |
| </span>supported_leafs: u32, |
| <span class="doccomment">/// How many extended leafs are supported (e.g., leafs with EAX > EAX_EXTENDED_FUNCTION_INFO) |
| </span>supported_extended_leafs: u32, |
| } |
| |
| <span class="attribute">#[cfg(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| ))] |
| </span><span class="kw">impl </span>Default <span class="kw">for </span>CpuId { |
| <span class="kw">fn </span>default() -> CpuId { |
| CpuId::with_cpuid_fn(native_cpuid::cpuid_count) |
| } |
| } |
| |
| <span class="doccomment">/// Low-level data-structure to store result of cpuid instruction. |
| </span><span class="attribute">#[derive(Copy, Clone, Eq, PartialEq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| #[repr(C)] |
| </span><span class="kw">pub struct </span>CpuIdResult { |
| <span class="doccomment">/// Return value EAX register |
| </span><span class="kw">pub </span>eax: u32, |
| <span class="doccomment">/// Return value EBX register |
| </span><span class="kw">pub </span>ebx: u32, |
| <span class="doccomment">/// Return value ECX register |
| </span><span class="kw">pub </span>ecx: u32, |
| <span class="doccomment">/// Return value EDX register |
| </span><span class="kw">pub </span>edx: u32, |
| } |
| |
| <span class="kw">impl </span>CpuIdResult { |
| <span class="kw">pub fn </span>all_zero(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax == <span class="number">0 </span>&& <span class="self">self</span>.ebx == <span class="number">0 </span>&& <span class="self">self</span>.ecx == <span class="number">0 </span>&& <span class="self">self</span>.edx == <span class="number">0 |
| </span>} |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CpuIdResult { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"CpuIdResult"</span>) |
| .field(<span class="string">"eax"</span>, <span class="kw-2">&</span>(<span class="self">self</span>.eax <span class="kw">as </span><span class="kw-2">*const </span>u32)) |
| .field(<span class="string">"ebx"</span>, <span class="kw-2">&</span>(<span class="self">self</span>.ebx <span class="kw">as </span><span class="kw-2">*const </span>u32)) |
| .field(<span class="string">"ecx"</span>, <span class="kw-2">&</span>(<span class="self">self</span>.ecx <span class="kw">as </span><span class="kw-2">*const </span>u32)) |
| .field(<span class="string">"edx"</span>, <span class="kw-2">&</span>(<span class="self">self</span>.edx <span class="kw">as </span><span class="kw-2">*const </span>u32)) |
| .finish() |
| } |
| } |
| |
| <span class="comment">// |
| // Normal leafs: |
| // |
| </span><span class="kw">const </span>EAX_VENDOR_INFO: u32 = <span class="number">0x0</span>; |
| <span class="kw">const </span>EAX_FEATURE_INFO: u32 = <span class="number">0x1</span>; |
| <span class="kw">const </span>EAX_CACHE_INFO: u32 = <span class="number">0x2</span>; |
| <span class="kw">const </span>EAX_PROCESSOR_SERIAL: u32 = <span class="number">0x3</span>; |
| <span class="kw">const </span>EAX_CACHE_PARAMETERS: u32 = <span class="number">0x4</span>; |
| <span class="kw">const </span>EAX_MONITOR_MWAIT_INFO: u32 = <span class="number">0x5</span>; |
| <span class="kw">const </span>EAX_THERMAL_POWER_INFO: u32 = <span class="number">0x6</span>; |
| <span class="kw">const </span>EAX_STRUCTURED_EXTENDED_FEATURE_INFO: u32 = <span class="number">0x7</span>; |
| <span class="kw">const </span>EAX_DIRECT_CACHE_ACCESS_INFO: u32 = <span class="number">0x9</span>; |
| <span class="kw">const </span>EAX_PERFORMANCE_MONITOR_INFO: u32 = <span class="number">0xA</span>; |
| <span class="kw">const </span>EAX_EXTENDED_TOPOLOGY_INFO: u32 = <span class="number">0xB</span>; |
| <span class="kw">const </span>EAX_EXTENDED_STATE_INFO: u32 = <span class="number">0xD</span>; |
| <span class="kw">const </span>EAX_RDT_MONITORING: u32 = <span class="number">0xF</span>; |
| <span class="kw">const </span>EAX_RDT_ALLOCATION: u32 = <span class="number">0x10</span>; |
| <span class="kw">const </span>EAX_SGX: u32 = <span class="number">0x12</span>; |
| <span class="kw">const </span>EAX_TRACE_INFO: u32 = <span class="number">0x14</span>; |
| <span class="kw">const </span>EAX_TIME_STAMP_COUNTER_INFO: u32 = <span class="number">0x15</span>; |
| <span class="kw">const </span>EAX_FREQUENCY_INFO: u32 = <span class="number">0x16</span>; |
| <span class="kw">const </span>EAX_SOC_VENDOR_INFO: u32 = <span class="number">0x17</span>; |
| <span class="kw">const </span>EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO: u32 = <span class="number">0x18</span>; |
| <span class="kw">const </span>EAX_EXTENDED_TOPOLOGY_INFO_V2: u32 = <span class="number">0x1F</span>; |
| |
| <span class="doccomment">/// Hypervisor leaf |
| </span><span class="kw">const </span>EAX_HYPERVISOR_INFO: u32 = <span class="number">0x4000_0000</span>; |
| |
| <span class="comment">// |
| // Extended leafs: |
| // |
| </span><span class="kw">const </span>EAX_EXTENDED_FUNCTION_INFO: u32 = <span class="number">0x8000_0000</span>; |
| <span class="kw">const </span>EAX_EXTENDED_PROCESSOR_AND_FEATURE_IDENTIFIERS: u32 = <span class="number">0x8000_0001</span>; |
| <span class="kw">const </span>EAX_EXTENDED_BRAND_STRING: u32 = <span class="number">0x8000_0002</span>; |
| <span class="kw">const </span>EAX_L1_CACHE_INFO: u32 = <span class="number">0x8000_0005</span>; |
| <span class="kw">const </span>EAX_L2_L3_CACHE_INFO: u32 = <span class="number">0x8000_0006</span>; |
| <span class="kw">const </span>EAX_ADVANCED_POWER_MGMT_INFO: u32 = <span class="number">0x8000_0007</span>; |
| <span class="kw">const </span>EAX_PROCESSOR_CAPACITY_INFO: u32 = <span class="number">0x8000_0008</span>; |
| <span class="kw">const </span>EAX_TLB_1GB_PAGE_INFO: u32 = <span class="number">0x8000_0019</span>; |
| <span class="kw">const </span>EAX_PERFORMANCE_OPTIMIZATION_INFO: u32 = <span class="number">0x8000_001A</span>; |
| <span class="kw">const </span>EAX_CACHE_PARAMETERS_AMD: u32 = <span class="number">0x8000_001D</span>; |
| <span class="kw">const </span>EAX_PROCESSOR_TOPOLOGY_INFO: u32 = <span class="number">0x8000_001E</span>; |
| <span class="kw">const </span>EAX_MEMORY_ENCRYPTION_INFO: u32 = <span class="number">0x8000_001F</span>; |
| <span class="kw">const </span>EAX_SVM_FEATURES: u32 = <span class="number">0x8000_000A</span>; |
| |
| <span class="kw">impl </span>CpuId { |
| <span class="doccomment">/// Return new CpuId struct. |
| </span><span class="attribute">#[cfg(any( |
| all(target_arch = <span class="string">"x86"</span>, not(target_env = <span class="string">"sgx"</span>), target_feature = <span class="string">"sse"</span>), |
| all(target_arch = <span class="string">"x86_64"</span>, not(target_env = <span class="string">"sgx"</span>)) |
| ))] |
| </span><span class="kw">pub fn </span>new() -> <span class="self">Self </span>{ |
| <span class="self">Self</span>::default() |
| } |
| |
| <span class="doccomment">/// Return new CpuId struct with custom reader function. |
| /// |
| /// This is useful for example when testing code or if we want to interpose |
| /// on the CPUID calls this library makes. |
| </span><span class="kw">pub fn </span>with_cpuid_fn(cpuid_fn: <span class="kw">fn</span>(u32, u32) -> CpuIdResult) -> <span class="self">Self </span>{ |
| <span class="kw">let </span>read = CpuIdReader::new(cpuid_fn); |
| <span class="kw">let </span>vendor_leaf = read.cpuid1(EAX_VENDOR_INFO); |
| <span class="kw">let </span>extended_leaf = read.cpuid1(EAX_EXTENDED_FUNCTION_INFO); |
| CpuId { |
| supported_leafs: vendor_leaf.eax, |
| supported_extended_leafs: extended_leaf.eax, |
| vendor: Vendor::from_vendor_leaf(vendor_leaf), |
| read, |
| } |
| } |
| |
| <span class="doccomment">/// Check if a non extended leaf (`val`) is supported. |
| </span><span class="kw">fn </span>leaf_is_supported(<span class="kw-2">&</span><span class="self">self</span>, val: u32) -> bool { |
| <span class="comment">// Exclude reserved functions/leafs on AMD |
| </span><span class="kw">if </span><span class="self">self</span>.vendor == Vendor::Amd && ((<span class="number">0x2</span>..=<span class="number">0x4</span>).contains(<span class="kw-2">&</span>val) || (<span class="number">0x8</span>..=<span class="number">0xa</span>).contains(<span class="kw-2">&</span>val)) |
| { |
| <span class="kw">return </span><span class="bool-val">false</span>; |
| } |
| |
| <span class="kw">if </span>val < EAX_EXTENDED_FUNCTION_INFO { |
| val <= <span class="self">self</span>.supported_leafs |
| } <span class="kw">else </span>{ |
| val <= <span class="self">self</span>.supported_extended_leafs |
| } |
| } |
| |
| <span class="doccomment">/// Return information about the vendor (LEAF=0x00). |
| /// |
| /// This leaf will contain a ASCII readable string such as "GenuineIntel" |
| /// for Intel CPUs or "AuthenticAMD" for AMD CPUs. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_vendor_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><VendorInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_VENDOR_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_VENDOR_INFO); |
| <span class="prelude-val">Some</span>(VendorInfo { |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Query a set of features that are available on this CPU (LEAF=0x01). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_feature_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><FeatureInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_FEATURE_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_FEATURE_INFO); |
| <span class="prelude-val">Some</span>(FeatureInfo { |
| vendor: <span class="self">self</span>.vendor, |
| eax: res.eax, |
| ebx: res.ebx, |
| edx_ecx: FeatureInfoFlags { |
| bits: (((res.edx <span class="kw">as </span>u64) << <span class="number">32</span>) | (res.ecx <span class="kw">as </span>u64)), |
| }, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Query basic information about caches (LEAF=0x02). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_cache_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><CacheInfoIter> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_CACHE_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_CACHE_INFO); |
| <span class="prelude-val">Some</span>(CacheInfoIter { |
| current: <span class="number">1</span>, |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Retrieve serial number of processor (LEAF=0x03). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_processor_serial(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorSerial> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_PROCESSOR_SERIAL) { |
| <span class="comment">// upper 64-96 bits are in res1.eax: |
| </span><span class="kw">let </span>res1 = <span class="self">self</span>.read.cpuid1(EAX_FEATURE_INFO); |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_PROCESSOR_SERIAL); |
| <span class="prelude-val">Some</span>(ProcessorSerial { |
| ecx: res.ecx, |
| edx: res.edx, |
| eax: res1.eax, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Retrieve more elaborate information about caches (LEAF=0x04 or 0x8000_001D). |
| /// |
| /// As opposed to [get_cache_info](CpuId::get_cache_info), this will tell us |
| /// about associativity, set size, line size of each level in the cache |
| /// hierarchy. |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_cache_parameters(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><CacheParametersIter> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_CACHE_PARAMETERS) |
| || (<span class="self">self</span>.vendor == Vendor::Amd && <span class="self">self</span>.leaf_is_supported(EAX_CACHE_PARAMETERS_AMD)) |
| { |
| <span class="prelude-val">Some</span>(CacheParametersIter { |
| read: <span class="self">self</span>.read, |
| leaf: <span class="kw">if </span><span class="self">self</span>.vendor == Vendor::Amd { |
| EAX_CACHE_PARAMETERS_AMD |
| } <span class="kw">else </span>{ |
| EAX_CACHE_PARAMETERS |
| }, |
| current: <span class="number">0</span>, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Information about how monitor/mwait works on this CPU (LEAF=0x05). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_monitor_mwait_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><MonitorMwaitInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_MONITOR_MWAIT_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_MONITOR_MWAIT_INFO); |
| <span class="prelude-val">Some</span>(MonitorMwaitInfo { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Query information about thermal and power management features of the CPU (LEAF=0x06). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_thermal_power_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ThermalPowerInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_THERMAL_POWER_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_THERMAL_POWER_INFO); |
| <span class="prelude-val">Some</span>(ThermalPowerInfo { |
| eax: ThermalPowerFeaturesEax { bits: res.eax }, |
| ebx: res.ebx, |
| ecx: ThermalPowerFeaturesEcx { bits: res.ecx }, |
| _edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Find out about more features supported by this CPU (LEAF=0x07). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_extended_feature_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedFeatures> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_STRUCTURED_EXTENDED_FEATURE_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_STRUCTURED_EXTENDED_FEATURE_INFO); |
| <span class="prelude-val">Some</span>(ExtendedFeatures { |
| _eax: res.eax, |
| ebx: ExtendedFeaturesEbx { bits: res.ebx }, |
| ecx: ExtendedFeaturesEcx { bits: res.ecx }, |
| _edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Direct cache access info (LEAF=0x09). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_direct_cache_access_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><DirectCacheAccessInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_DIRECT_CACHE_ACCESS_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_DIRECT_CACHE_ACCESS_INFO); |
| <span class="prelude-val">Some</span>(DirectCacheAccessInfo { eax: res.eax }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Info about performance monitoring (LEAF=0x0A). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_performance_monitoring_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><PerformanceMonitoringInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_PERFORMANCE_MONITOR_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_PERFORMANCE_MONITOR_INFO); |
| <span class="prelude-val">Some</span>(PerformanceMonitoringInfo { |
| eax: res.eax, |
| ebx: PerformanceMonitoringFeaturesEbx { bits: res.ebx }, |
| _ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Information about topology (LEAF=0x0B). |
| /// |
| /// Intel SDM suggests software should check support for leaf 0x1F |
| /// ([`CpuId::get_extended_topology_info_v2`]), and if supported, enumerate |
| /// that leaf instead. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_extended_topology_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedTopologyIter> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_TOPOLOGY_INFO) { |
| <span class="prelude-val">Some</span>(ExtendedTopologyIter { |
| read: <span class="self">self</span>.read, |
| level: <span class="number">0</span>, |
| is_v2: <span class="bool-val">false</span>, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Extended information about topology (LEAF=0x1F). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_extended_topology_info_v2(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedTopologyIter> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_TOPOLOGY_INFO_V2) { |
| <span class="prelude-val">Some</span>(ExtendedTopologyIter { |
| read: <span class="self">self</span>.read, |
| level: <span class="number">0</span>, |
| is_v2: <span class="bool-val">true</span>, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Information for saving/restoring extended register state (LEAF=0x0D). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_extended_state_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedStateInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_STATE_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_EXTENDED_STATE_INFO, <span class="number">0</span>); |
| <span class="kw">let </span>res1 = <span class="self">self</span>.read.cpuid2(EAX_EXTENDED_STATE_INFO, <span class="number">1</span>); |
| <span class="prelude-val">Some</span>(ExtendedStateInfo { |
| read: <span class="self">self</span>.read, |
| eax: ExtendedStateInfoXCR0Flags { bits: res.eax }, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| _edx: res.edx, |
| eax1: res1.eax, |
| ebx1: res1.ebx, |
| ecx1: ExtendedStateInfoXSSFlags { bits: res1.ecx }, |
| _edx1: res1.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Quality of service monitoring information (LEAF=0x0F). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_rdt_monitoring_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><RdtMonitoringInfo> { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_RDT_MONITORING); |
| |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_RDT_MONITORING) { |
| <span class="prelude-val">Some</span>(RdtMonitoringInfo { |
| read: <span class="self">self</span>.read, |
| ebx: res.ebx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Quality of service enforcement information (LEAF=0x10). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_rdt_allocation_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><RdtAllocationInfo> { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_RDT_ALLOCATION); |
| |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_RDT_ALLOCATION) { |
| <span class="prelude-val">Some</span>(RdtAllocationInfo { |
| read: <span class="self">self</span>.read, |
| ebx: res.ebx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Information about secure enclave support (LEAF=0x12). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_sgx_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SgxInfo> { |
| <span class="comment">// Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1. |
| </span><span class="self">self</span>.get_extended_feature_info().and_then(|info| { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_SGX) && info.has_sgx() { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_SGX, <span class="number">0</span>); |
| <span class="kw">let </span>res1 = <span class="self">self</span>.read.cpuid2(EAX_SGX, <span class="number">1</span>); |
| <span class="prelude-val">Some</span>(SgxInfo { |
| read: <span class="self">self</span>.read, |
| eax: res.eax, |
| ebx: res.ebx, |
| _ecx: res.ecx, |
| edx: res.edx, |
| eax1: res1.eax, |
| ebx1: res1.ebx, |
| ecx1: res1.ecx, |
| edx1: res1.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| }) |
| } |
| |
| <span class="doccomment">/// Intel Processor Trace Enumeration Information (LEAF=0x14). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_processor_trace_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorTraceInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_TRACE_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_TRACE_INFO, <span class="number">0</span>); |
| <span class="kw">let </span>res1 = <span class="kw">if </span>res.eax >= <span class="number">1 </span>{ |
| <span class="prelude-val">Some</span>(<span class="self">self</span>.read.cpuid2(EAX_TRACE_INFO, <span class="number">1</span>)) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>}; |
| |
| <span class="prelude-val">Some</span>(ProcessorTraceInfo { |
| _eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| _edx: res.edx, |
| leaf1: res1, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Time Stamp Counter/Core Crystal Clock Information (LEAF=0x15). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_tsc_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><TscInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_TIME_STAMP_COUNTER_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_TIME_STAMP_COUNTER_INFO, <span class="number">0</span>); |
| <span class="prelude-val">Some</span>(TscInfo { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Processor Frequency Information (LEAF=0x16). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_processor_frequency_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorFrequencyInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_FREQUENCY_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_FREQUENCY_INFO); |
| <span class="prelude-val">Some</span>(ProcessorFrequencyInfo { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Contains SoC vendor specific information (LEAF=0x17). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_soc_vendor_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SoCVendorInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_SOC_VENDOR_INFO) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_SOC_VENDOR_INFO); |
| <span class="prelude-val">Some</span>(SoCVendorInfo { |
| read: <span class="self">self</span>.read, |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Query deterministic address translation feature (LEAF=0x18). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_deterministic_address_translation_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><DatIter> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO) { |
| <span class="kw">let </span>res = <span class="self">self |
| </span>.read |
| .cpuid2(EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO, <span class="number">0</span>); |
| <span class="prelude-val">Some</span>(DatIter { |
| read: <span class="self">self</span>.read, |
| current: <span class="number">0</span>, |
| count: res.eax, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Returns information provided by the hypervisor, if running |
| /// in a virtual environment (LEAF=0x4000_00xx). |
| /// |
| /// # Platform |
| /// Needs to be a virtual CPU to be supported. |
| </span><span class="kw">pub fn </span>get_hypervisor_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><HypervisorInfo> { |
| <span class="comment">// We only fetch HypervisorInfo, if the Hypervisor-Flag is set. |
| // See https://github.com/gz/rust-cpuid/issues/52 |
| </span><span class="self">self</span>.get_feature_info() |
| .filter(|fi| fi.has_hypervisor()) |
| .map(|<span class="kw">_</span>| { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid1(EAX_HYPERVISOR_INFO); |
| <span class="kw">if </span>res.eax > <span class="number">0 </span>{ |
| <span class="prelude-val">Some</span>(HypervisorInfo { |
| read: <span class="self">self</span>.read, |
| res, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| }) |
| .flatten() |
| } |
| |
| <span class="doccomment">/// Extended Processor and Processor Feature Identifiers (LEAF=0x8000_0001). |
| /// |
| /// # Platforms |
| /// ✅ AMD 🟡 Intel |
| </span><span class="kw">pub fn </span>get_extended_processor_and_feature_identifiers( |
| <span class="kw-2">&</span><span class="self">self</span>, |
| ) -> <span class="prelude-ty">Option</span><ExtendedProcessorFeatureIdentifiers> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_PROCESSOR_AND_FEATURE_IDENTIFIERS) { |
| <span class="prelude-val">Some</span>(ExtendedProcessorFeatureIdentifiers::new( |
| <span class="self">self</span>.vendor, |
| <span class="self">self</span>.read |
| .cpuid1(EAX_EXTENDED_PROCESSOR_AND_FEATURE_IDENTIFIERS), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Retrieve processor brand string (LEAF=0x8000_000{2..4}). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>get_processor_brand_string(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorBrandString> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_BRAND_STRING) |
| && <span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_BRAND_STRING + <span class="number">1</span>) |
| && <span class="self">self</span>.leaf_is_supported(EAX_EXTENDED_BRAND_STRING + <span class="number">2</span>) |
| { |
| <span class="prelude-val">Some</span>(ProcessorBrandString::new([ |
| <span class="self">self</span>.read.cpuid1(EAX_EXTENDED_BRAND_STRING), |
| <span class="self">self</span>.read.cpuid1(EAX_EXTENDED_BRAND_STRING + <span class="number">1</span>), |
| <span class="self">self</span>.read.cpuid1(EAX_EXTENDED_BRAND_STRING + <span class="number">2</span>), |
| ])) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// L1 Instruction Cache Information (LEAF=0x8000_0005) |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel (reserved) |
| </span><span class="kw">pub fn </span>get_l1_cache_and_tlb_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><L1CacheTlbInfo> { |
| <span class="kw">if </span><span class="self">self</span>.vendor == Vendor::Amd && <span class="self">self</span>.leaf_is_supported(EAX_L1_CACHE_INFO) { |
| <span class="prelude-val">Some</span>(L1CacheTlbInfo::new(<span class="self">self</span>.read.cpuid1(EAX_L1_CACHE_INFO))) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// L2/L3 Cache and TLB Information (LEAF=0x8000_0006). |
| /// |
| /// # Platforms |
| /// ✅ AMD 🟡 Intel |
| </span><span class="kw">pub fn </span>get_l2_l3_cache_and_tlb_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><L2And3CacheTlbInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_L2_L3_CACHE_INFO) { |
| <span class="prelude-val">Some</span>(L2And3CacheTlbInfo::new( |
| <span class="self">self</span>.read.cpuid1(EAX_L2_L3_CACHE_INFO), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Advanced Power Management Information (LEAF=0x8000_0007). |
| /// |
| /// # Platforms |
| /// ✅ AMD 🟡 Intel |
| </span><span class="kw">pub fn </span>get_advanced_power_mgmt_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ApmInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_ADVANCED_POWER_MGMT_INFO) { |
| <span class="prelude-val">Some</span>(ApmInfo::new(<span class="self">self</span>.read.cpuid1(EAX_ADVANCED_POWER_MGMT_INFO))) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Processor Capacity Parameters and Extended Feature Identification (LEAF=0x8000_0008). |
| /// |
| /// # Platforms |
| /// ✅ AMD 🟡 Intel |
| </span><span class="kw">pub fn </span>get_processor_capacity_feature_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorCapacityAndFeatureInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_PROCESSOR_CAPACITY_INFO) { |
| <span class="prelude-val">Some</span>(ProcessorCapacityAndFeatureInfo::new( |
| <span class="self">self</span>.read.cpuid1(EAX_PROCESSOR_CAPACITY_INFO), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// This function provides information about the SVM features that the processory |
| /// supports. (LEAF=0x8000_000A) |
| /// |
| /// If SVM is not supported if [ExtendedProcessorFeatureIdentifiers::has_svm] is |
| /// false, this function is reserved then. |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel |
| </span><span class="kw">pub fn </span>get_svm_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SvmFeatures> { |
| <span class="kw">let </span>has_svm = <span class="self">self |
| </span>.get_extended_processor_and_feature_identifiers() |
| .map_or(<span class="bool-val">false</span>, |f| f.has_svm()); |
| <span class="kw">if </span>has_svm && <span class="self">self</span>.leaf_is_supported(EAX_SVM_FEATURES) { |
| <span class="prelude-val">Some</span>(SvmFeatures::new(<span class="self">self</span>.read.cpuid1(EAX_SVM_FEATURES))) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// TLB 1-GiB Pages Information (LEAF=0x8000_0019) |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel |
| </span><span class="kw">pub fn </span>get_tlb_1gb_page_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><Tlb1gbPageInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_TLB_1GB_PAGE_INFO) { |
| <span class="prelude-val">Some</span>(Tlb1gbPageInfo::new(<span class="self">self</span>.read.cpuid1(EAX_TLB_1GB_PAGE_INFO))) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Informations about performance optimization (LEAF=0x8000_001A) |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel (reserved) |
| </span><span class="kw">pub fn </span>get_performance_optimization_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><PerformanceOptimizationInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_PERFORMANCE_OPTIMIZATION_INFO) { |
| <span class="prelude-val">Some</span>(PerformanceOptimizationInfo::new( |
| <span class="self">self</span>.read.cpuid1(EAX_PERFORMANCE_OPTIMIZATION_INFO), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Informations about processor topology (LEAF=0x8000_001E) |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel (reserved) |
| </span><span class="kw">pub fn </span>get_processor_topology_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ProcessorTopologyInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_PROCESSOR_TOPOLOGY_INFO) { |
| <span class="prelude-val">Some</span>(ProcessorTopologyInfo::new( |
| <span class="self">self</span>.read.cpuid1(EAX_PROCESSOR_TOPOLOGY_INFO), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Informations about memory encryption support (LEAF=0x8000_001F) |
| /// |
| /// # Platforms |
| /// ✅ AMD ❌ Intel (reserved) |
| </span><span class="kw">pub fn </span>get_memory_encryption_info(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><MemoryEncryptionInfo> { |
| <span class="kw">if </span><span class="self">self</span>.leaf_is_supported(EAX_MEMORY_ENCRYPTION_INFO) { |
| <span class="prelude-val">Some</span>(MemoryEncryptionInfo::new( |
| <span class="self">self</span>.read.cpuid1(EAX_MEMORY_ENCRYPTION_INFO), |
| )) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CpuId { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"CpuId"</span>) |
| .field(<span class="string">"vendor"</span>, <span class="kw-2">&</span><span class="self">self</span>.vendor) |
| <span class="comment">// .field("supported_leafs", &(self.supported_leafs as *const u32)) |
| // .field("supported_extended_leafs", &(self.supported_extended_leafs as *const u32)) |
| </span>.field(<span class="string">"vendor_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_vendor_info()) |
| .field(<span class="string">"feature_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_feature_info()) |
| .field(<span class="string">"cache_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_cache_info()) |
| .field(<span class="string">"processor_serial"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_processor_serial()) |
| .field(<span class="string">"cache_parameters"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_cache_parameters()) |
| .field(<span class="string">"monitor_mwait_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_monitor_mwait_info()) |
| .field(<span class="string">"thermal_power_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_thermal_power_info()) |
| .field(<span class="string">"extended_feature_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_extended_feature_info()) |
| .field( |
| <span class="string">"direct_cache_access_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_direct_cache_access_info(), |
| ) |
| .field( |
| <span class="string">"performance_monitoring_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_performance_monitoring_info(), |
| ) |
| .field(<span class="string">"extended_topology_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_extended_topology_info()) |
| .field(<span class="string">"extended_state_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_extended_state_info()) |
| .field(<span class="string">"rdt_monitoring_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_rdt_monitoring_info()) |
| .field(<span class="string">"rdt_allocation_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_rdt_allocation_info()) |
| .field(<span class="string">"sgx_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_sgx_info()) |
| .field(<span class="string">"processor_trace_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_processor_trace_info()) |
| .field(<span class="string">"tsc_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_tsc_info()) |
| .field( |
| <span class="string">"processor_frequency_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_processor_frequency_info(), |
| ) |
| .field( |
| <span class="string">"deterministic_address_translation_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_deterministic_address_translation_info(), |
| ) |
| .field(<span class="string">"soc_vendor_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_soc_vendor_info()) |
| .field(<span class="string">"hypervisor_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_hypervisor_info()) |
| .field( |
| <span class="string">"extended_processor_and_feature_identifiers"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_extended_processor_and_feature_identifiers(), |
| ) |
| .field(<span class="string">"processor_brand_string"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_processor_brand_string()) |
| .field(<span class="string">"l1_cache_and_tlb_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_l1_cache_and_tlb_info()) |
| .field( |
| <span class="string">"l2_l3_cache_and_tlb_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_l2_l3_cache_and_tlb_info(), |
| ) |
| .field( |
| <span class="string">"advanced_power_mgmt_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_advanced_power_mgmt_info(), |
| ) |
| .field( |
| <span class="string">"processor_capacity_feature_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_processor_capacity_feature_info(), |
| ) |
| .field(<span class="string">"svm_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_svm_info()) |
| .field(<span class="string">"tlb_1gb_page_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_tlb_1gb_page_info()) |
| .field( |
| <span class="string">"performance_optimization_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_performance_optimization_info(), |
| ) |
| .field( |
| <span class="string">"processor_topology_info"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.get_processor_topology_info(), |
| ) |
| .field(<span class="string">"memory_encryption_info"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_memory_encryption_info()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Vendor Info String (LEAF=0x0) |
| /// |
| /// A string that can be for example "AuthenticAMD" or "GenuineIntel". |
| /// |
| /// # Technical Background |
| /// |
| /// The vendor info is a 12-byte (96 bit) long string stored in `ebx`, `edx` and |
| /// `ecx` by the corresponding `cpuid` instruction. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[derive(PartialEq, Eq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| #[repr(C)] |
| </span><span class="kw">pub struct </span>VendorInfo { |
| ebx: u32, |
| edx: u32, |
| ecx: u32, |
| } |
| |
| <span class="kw">impl </span>VendorInfo { |
| <span class="doccomment">/// Return vendor identification as human readable string. |
| </span><span class="kw">pub fn </span>as_str(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>str { |
| <span class="kw">let </span>brand_string_start = <span class="self">self </span><span class="kw">as </span><span class="kw-2">*const </span>VendorInfo <span class="kw">as </span><span class="kw-2">*const </span>u8; |
| <span class="kw">let </span>slice = <span class="kw">unsafe </span>{ |
| <span class="comment">// Safety: VendorInfo is laid out with repr(C) and exactly |
| // 12 byte long without any padding. |
| </span>slice::from_raw_parts(brand_string_start, size_of::<VendorInfo>()) |
| }; |
| |
| str::from_utf8(slice).unwrap_or(<span class="string">"InvalidVendorString"</span>) |
| } |
| |
| <span class="attribute">#[deprecated( |
| since = <span class="string">"10.0.0"</span>, |
| note = <span class="string">"Use idiomatic function name `as_str` instead" |
| </span>)] |
| </span><span class="kw">pub fn </span>as_string(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>str { |
| <span class="self">self</span>.as_str() |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>VendorInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"VendorInfo"</span>) |
| .field(<span class="string">"brand_string"</span>, <span class="kw-2">&</span><span class="self">self</span>.as_str()) |
| .finish() |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>VendorInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="macro">write!</span>(f, <span class="string">"{}"</span>, <span class="self">self</span>.as_str()) |
| } |
| } |
| |
| <span class="doccomment">/// Iterates over cache information (LEAF=0x02). |
| /// |
| /// This will just return an index into a static table of cache descriptions |
| /// (see [CACHE_INFO_TABLE](crate::CACHE_INFO_TABLE)). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[derive(PartialEq, Eq, Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>CacheInfoIter { |
| current: u32, |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>CacheInfoIter { |
| <span class="kw">type </span>Item = CacheInfo; |
| |
| <span class="doccomment">/// Iterate over all cache information. |
| </span><span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><CacheInfo> { |
| <span class="comment">// Every byte of the 4 register values returned by cpuid |
| // can contain information about a cache (except the |
| // very first one). |
| </span><span class="kw">if </span><span class="self">self</span>.current >= <span class="number">4 </span>* <span class="number">4 </span>{ |
| <span class="kw">return </span><span class="prelude-val">None</span>; |
| } |
| <span class="kw">let </span>reg_index = <span class="self">self</span>.current % <span class="number">4</span>; |
| <span class="kw">let </span>byte_index = <span class="self">self</span>.current / <span class="number">4</span>; |
| |
| <span class="kw">let </span>reg = <span class="kw">match </span>reg_index { |
| <span class="number">0 </span>=> <span class="self">self</span>.eax, |
| <span class="number">1 </span>=> <span class="self">self</span>.ebx, |
| <span class="number">2 </span>=> <span class="self">self</span>.ecx, |
| <span class="number">3 </span>=> <span class="self">self</span>.edx, |
| <span class="kw">_ </span>=> <span class="macro">unreachable!</span>(), |
| }; |
| |
| <span class="kw">let </span>byte = <span class="kw">match </span>byte_index { |
| <span class="number">0 </span>=> reg, |
| <span class="number">1 </span>=> reg >> <span class="number">8</span>, |
| <span class="number">2 </span>=> reg >> <span class="number">16</span>, |
| <span class="number">3 </span>=> reg >> <span class="number">24</span>, |
| <span class="kw">_ </span>=> <span class="macro">unreachable!</span>(), |
| } <span class="kw">as </span>u8; |
| |
| <span class="kw">if </span>byte == <span class="number">0 </span>{ |
| <span class="self">self</span>.current += <span class="number">1</span>; |
| <span class="kw">return </span><span class="self">self</span>.next(); |
| } |
| |
| <span class="kw">for </span>cache_info <span class="kw">in </span>CACHE_INFO_TABLE.iter() { |
| <span class="kw">if </span>cache_info.num == byte { |
| <span class="self">self</span>.current += <span class="number">1</span>; |
| <span class="kw">return </span><span class="prelude-val">Some</span>(<span class="kw-2">*</span>cache_info); |
| } |
| } |
| |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CacheInfoIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="doccomment">/// What type of cache are we dealing with? |
| </span><span class="attribute">#[derive(Copy, Clone, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>CacheInfoType { |
| General, |
| Cache, |
| TLB, |
| STLB, |
| DTLB, |
| Prefetch, |
| } |
| |
| <span class="doccomment">/// Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers). |
| </span><span class="attribute">#[derive(Copy, Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>CacheInfo { |
| <span class="doccomment">/// Number as retrieved from cpuid |
| </span><span class="kw">pub </span>num: u8, |
| <span class="doccomment">/// Cache type |
| </span><span class="kw">pub </span>typ: CacheInfoType, |
| } |
| |
| <span class="kw">impl </span>CacheInfo { |
| <span class="doccomment">/// Description of the cache (from Intel Manual) |
| </span><span class="kw">pub fn </span>desc(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span><span class="lifetime">'static </span>str { |
| <span class="kw">match </span><span class="self">self</span>.num { |
| <span class="number">0x00 </span>=> <span class="string">"Null descriptor, this byte contains no information"</span>, |
| <span class="number">0x01 </span>=> <span class="string">"Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries"</span>, |
| <span class="number">0x02 </span>=> <span class="string">"Instruction TLB: 4 MByte pages, fully associative, 2 entries"</span>, |
| <span class="number">0x03 </span>=> <span class="string">"Data TLB: 4 KByte pages, 4-way set associative, 64 entries"</span>, |
| <span class="number">0x04 </span>=> <span class="string">"Data TLB: 4 MByte pages, 4-way set associative, 8 entries"</span>, |
| <span class="number">0x05 </span>=> <span class="string">"Data TLB1: 4 MByte pages, 4-way set associative, 32 entries"</span>, |
| <span class="number">0x06 </span>=> <span class="string">"1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x08 </span>=> <span class="string">"1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x09 </span>=> <span class="string">"1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x0A </span>=> <span class="string">"1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size"</span>, |
| <span class="number">0x0B </span>=> <span class="string">"Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries"</span>, |
| <span class="number">0x0C </span>=> <span class="string">"1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x0D </span>=> <span class="string">"1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x0E </span>=> <span class="string">"1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size"</span>, |
| <span class="number">0x1D </span>=> <span class="string">"2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size"</span>, |
| <span class="number">0x21 </span>=> <span class="string">"2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0x22 </span>=> <span class="string">"3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x23 </span>=> <span class="string">"3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x24 </span>=> <span class="string">"2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0x25 </span>=> <span class="string">"3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x29 </span>=> <span class="string">"3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x2C </span>=> <span class="string">"1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0x30 </span>=> <span class="string">"1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0x40 </span>=> <span class="string">"No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache"</span>, |
| <span class="number">0x41 </span>=> <span class="string">"2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x42 </span>=> <span class="string">"2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x43 </span>=> <span class="string">"2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x44 </span>=> <span class="string">"2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x45 </span>=> <span class="string">"2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size"</span>, |
| <span class="number">0x46 </span>=> <span class="string">"3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x47 </span>=> <span class="string">"3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0x48 </span>=> <span class="string">"2nd-level cache: 3MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0x49 </span>=> <span class="string">"3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set ssociative, 64 byte line size"</span>, |
| <span class="number">0x4A </span>=> <span class="string">"3rd-level cache: 6MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0x4B </span>=> <span class="string">"3rd-level cache: 8MByte, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0x4C </span>=> <span class="string">"3rd-level cache: 12MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0x4D </span>=> <span class="string">"3rd-level cache: 16MByte, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0x4E </span>=> <span class="string">"2nd-level cache: 6MByte, 24-way set associative, 64 byte line size"</span>, |
| <span class="number">0x4F </span>=> <span class="string">"Instruction TLB: 4 KByte pages, 32 entries"</span>, |
| <span class="number">0x50 </span>=> <span class="string">"Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries"</span>, |
| <span class="number">0x51 </span>=> <span class="string">"Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries"</span>, |
| <span class="number">0x52 </span>=> <span class="string">"Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries"</span>, |
| <span class="number">0x55 </span>=> <span class="string">"Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries"</span>, |
| <span class="number">0x56 </span>=> <span class="string">"Data TLB0: 4 MByte pages, 4-way set associative, 16 entries"</span>, |
| <span class="number">0x57 </span>=> <span class="string">"Data TLB0: 4 KByte pages, 4-way associative, 16 entries"</span>, |
| <span class="number">0x59 </span>=> <span class="string">"Data TLB0: 4 KByte pages, fully associative, 16 entries"</span>, |
| <span class="number">0x5A </span>=> <span class="string">"Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries"</span>, |
| <span class="number">0x5B </span>=> <span class="string">"Data TLB: 4 KByte and 4 MByte pages, 64 entries"</span>, |
| <span class="number">0x5C </span>=> <span class="string">"Data TLB: 4 KByte and 4 MByte pages,128 entries"</span>, |
| <span class="number">0x5D </span>=> <span class="string">"Data TLB: 4 KByte and 4 MByte pages,256 entries"</span>, |
| <span class="number">0x60 </span>=> <span class="string">"1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0x61 </span>=> <span class="string">"Instruction TLB: 4 KByte pages, fully associative, 48 entries"</span>, |
| <span class="number">0x63 </span>=> <span class="string">"Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries"</span>, |
| <span class="number">0x64 </span>=> <span class="string">"Data TLB: 4 KByte pages, 4-way set associative, 512 entries"</span>, |
| <span class="number">0x66 </span>=> <span class="string">"1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x67 </span>=> <span class="string">"1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x68 </span>=> <span class="string">"1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x6A </span>=> <span class="string">"uTLB: 4 KByte pages, 8-way set associative, 64 entries"</span>, |
| <span class="number">0x6B </span>=> <span class="string">"DTLB: 4 KByte pages, 8-way set associative, 256 entries"</span>, |
| <span class="number">0x6C </span>=> <span class="string">"DTLB: 2M/4M pages, 8-way set associative, 128 entries"</span>, |
| <span class="number">0x6D </span>=> <span class="string">"DTLB: 1 GByte pages, fully associative, 16 entries"</span>, |
| <span class="number">0x70 </span>=> <span class="string">"Trace cache: 12 K-μop, 8-way set associative"</span>, |
| <span class="number">0x71 </span>=> <span class="string">"Trace cache: 16 K-μop, 8-way set associative"</span>, |
| <span class="number">0x72 </span>=> <span class="string">"Trace cache: 32 K-μop, 8-way set associative"</span>, |
| <span class="number">0x76 </span>=> <span class="string">"Instruction TLB: 2M/4M pages, fully associative, 8 entries"</span>, |
| <span class="number">0x78 </span>=> <span class="string">"2nd-level cache: 1 MByte, 4-way set associative, 64byte line size"</span>, |
| <span class="number">0x79 </span>=> <span class="string">"2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x7A </span>=> <span class="string">"2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x7B </span>=> <span class="string">"2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x7C </span>=> <span class="string">"2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector"</span>, |
| <span class="number">0x7D </span>=> <span class="string">"2nd-level cache: 2 MByte, 8-way set associative, 64byte line size"</span>, |
| <span class="number">0x7F </span>=> <span class="string">"2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size"</span>, |
| <span class="number">0x80 </span>=> <span class="string">"2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size"</span>, |
| <span class="number">0x82 </span>=> <span class="string">"2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size"</span>, |
| <span class="number">0x83 </span>=> <span class="string">"2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size"</span>, |
| <span class="number">0x84 </span>=> <span class="string">"2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size"</span>, |
| <span class="number">0x85 </span>=> <span class="string">"2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size"</span>, |
| <span class="number">0x86 </span>=> <span class="string">"2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0x87 </span>=> <span class="string">"2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0xA0 </span>=> <span class="string">"DTLB: 4k pages, fully associative, 32 entries"</span>, |
| <span class="number">0xB0 </span>=> <span class="string">"Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries"</span>, |
| <span class="number">0xB1 </span>=> <span class="string">"Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries"</span>, |
| <span class="number">0xB2 </span>=> <span class="string">"Instruction TLB: 4KByte pages, 4-way set associative, 64 entries"</span>, |
| <span class="number">0xB3 </span>=> <span class="string">"Data TLB: 4 KByte pages, 4-way set associative, 128 entries"</span>, |
| <span class="number">0xB4 </span>=> <span class="string">"Data TLB1: 4 KByte pages, 4-way associative, 256 entries"</span>, |
| <span class="number">0xB5 </span>=> <span class="string">"Instruction TLB: 4KByte pages, 8-way set associative, 64 entries"</span>, |
| <span class="number">0xB6 </span>=> <span class="string">"Instruction TLB: 4KByte pages, 8-way set associative, 128 entries"</span>, |
| <span class="number">0xBA </span>=> <span class="string">"Data TLB1: 4 KByte pages, 4-way associative, 64 entries"</span>, |
| <span class="number">0xC0 </span>=> <span class="string">"Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries"</span>, |
| <span class="number">0xC1 </span>=> <span class="string">"Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries"</span>, |
| <span class="number">0xC2 </span>=> <span class="string">"DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries"</span>, |
| <span class="number">0xC3 </span>=> <span class="string">"Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries."</span>, |
| <span class="number">0xC4 </span>=> <span class="string">"DTLB: 2M/4M Byte pages, 4-way associative, 32 entries"</span>, |
| <span class="number">0xCA </span>=> <span class="string">"Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries"</span>, |
| <span class="number">0xD0 </span>=> <span class="string">"3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0xD1 </span>=> <span class="string">"3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0xD2 </span>=> <span class="string">"3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size"</span>, |
| <span class="number">0xD6 </span>=> <span class="string">"3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0xD7 </span>=> <span class="string">"3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0xD8 </span>=> <span class="string">"3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size"</span>, |
| <span class="number">0xDC </span>=> <span class="string">"3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0xDD </span>=> <span class="string">"3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0xDE </span>=> <span class="string">"3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size"</span>, |
| <span class="number">0xE2 </span>=> <span class="string">"3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0xE3 </span>=> <span class="string">"3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0xE4 </span>=> <span class="string">"3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size"</span>, |
| <span class="number">0xEA </span>=> <span class="string">"3rd-level cache: 12MByte, 24-way set associative, 64 byte line size"</span>, |
| <span class="number">0xEB </span>=> <span class="string">"3rd-level cache: 18MByte, 24-way set associative, 64 byte line size"</span>, |
| <span class="number">0xEC </span>=> <span class="string">"3rd-level cache: 24MByte, 24-way set associative, 64 byte line size"</span>, |
| <span class="number">0xF0 </span>=> <span class="string">"64-Byte prefetching"</span>, |
| <span class="number">0xF1 </span>=> <span class="string">"128-Byte prefetching"</span>, |
| <span class="number">0xFE </span>=> <span class="string">"CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters."</span>, |
| <span class="number">0xFF </span>=> <span class="string">"CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters"</span>, |
| <span class="kw">_ </span>=> <span class="string">"Unknown cache type!" |
| </span>} |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CacheInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| f.debug_struct(<span class="string">"CacheInfo"</span>) |
| .field(<span class="string">"typ"</span>, <span class="kw-2">&</span><span class="self">self</span>.typ) |
| .field(<span class="string">"desc"</span>, <span class="kw-2">&</span><span class="self">self</span>.desc()) |
| .finish() |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>CacheInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="kw">let </span>typ = <span class="kw">match </span><span class="self">self</span>.typ { |
| CacheInfoType::General => <span class="string">"N/A"</span>, |
| CacheInfoType::Cache => <span class="string">"Cache"</span>, |
| CacheInfoType::TLB => <span class="string">"TLB"</span>, |
| CacheInfoType::STLB => <span class="string">"STLB"</span>, |
| CacheInfoType::DTLB => <span class="string">"DTLB"</span>, |
| CacheInfoType::Prefetch => <span class="string">"Prefetcher"</span>, |
| }; |
| |
| <span class="macro">write!</span>(f, <span class="string">"{:x}:\t {}: {}"</span>, <span class="self">self</span>.num, typ, <span class="self">self</span>.desc()) |
| } |
| } |
| |
| <span class="doccomment">/// This table is taken from Intel manual (Section CPUID instruction). |
| </span><span class="kw">pub const </span>CACHE_INFO_TABLE: [CacheInfo; <span class="number">108</span>] = [ |
| CacheInfo { |
| num: <span class="number">0x00</span>, |
| typ: CacheInfoType::General, |
| }, |
| CacheInfo { |
| num: <span class="number">0x01</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x02</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x03</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x04</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x05</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x06</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x08</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x09</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x0A</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x0B</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x0C</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x0D</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x0E</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x21</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x22</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x23</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x24</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x25</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x29</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x2C</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x30</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x40</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x41</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x42</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x43</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x44</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x45</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x46</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x47</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x48</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x49</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4A</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4B</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4C</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4D</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4E</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x4F</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x50</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x51</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x52</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x55</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x56</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x57</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x59</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x5A</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x5B</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x5C</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x5D</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x60</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x61</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x63</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x66</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x67</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x68</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x6A</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x6B</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x6C</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x6D</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x70</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x71</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x72</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x76</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0x78</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x79</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x7A</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x7B</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x7C</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x7D</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x7F</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x80</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x82</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x83</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x84</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x85</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x86</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0x87</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB0</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB1</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB2</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB3</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB4</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB5</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xB6</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xBA</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xC0</span>, |
| typ: CacheInfoType::TLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xC1</span>, |
| typ: CacheInfoType::STLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xC2</span>, |
| typ: CacheInfoType::DTLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xCA</span>, |
| typ: CacheInfoType::STLB, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD0</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD1</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD2</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD6</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD7</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xD8</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xDC</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xDD</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xDE</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xE2</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xE3</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xE4</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xEA</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xEB</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xEC</span>, |
| typ: CacheInfoType::Cache, |
| }, |
| CacheInfo { |
| num: <span class="number">0xF0</span>, |
| typ: CacheInfoType::Prefetch, |
| }, |
| CacheInfo { |
| num: <span class="number">0xF1</span>, |
| typ: CacheInfoType::Prefetch, |
| }, |
| CacheInfo { |
| num: <span class="number">0xFE</span>, |
| typ: CacheInfoType::General, |
| }, |
| CacheInfo { |
| num: <span class="number">0xFF</span>, |
| typ: CacheInfoType::General, |
| }, |
| ]; |
| |
| <span class="doccomment">/// Processor Serial Number (LEAF=0x3). |
| /// |
| /// # Deprecated |
| /// |
| /// Processor serial number (PSN) is not supported in the Pentium 4 processor or |
| /// later. On all models, use the PSN flag (returned using CPUID) to check for |
| /// PSN support before accessing the feature. |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[derive(PartialEq, Eq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ProcessorSerial { |
| <span class="doccomment">/// Lower bits |
| </span>ecx: u32, |
| <span class="doccomment">/// Middle bits |
| </span>edx: u32, |
| <span class="doccomment">/// Upper bits (come from leaf 0x1) |
| </span>eax: u32, |
| } |
| |
| <span class="kw">impl </span>ProcessorSerial { |
| <span class="doccomment">/// Bits 00-31 of 96 bit processor serial number. |
| /// |
| /// (Available in Pentium III processor only; otherwise, the value in this register is reserved.) |
| </span><span class="kw">pub fn </span>serial_lower(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="doccomment">/// Bits 32-63 of 96 bit processor serial number. |
| /// |
| /// (Available in Pentium III processor only; otherwise, the value in this register is reserved.) |
| </span><span class="kw">pub fn </span>serial_middle(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.edx |
| } |
| |
| <span class="doccomment">/// Bits 64-96 of 96 bit processor serial number. |
| </span><span class="kw">pub fn </span>serial_upper(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.eax |
| } |
| |
| <span class="doccomment">/// Combination of bits 00-31 and 32-63 of 96 bit processor serial number. |
| </span><span class="kw">pub fn </span>serial(<span class="kw-2">&</span><span class="self">self</span>) -> u64 { |
| (<span class="self">self</span>.serial_lower() <span class="kw">as </span>u64) | (<span class="self">self</span>.serial_middle() <span class="kw">as </span>u64) << <span class="number">32 |
| </span>} |
| |
| <span class="doccomment">/// 96 bit processor serial number. |
| </span><span class="kw">pub fn </span>serial_all(<span class="kw-2">&</span><span class="self">self</span>) -> u128 { |
| (<span class="self">self</span>.serial_lower() <span class="kw">as </span>u128) |
| | ((<span class="self">self</span>.serial_middle() <span class="kw">as </span>u128) << <span class="number">32</span>) |
| | ((<span class="self">self</span>.serial_upper() <span class="kw">as </span>u128) << <span class="number">64</span>) |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ProcessorSerial { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"ProcessorSerial"</span>) |
| .field(<span class="string">"serial_lower"</span>, <span class="kw-2">&</span><span class="self">self</span>.serial_lower()) |
| .field(<span class="string">"serial_middle"</span>, <span class="kw-2">&</span><span class="self">self</span>.serial_middle()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Processor and Processor Feature Identifiers (LEAF=0x01). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>FeatureInfo { |
| vendor: Vendor, |
| eax: u32, |
| ebx: u32, |
| edx_ecx: FeatureInfoFlags, |
| } |
| |
| <span class="kw">impl </span>FeatureInfo { |
| <span class="doccomment">/// Version Information: Extended Family |
| </span><span class="kw">pub fn </span>extended_family_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">20</span>, <span class="number">27</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Version Information: Extended Model |
| </span><span class="kw">pub fn </span>extended_model_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">16</span>, <span class="number">19</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Version Information: Family |
| </span><span class="kw">pub fn </span>base_family_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">8</span>, <span class="number">11</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Version Information: Model |
| </span><span class="kw">pub fn </span>base_model_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">4</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="kw">pub fn </span>family_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| <span class="kw">let </span>base_family_id = <span class="self">self</span>.base_family_id(); |
| <span class="kw">let </span>extended_family_id = <span class="self">self</span>.extended_family_id(); |
| <span class="kw">let </span>just_use_base = (<span class="self">self</span>.vendor == Vendor::Amd && base_family_id < <span class="number">0xf</span>) |
| || (<span class="self">self</span>.vendor == Vendor::Intel && base_family_id != <span class="number">0xf</span>); |
| |
| <span class="kw">if </span>just_use_base { |
| base_family_id |
| } <span class="kw">else </span>{ |
| base_family_id + extended_family_id |
| } |
| } |
| |
| <span class="kw">pub fn </span>model_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| <span class="kw">let </span>base_family_id = <span class="self">self</span>.base_family_id(); |
| <span class="kw">let </span>base_model_id = <span class="self">self</span>.base_model_id(); |
| <span class="kw">let </span>extended_model_id = <span class="self">self</span>.extended_model_id(); |
| <span class="kw">let </span>just_use_base = (<span class="self">self</span>.vendor == Vendor::Amd && base_family_id < <span class="number">0xf</span>) |
| || (<span class="self">self</span>.vendor == Vendor::Intel && base_family_id != <span class="number">0xf </span>&& base_family_id != <span class="number">0x6</span>); |
| |
| <span class="kw">if </span>just_use_base { |
| base_model_id |
| } <span class="kw">else </span>{ |
| (extended_model_id << <span class="number">4</span>) | base_model_id |
| } |
| } |
| |
| <span class="doccomment">/// Version Information: Stepping ID |
| </span><span class="kw">pub fn </span>stepping_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">3</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Brand Index |
| </span><span class="kw">pub fn </span>brand_index(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// CLFLUSH line size (Value ∗ 8 = cache line size in bytes) |
| </span><span class="kw">pub fn </span>cflush_cache_line_size(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">8</span>, <span class="number">15</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Initial APIC ID |
| </span><span class="kw">pub fn </span>initial_local_apic_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">24</span>, <span class="number">31</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Maximum number of addressable IDs for logical processors in this physical package. |
| </span><span class="kw">pub fn </span>max_logical_processor_ids(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">16</span>, <span class="number">23</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor \ |
| supports this technology."</span>, |
| has_sse3, |
| edx_ecx, |
| FeatureInfoFlags::SSE3 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ \ |
| instruction"</span>, |
| has_pclmulqdq, |
| edx_ecx, |
| FeatureInfoFlags::PCLMULQDQ |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"64-bit DS Area. A value of 1 indicates the processor supports DS area \ |
| using 64-bit layout"</span>, |
| has_ds_area, |
| edx_ecx, |
| FeatureInfoFlags::DTES64 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"MONITOR/MWAIT. A value of 1 indicates the processor supports this feature."</span>, |
| has_monitor_mwait, |
| edx_ecx, |
| FeatureInfoFlags::MONITOR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"CPL Qualified Debug Store. A value of 1 indicates the processor supports \ |
| the extensions to the Debug Store feature to allow for branch message \ |
| storage qualified by CPL."</span>, |
| has_cpl, |
| edx_ecx, |
| FeatureInfoFlags::DSCPL |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Virtual Machine Extensions. A value of 1 indicates that the processor \ |
| supports this technology."</span>, |
| has_vmx, |
| edx_ecx, |
| FeatureInfoFlags::VMX |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Safer Mode Extensions. A value of 1 indicates that the processor supports \ |
| this technology. See Chapter 5, Safer Mode Extensions Reference."</span>, |
| has_smx, |
| edx_ecx, |
| FeatureInfoFlags::SMX |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Enhanced Intel SpeedStep® technology. A value of 1 indicates that the \ |
| processor supports this technology."</span>, |
| has_eist, |
| edx_ecx, |
| FeatureInfoFlags::EIST |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Thermal Monitor 2. A value of 1 indicates whether the processor supports \ |
| this technology."</span>, |
| has_tm2, |
| edx_ecx, |
| FeatureInfoFlags::TM2 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates the presence of the Supplemental Streaming SIMD \ |
| Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions \ |
| are not present in the processor"</span>, |
| has_ssse3, |
| edx_ecx, |
| FeatureInfoFlags::SSSE3 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"L1 Context ID. A value of 1 indicates the L1 data cache mode can be set \ |
| to either adaptive mode or shared mode. A value of 0 indicates this \ |
| feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit \ |
| 24 (L1 Data Cache Context Mode) for details."</span>, |
| has_cnxtid, |
| edx_ecx, |
| FeatureInfoFlags::CNXTID |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates the processor supports FMA extensions using YMM \ |
| state."</span>, |
| has_fma, |
| edx_ecx, |
| FeatureInfoFlags::FMA |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"CMPXCHG16B Available. A value of 1 indicates that the feature is \ |
| available. See the CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes \ |
| section. 14"</span>, |
| has_cmpxchg16b, |
| edx_ecx, |
| FeatureInfoFlags::CMPXCHG16B |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Perfmon and Debug Capability: A value of 1 indicates the processor \ |
| supports the performance and debug feature indication MSR \ |
| IA32_PERF_CAPABILITIES."</span>, |
| has_pdcm, |
| edx_ecx, |
| FeatureInfoFlags::PDCM |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Process-context identifiers. A value of 1 indicates that the processor \ |
| supports PCIDs and the software may set CR4.PCIDE to 1."</span>, |
| has_pcid, |
| edx_ecx, |
| FeatureInfoFlags::PCID |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates the processor supports the ability to prefetch \ |
| data from a memory mapped device."</span>, |
| has_dca, |
| edx_ecx, |
| FeatureInfoFlags::DCA |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports SSE4.1."</span>, |
| has_sse41, |
| edx_ecx, |
| FeatureInfoFlags::SSE41 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports SSE4.2."</span>, |
| has_sse42, |
| edx_ecx, |
| FeatureInfoFlags::SSE42 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports x2APIC feature."</span>, |
| has_x2apic, |
| edx_ecx, |
| FeatureInfoFlags::X2APIC |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports MOVBE instruction."</span>, |
| has_movbe, |
| edx_ecx, |
| FeatureInfoFlags::MOVBE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports the POPCNT instruction."</span>, |
| has_popcnt, |
| edx_ecx, |
| FeatureInfoFlags::POPCNT |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processors local APIC timer supports \ |
| one-shot operation using a TSC deadline value."</span>, |
| has_tsc_deadline, |
| edx_ecx, |
| FeatureInfoFlags::TSC_DEADLINE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports the AESNI instruction \ |
| extensions."</span>, |
| has_aesni, |
| edx_ecx, |
| FeatureInfoFlags::AESNI |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the processor supports the XSAVE/XRSTOR \ |
| processor extended states feature, the XSETBV/XGETBV instructions, and \ |
| XCR0."</span>, |
| has_xsave, |
| edx_ecx, |
| FeatureInfoFlags::XSAVE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions \ |
| to access XCR0, and support for processor extended state management using \ |
| XSAVE/XRSTOR."</span>, |
| has_oxsave, |
| edx_ecx, |
| FeatureInfoFlags::OSXSAVE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates the processor supports the AVX instruction \ |
| extensions."</span>, |
| has_avx, |
| edx_ecx, |
| FeatureInfoFlags::AVX |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that processor supports 16-bit floating-point \ |
| conversion instructions."</span>, |
| has_f16c, |
| edx_ecx, |
| FeatureInfoFlags::F16C |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates that processor supports RDRAND instruction."</span>, |
| has_rdrand, |
| edx_ecx, |
| FeatureInfoFlags::RDRAND |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"A value of 1 indicates the indicates the presence of a hypervisor."</span>, |
| has_hypervisor, |
| edx_ecx, |
| FeatureInfoFlags::HYPERVISOR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Floating Point Unit On-Chip. The processor contains an x87 FPU."</span>, |
| has_fpu, |
| edx_ecx, |
| FeatureInfoFlags::FPU |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including \ |
| CR4.VME for controlling the feature, CR4.PVI for protected mode virtual \ |
| interrupts, software interrupt indirection, expansion of the TSS with the \ |
| software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags."</span>, |
| has_vme, |
| edx_ecx, |
| FeatureInfoFlags::VME |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Debugging Extensions. Support for I/O breakpoints, including CR4.DE for \ |
| controlling the feature, and optional trapping of accesses to DR4 and DR5."</span>, |
| has_de, |
| edx_ecx, |
| FeatureInfoFlags::DE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Page Size Extension. Large pages of size 4 MByte are supported, including \ |
| CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page \ |
| Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs."</span>, |
| has_pse, |
| edx_ecx, |
| FeatureInfoFlags::PSE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD \ |
| for controlling privilege."</span>, |
| has_tsc, |
| edx_ecx, |
| FeatureInfoFlags::TSC |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and \ |
| WRMSR instructions are supported. Some of the MSRs are implementation \ |
| dependent."</span>, |
| has_msr, |
| edx_ecx, |
| FeatureInfoFlags::MSR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Physical Address Extension. Physical addresses greater than 32 bits are \ |
| supported: extended page table entry formats, an extra level in the page \ |
| translation tables is defined, 2-MByte pages are supported instead of 4 \ |
| Mbyte pages if PAE bit is 1."</span>, |
| has_pae, |
| edx_ecx, |
| FeatureInfoFlags::PAE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Machine Check Exception. Exception 18 is defined for Machine Checks, \ |
| including CR4.MCE for controlling the feature. This feature does not \ |
| define the model-specific implementations of machine-check error logging, \ |
| reporting, and processor shutdowns. Machine Check exception handlers may \ |
| have to depend on processor version to do model specific processing of \ |
| the exception, or test for the presence of the Machine Check feature."</span>, |
| has_mce, |
| edx_ecx, |
| FeatureInfoFlags::MCE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) \ |
| instruction is supported (implicitly locked and atomic)."</span>, |
| has_cmpxchg8b, |
| edx_ecx, |
| FeatureInfoFlags::CX8 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"APIC On-Chip. The processor contains an Advanced Programmable Interrupt \ |
| Controller (APIC), responding to memory mapped commands in the physical \ |
| address range FFFE0000H to FFFE0FFFH (by default - some processors permit \ |
| the APIC to be relocated)."</span>, |
| has_apic, |
| edx_ecx, |
| FeatureInfoFlags::APIC |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and \ |
| associated MSRs are supported."</span>, |
| has_sysenter_sysexit, |
| edx_ecx, |
| FeatureInfoFlags::SEP |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR \ |
| contains feature bits that describe what memory types are supported, how \ |
| many variable MTRRs are supported, and whether fixed MTRRs are supported."</span>, |
| has_mtrr, |
| edx_ecx, |
| FeatureInfoFlags::MTRR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Page Global Bit. The global bit is supported in paging-structure entries \ |
| that map a page, indicating TLB entries that are common to different \ |
| processes and need not be flushed. The CR4.PGE bit controls this feature."</span>, |
| has_pge, |
| edx_ecx, |
| FeatureInfoFlags::PGE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Machine Check Architecture. A value of 1 indicates the Machine Check \ |
| Architecture of reporting machine errors is supported. The MCG_CAP MSR \ |
| contains feature bits describing how many banks of error reporting MSRs \ |
| are supported."</span>, |
| has_mca, |
| edx_ecx, |
| FeatureInfoFlags::MCA |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Conditional Move Instructions. The conditional move instruction CMOV is \ |
| supported. In addition, if x87 FPU is present as indicated by the \ |
| CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported"</span>, |
| has_cmov, |
| edx_ecx, |
| FeatureInfoFlags::CMOV |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Page Attribute Table. Page Attribute Table is supported. This feature \ |
| augments the Memory Type Range Registers (MTRRs), allowing an operating \ |
| system to specify attributes of memory accessed through a linear address \ |
| on a 4KB granularity."</span>, |
| has_pat, |
| edx_ecx, |
| FeatureInfoFlags::PAT |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"36-Bit Page Size Extension. 4-MByte pages addressing physical memory \ |
| beyond 4 GBytes are supported with 32-bit paging. This feature indicates \ |
| that upper bits of the physical address of a 4-MByte page are encoded in \ |
| bits 20:13 of the page-directory entry. Such physical addresses are \ |
| limited by MAXPHYADDR and may be up to 40 bits in size."</span>, |
| has_pse36, |
| edx_ecx, |
| FeatureInfoFlags::PSE36 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Processor Serial Number. The processor supports the 96-bit processor \ |
| identification number feature and the feature is enabled."</span>, |
| has_psn, |
| edx_ecx, |
| FeatureInfoFlags::PSN |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"CLFLUSH Instruction. CLFLUSH Instruction is supported."</span>, |
| has_clflush, |
| edx_ecx, |
| FeatureInfoFlags::CLFSH |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Debug Store. The processor supports the ability to write debug \ |
| information into a memory resident buffer. This feature is used by the \ |
| branch trace store (BTS) and processor event-based sampling (PEBS) \ |
| facilities (see Chapter 23, Introduction to Virtual-Machine Extensions, \ |
| in the Intel® 64 and IA-32 Architectures Software Developers Manual, \ |
| Volume 3C)."</span>, |
| has_ds, |
| edx_ecx, |
| FeatureInfoFlags::DS |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Thermal Monitor and Software Controlled Clock Facilities. The processor \ |
| implements internal MSRs that allow processor temperature to be monitored \ |
| and processor performance to be modulated in predefined duty cycles under \ |
| software control."</span>, |
| has_acpi, |
| edx_ecx, |
| FeatureInfoFlags::ACPI |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Intel MMX Technology. The processor supports the Intel MMX technology."</span>, |
| has_mmx, |
| edx_ecx, |
| FeatureInfoFlags::MMX |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are \ |
| supported for fast save and restore of the floating point context. \ |
| Presence of this bit also indicates that CR4.OSFXSR is available for an \ |
| operating system to indicate that it supports the FXSAVE and FXRSTOR \ |
| instructions."</span>, |
| has_fxsave_fxstor, |
| edx_ecx, |
| FeatureInfoFlags::FXSR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"SSE. The processor supports the SSE extensions."</span>, |
| has_sse, |
| edx_ecx, |
| FeatureInfoFlags::SSE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"SSE2. The processor supports the SSE2 extensions."</span>, |
| has_sse2, |
| edx_ecx, |
| FeatureInfoFlags::SSE2 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Self Snoop. The processor supports the management of conflicting memory \ |
| types by performing a snoop of its own cache structure for transactions \ |
| issued to the bus."</span>, |
| has_ss, |
| edx_ecx, |
| FeatureInfoFlags::SS |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates \ |
| there is only a single logical processor in the package and software \ |
| should assume only a single APIC ID is reserved. A value of 1 for HTT \ |
| indicates the value in CPUID.1.EBX\\[23:16\\] (the Maximum number of \ |
| addressable IDs for logical processors in this package) is valid for the \ |
| package."</span>, |
| has_htt, |
| edx_ecx, |
| FeatureInfoFlags::HTT |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Thermal Monitor. The processor implements the thermal monitor automatic \ |
| thermal control circuitry (TCC)."</span>, |
| has_tm, |
| edx_ecx, |
| FeatureInfoFlags::TM |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Pending Break Enable. The processor supports the use of the FERR#/PBE# \ |
| pin when the processor is in the stop-clock state (STPCLK# is asserted) \ |
| to signal the processor that an interrupt is pending and that the \ |
| processor should return to normal operation to handle the interrupt. Bit \ |
| 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability."</span>, |
| has_pbe, |
| edx_ecx, |
| FeatureInfoFlags::PBE |
| ); |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>FeatureInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"FeatureInfo"</span>) |
| .field(<span class="string">"extended_family_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.extended_family_id()) |
| .field(<span class="string">"extended_model_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.extended_model_id()) |
| .field(<span class="string">"family_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.family_id()) |
| .field(<span class="string">"model_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.model_id()) |
| .field(<span class="string">"stepping_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.stepping_id()) |
| .field(<span class="string">"brand_index"</span>, <span class="kw-2">&</span><span class="self">self</span>.brand_index()) |
| .field(<span class="string">"cflush_cache_line_size"</span>, <span class="kw-2">&</span><span class="self">self</span>.cflush_cache_line_size()) |
| .field(<span class="string">"initial_local_apic_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.initial_local_apic_id()) |
| .field( |
| <span class="string">"max_logical_processor_ids"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.max_logical_processor_ids(), |
| ) |
| .field(<span class="string">"edx_ecx"</span>, <span class="kw-2">&</span><span class="self">self</span>.edx_ecx) |
| .finish() |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>FeatureInfoFlags: u64 { |
| |
| <span class="comment">// ECX flags |
| |
| </span><span class="doccomment">/// Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology. |
| </span><span class="kw">const </span>SSE3 = <span class="number">1 </span><< <span class="number">0</span>; |
| <span class="doccomment">/// PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction |
| </span><span class="kw">const </span>PCLMULQDQ = <span class="number">1 </span><< <span class="number">1</span>; |
| <span class="doccomment">/// 64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout |
| </span><span class="kw">const </span>DTES64 = <span class="number">1 </span><< <span class="number">2</span>; |
| <span class="doccomment">/// MONITOR/MWAIT. A value of 1 indicates the processor supports this feature. |
| </span><span class="kw">const </span>MONITOR = <span class="number">1 </span><< <span class="number">3</span>; |
| <span class="doccomment">/// CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL. |
| </span><span class="kw">const </span>DSCPL = <span class="number">1 </span><< <span class="number">4</span>; |
| <span class="doccomment">/// Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology. |
| </span><span class="kw">const </span>VMX = <span class="number">1 </span><< <span class="number">5</span>; |
| <span class="doccomment">/// Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See Chapter 5, Safer Mode Extensions Reference. |
| </span><span class="kw">const </span>SMX = <span class="number">1 </span><< <span class="number">6</span>; |
| <span class="doccomment">/// Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this technology. |
| </span><span class="kw">const </span>EIST = <span class="number">1 </span><< <span class="number">7</span>; |
| <span class="doccomment">/// Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology. |
| </span><span class="kw">const </span>TM2 = <span class="number">1 </span><< <span class="number">8</span>; |
| <span class="doccomment">/// A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor |
| </span><span class="kw">const </span>SSSE3 = <span class="number">1 </span><< <span class="number">9</span>; |
| <span class="doccomment">/// L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details. |
| </span><span class="kw">const </span>CNXTID = <span class="number">1 </span><< <span class="number">10</span>; |
| <span class="doccomment">/// A value of 1 indicates the processor supports FMA extensions using YMM state. |
| </span><span class="kw">const </span>FMA = <span class="number">1 </span><< <span class="number">12</span>; |
| <span class="doccomment">/// CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes section. 14 |
| </span><span class="kw">const </span>CMPXCHG16B = <span class="number">1 </span><< <span class="number">13</span>; |
| <span class="doccomment">/// Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES. |
| </span><span class="kw">const </span>PDCM = <span class="number">1 </span><< <span class="number">15</span>; |
| <span class="doccomment">/// Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and the software may set CR4.PCIDE to 1. |
| </span><span class="kw">const </span>PCID = <span class="number">1 </span><< <span class="number">17</span>; |
| <span class="doccomment">/// A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device. |
| </span><span class="kw">const </span>DCA = <span class="number">1 </span><< <span class="number">18</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports SSE4.1. |
| </span><span class="kw">const </span>SSE41 = <span class="number">1 </span><< <span class="number">19</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports SSE4.2. |
| </span><span class="kw">const </span>SSE42 = <span class="number">1 </span><< <span class="number">20</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports x2APIC feature. |
| </span><span class="kw">const </span>X2APIC = <span class="number">1 </span><< <span class="number">21</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports MOVBE instruction. |
| </span><span class="kw">const </span>MOVBE = <span class="number">1 </span><< <span class="number">22</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports the POPCNT instruction. |
| </span><span class="kw">const </span>POPCNT = <span class="number">1 </span><< <span class="number">23</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processors local APIC timer supports one-shot operation using a TSC deadline value. |
| </span><span class="kw">const </span>TSC_DEADLINE = <span class="number">1 </span><< <span class="number">24</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports the AESNI instruction extensions. |
| </span><span class="kw">const </span>AESNI = <span class="number">1 </span><< <span class="number">25</span>; |
| <span class="doccomment">/// A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0. |
| </span><span class="kw">const </span>XSAVE = <span class="number">1 </span><< <span class="number">26</span>; |
| <span class="doccomment">/// A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions to access XCR0, and support for processor extended state management using XSAVE/XRSTOR. |
| </span><span class="kw">const </span>OSXSAVE = <span class="number">1 </span><< <span class="number">27</span>; |
| <span class="doccomment">/// A value of 1 indicates the processor supports the AVX instruction extensions. |
| </span><span class="kw">const </span>AVX = <span class="number">1 </span><< <span class="number">28</span>; |
| <span class="doccomment">/// A value of 1 indicates that processor supports 16-bit floating-point conversion instructions. |
| </span><span class="kw">const </span>F16C = <span class="number">1 </span><< <span class="number">29</span>; |
| <span class="doccomment">/// A value of 1 indicates that processor supports RDRAND instruction. |
| </span><span class="kw">const </span>RDRAND = <span class="number">1 </span><< <span class="number">30</span>; |
| <span class="doccomment">/// A value of 1 indicates the indicates the presence of a hypervisor. |
| </span><span class="kw">const </span>HYPERVISOR = <span class="number">1 </span><< <span class="number">31</span>; |
| |
| |
| <span class="comment">// EDX flags |
| |
| </span><span class="doccomment">/// Floating Point Unit On-Chip. The processor contains an x87 FPU. |
| </span><span class="kw">const </span>FPU = <span class="number">1 </span><< <span class="number">32</span>; |
| <span class="doccomment">/// Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags. |
| </span><span class="kw">const </span>VME = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">1</span>); |
| <span class="doccomment">/// Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5. |
| </span><span class="kw">const </span>DE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">2</span>); |
| <span class="doccomment">/// Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs. |
| </span><span class="kw">const </span>PSE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">3</span>); |
| <span class="doccomment">/// Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege. |
| </span><span class="kw">const </span>TSC = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">4</span>); |
| <span class="doccomment">/// Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent. |
| </span><span class="kw">const </span>MSR = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">5</span>); |
| <span class="doccomment">/// Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1. |
| </span><span class="kw">const </span>PAE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">6</span>); |
| <span class="doccomment">/// Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature. |
| </span><span class="kw">const </span>MCE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">7</span>); |
| <span class="doccomment">/// CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly locked and atomic). |
| </span><span class="kw">const </span>CX8 = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">8</span>); |
| <span class="doccomment">/// APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated). |
| </span><span class="kw">const </span>APIC = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">9</span>); |
| <span class="doccomment">/// SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported. |
| </span><span class="kw">const </span>SEP = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">11</span>); |
| <span class="doccomment">/// Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported. |
| </span><span class="kw">const </span>MTRR = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">12</span>); |
| <span class="doccomment">/// Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature. |
| </span><span class="kw">const </span>PGE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">13</span>); |
| <span class="doccomment">/// Machine Check Architecture. The Machine Check exArchitecture, which provides a compatible mechanism for error reporting in P6 family, Pentium 4, Intel Xeon processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported. |
| </span><span class="kw">const </span>MCA = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">14</span>); |
| <span class="doccomment">/// Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported |
| </span><span class="kw">const </span>CMOV = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">15</span>); |
| <span class="doccomment">/// Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity. |
| </span><span class="kw">const </span>PAT = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">16</span>); |
| <span class="doccomment">/// 36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size. |
| </span><span class="kw">const </span>PSE36 = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">17</span>); |
| <span class="doccomment">/// Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled. |
| </span><span class="kw">const </span>PSN = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">18</span>); |
| <span class="doccomment">/// CLFLUSH Instruction. CLFLUSH Instruction is supported. |
| </span><span class="kw">const </span>CLFSH = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">19</span>); |
| <span class="doccomment">/// Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see Chapter 23, Introduction to Virtual-Machine Extensions, in the Intel® 64 and IA-32 Architectures Software Developers Manual, Volume 3C). |
| </span><span class="kw">const </span>DS = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">21</span>); |
| <span class="doccomment">/// Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control. |
| </span><span class="kw">const </span>ACPI = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">22</span>); |
| <span class="doccomment">/// Intel MMX Technology. The processor supports the Intel MMX technology. |
| </span><span class="kw">const </span>MMX = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">23</span>); |
| <span class="doccomment">/// FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions. |
| </span><span class="kw">const </span>FXSR = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">24</span>); |
| <span class="doccomment">/// SSE. The processor supports the SSE extensions. |
| </span><span class="kw">const </span>SSE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">25</span>); |
| <span class="doccomment">/// SSE2. The processor supports the SSE2 extensions. |
| </span><span class="kw">const </span>SSE2 = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">26</span>); |
| <span class="doccomment">/// Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. |
| </span><span class="kw">const </span>SS = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">27</span>); |
| <span class="doccomment">/// Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package. |
| </span><span class="kw">const </span>HTT = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">28</span>); |
| <span class="doccomment">/// Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC). |
| </span><span class="kw">const </span>TM = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">29</span>); |
| <span class="doccomment">/// Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. |
| </span><span class="kw">const </span>PBE = <span class="number">1 </span><< (<span class="number">32 </span>+ <span class="number">31</span>); |
| } |
| } |
| |
| <span class="doccomment">/// Iterator over caches (LEAF=0x04). |
| /// |
| /// Yields a [CacheParameter] for each cache. |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="attribute">#[derive(Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>CacheParametersIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| leaf: u32, |
| current: u32, |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>CacheParametersIter { |
| <span class="kw">type </span>Item = CacheParameter; |
| |
| <span class="doccomment">/// Iterate over all cache info subleafs for this CPU. |
| /// |
| /// # Note |
| /// cpuid is called every-time we advance the iterator to get information |
| /// about the next cache. |
| </span><span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><CacheParameter> { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(<span class="self">self</span>.leaf, <span class="self">self</span>.current); |
| <span class="kw">let </span>cp = CacheParameter { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }; |
| |
| <span class="kw">match </span>cp.cache_type() { |
| CacheType::Null => <span class="prelude-val">None</span>, |
| CacheType::Reserved => <span class="prelude-val">None</span>, |
| <span class="kw">_ </span>=> { |
| <span class="self">self</span>.current += <span class="number">1</span>; |
| <span class="prelude-val">Some</span>(cp) |
| } |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CacheParametersIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="doccomment">/// Information about an individual cache in the hierarchy. |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="attribute">#[derive(Copy, Clone, Eq, PartialEq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>CacheParameter { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="doccomment">/// Info about a what a given cache caches (instructions, data, etc.) |
| </span><span class="attribute">#[derive(PartialEq, Eq, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>CacheType { |
| <span class="doccomment">/// Null - No more caches |
| </span>Null = <span class="number">0</span>, |
| <span class="doccomment">/// Data cache |
| </span>Data, |
| <span class="doccomment">/// Instruction cache |
| </span>Instruction, |
| <span class="doccomment">/// Data and Instruction cache |
| </span>Unified, |
| <span class="doccomment">/// 4-31 = Reserved |
| </span>Reserved, |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>CacheType { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="kw">let </span>typ = <span class="kw">match </span><span class="self">self </span>{ |
| CacheType::Null => <span class="string">"Null"</span>, |
| CacheType::Data => <span class="string">"Data"</span>, |
| CacheType::Instruction => <span class="string">"Instruction"</span>, |
| CacheType::Unified => <span class="string">"Unified"</span>, |
| CacheType::Reserved => <span class="string">"Reserved"</span>, |
| }; |
| |
| f.write_str(typ) |
| } |
| } |
| |
| <span class="kw">impl </span>CacheParameter { |
| <span class="doccomment">/// Cache Type |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>cache_type(<span class="kw-2">&</span><span class="self">self</span>) -> CacheType { |
| <span class="kw">let </span>typ = get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">4</span>) <span class="kw">as </span>u8; |
| <span class="kw">match </span>typ { |
| <span class="number">0 </span>=> CacheType::Null, |
| <span class="number">1 </span>=> CacheType::Data, |
| <span class="number">2 </span>=> CacheType::Instruction, |
| <span class="number">3 </span>=> CacheType::Unified, |
| <span class="kw">_ </span>=> CacheType::Reserved, |
| } |
| } |
| |
| <span class="doccomment">/// Cache Level (starts at 1) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>level(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">5</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Self Initializing cache level (does not need SW initialization). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>is_self_initializing(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.eax, <span class="number">8</span>, <span class="number">8</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Fully Associative cache |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>is_fully_associative(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.eax, <span class="number">9</span>, <span class="number">9</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Maximum number of addressable IDs for logical processors sharing this cache |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>max_cores_for_cache(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (get_bits(<span class="self">self</span>.eax, <span class="number">14</span>, <span class="number">25</span>) + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// Maximum number of addressable IDs for processor cores in the physical package |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>max_cores_for_package(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (get_bits(<span class="self">self</span>.eax, <span class="number">26</span>, <span class="number">31</span>) + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// System Coherency Line Size (Bits 11-00) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>coherency_line_size(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">11</span>) + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// Physical Line partitions (Bits 21-12) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>physical_line_partitions(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (get_bits(<span class="self">self</span>.ebx, <span class="number">12</span>, <span class="number">21</span>) + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// Ways of associativity (Bits 31-22) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>associativity(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (get_bits(<span class="self">self</span>.ebx, <span class="number">22</span>, <span class="number">31</span>) + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// Number of Sets (Bits 31-00) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>sets(<span class="kw-2">&</span><span class="self">self</span>) -> usize { |
| (<span class="self">self</span>.ecx + <span class="number">1</span>) <span class="kw">as </span>usize |
| } |
| |
| <span class="doccomment">/// Write-Back Invalidate/Invalidate (Bit 0) |
| /// False: WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. |
| /// True: WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>is_write_back_invalidate(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">0</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Cache Inclusiveness (Bit 1) |
| /// False: Cache is not inclusive of lower cache levels. |
| /// True: Cache is inclusive of lower cache levels. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>is_inclusive(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.edx, <span class="number">1</span>, <span class="number">1</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Complex Cache Indexing (Bit 2) |
| /// False: Direct mapped cache. |
| /// True: A complex function is used to index the cache, potentially using all address bits. |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>has_complex_indexing(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.edx, <span class="number">2</span>, <span class="number">2</span>) == <span class="number">1 |
| </span>} |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>CacheParameter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"CacheParameter"</span>) |
| .field(<span class="string">"cache_type"</span>, <span class="kw-2">&</span><span class="self">self</span>.cache_type()) |
| .field(<span class="string">"level"</span>, <span class="kw-2">&</span><span class="self">self</span>.level()) |
| .field(<span class="string">"is_self_initializing"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_self_initializing()) |
| .field(<span class="string">"is_fully_associative"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_fully_associative()) |
| .field(<span class="string">"max_cores_for_cache"</span>, <span class="kw-2">&</span><span class="self">self</span>.max_cores_for_cache()) |
| .field(<span class="string">"max_cores_for_package"</span>, <span class="kw-2">&</span><span class="self">self</span>.max_cores_for_package()) |
| .field(<span class="string">"coherency_line_size"</span>, <span class="kw-2">&</span><span class="self">self</span>.coherency_line_size()) |
| .field(<span class="string">"physical_line_partitions"</span>, <span class="kw-2">&</span><span class="self">self</span>.physical_line_partitions()) |
| .field(<span class="string">"associativity"</span>, <span class="kw-2">&</span><span class="self">self</span>.associativity()) |
| .field(<span class="string">"sets"</span>, <span class="kw-2">&</span><span class="self">self</span>.sets()) |
| .field(<span class="string">"is_write_back_invalidate"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_write_back_invalidate()) |
| .field(<span class="string">"is_inclusive"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_inclusive()) |
| .field(<span class="string">"has_complex_indexing"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_complex_indexing()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Information about how monitor/mwait works on this CPU (LEAF=0x05). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="attribute">#[derive(Eq, PartialEq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>MonitorMwaitInfo { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>MonitorMwaitInfo { |
| <span class="doccomment">/// Smallest monitor-line size in bytes (default is processor's monitor granularity) |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>smallest_monitor_line(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Largest monitor-line size in bytes (default is processor's monitor granularity |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>largest_monitor_line(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>extensions_supported(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.ecx, <span class="number">0</span>, <span class="number">0</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Supports treating interrupts as break-event for MWAIT, even when interrupts disabled |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>interrupts_as_break_event(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| get_bits(<span class="self">self</span>.ecx, <span class="number">1</span>, <span class="number">1</span>) == <span class="number">1 |
| </span>} |
| |
| <span class="doccomment">/// Number of C0 sub C-states supported using MWAIT (Bits 03 - 00) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c0_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">3</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C1 sub C-states supported using MWAIT (Bits 07 - 04) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c1_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">4</span>, <span class="number">7</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C2 sub C-states supported using MWAIT (Bits 11 - 08) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c2_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">8</span>, <span class="number">11</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C3 sub C-states supported using MWAIT (Bits 15 - 12) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c3_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">12</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C4 sub C-states supported using MWAIT (Bits 19 - 16) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c4_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">16</span>, <span class="number">19</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C5 sub C-states supported using MWAIT (Bits 23 - 20) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c5_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">20</span>, <span class="number">23</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C6 sub C-states supported using MWAIT (Bits 27 - 24) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c6_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">24</span>, <span class="number">27</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of C7 sub C-states supported using MWAIT (Bits 31 - 28) |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>supported_c7_states(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">28</span>, <span class="number">31</span>) <span class="kw">as </span>u16 |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>MonitorMwaitInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"MonitorMwaitInfo"</span>) |
| .field(<span class="string">"smallest_monitor_line"</span>, <span class="kw-2">&</span><span class="self">self</span>.smallest_monitor_line()) |
| .field(<span class="string">"largest_monitor_line"</span>, <span class="kw-2">&</span><span class="self">self</span>.largest_monitor_line()) |
| .field(<span class="string">"extensions_supported"</span>, <span class="kw-2">&</span><span class="self">self</span>.extensions_supported()) |
| .field( |
| <span class="string">"interrupts_as_break_event"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.interrupts_as_break_event(), |
| ) |
| .field(<span class="string">"supported_c0_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c0_states()) |
| .field(<span class="string">"supported_c1_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c1_states()) |
| .field(<span class="string">"supported_c2_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c2_states()) |
| .field(<span class="string">"supported_c3_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c3_states()) |
| .field(<span class="string">"supported_c4_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c4_states()) |
| .field(<span class="string">"supported_c5_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c5_states()) |
| .field(<span class="string">"supported_c6_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c6_states()) |
| .field(<span class="string">"supported_c7_states"</span>, <span class="kw-2">&</span><span class="self">self</span>.supported_c7_states()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Query information about thermal and power management features of the CPU (LEAF=0x06). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ThermalPowerInfo { |
| eax: ThermalPowerFeaturesEax, |
| ebx: u32, |
| ecx: ThermalPowerFeaturesEcx, |
| _edx: u32, |
| } |
| |
| <span class="kw">impl </span>ThermalPowerInfo { |
| <span class="doccomment">/// Number of Interrupt Thresholds in Digital Thermal Sensor |
| /// |
| /// # Platforms |
| /// ❌ AMD (undefined/reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>dts_irq_threshold(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">3</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Digital temperature sensor is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_dts(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::DTS) |
| } |
| |
| <span class="doccomment">/// Intel Turbo Boost Technology Available (see description of |
| /// IA32_MISC_ENABLE\[38\]). |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_turbo_boost(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::TURBO_BOOST) |
| } |
| |
| <span class="doccomment">/// ARAT. APIC-Timer-always-running feature is supported if set. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>has_arat(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::ARAT) |
| } |
| |
| <span class="doccomment">/// PLN. Power limit notification controls are supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_pln(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::PLN) |
| } |
| |
| <span class="doccomment">/// ECMD. Clock modulation duty cycle extension is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_ecmd(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::ECMD) |
| } |
| |
| <span class="doccomment">/// PTM. Package thermal management is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_ptm(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::PTM) |
| } |
| |
| <span class="doccomment">/// HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, |
| /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::HWP) |
| } |
| |
| <span class="doccomment">/// HWP Notification. IA32_HWP_INTERRUPT MSR is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_notification(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::HWP_NOTIFICATION) |
| } |
| |
| <span class="doccomment">/// HWP Activity Window. IA32_HWP_REQUEST[bits 41:32] is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_activity_window(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::HWP_ACTIVITY_WINDOW) |
| } |
| |
| <span class="doccomment">/// HWP Energy Performance Preference. IA32_HWP_REQUEST[bits 31:24] is |
| /// supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_energy_performance_preference(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::HWP_ENERGY_PERFORMANCE_PREFERENCE) |
| } |
| |
| <span class="doccomment">/// HWP Package Level Request. IA32_HWP_REQUEST_PKG MSR is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_package_level_request(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::HWP_PACKAGE_LEVEL_REQUEST) |
| } |
| |
| <span class="doccomment">/// HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, |
| /// IA32_THREAD_STALL MSRs are supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hdc(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::HDC) |
| } |
| |
| <span class="doccomment">/// Intel® Turbo Boost Max Technology 3.0 available. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_turbo_boost3(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::TURBO_BOOST_3) |
| } |
| |
| <span class="doccomment">/// HWP Capabilities. Highest Performance change is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_capabilities(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::HWP_CAPABILITIES) |
| } |
| |
| <span class="doccomment">/// HWP PECI override is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_peci_override(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::HWP_PECI_OVERRIDE) |
| } |
| |
| <span class="doccomment">/// Flexible HWP is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_flexible_hwp(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax.contains(ThermalPowerFeaturesEax::FLEXIBLE_HWP) |
| } |
| |
| <span class="doccomment">/// Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_hwp_fast_access_mode(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::HWP_REQUEST_MSR_FAST_ACCESS) |
| } |
| |
| <span class="doccomment">/// Ignoring Idle Logical Processor HWP request is supported if set. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_ignore_idle_processor_hwp_request(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax |
| .contains(ThermalPowerFeaturesEax::IGNORE_IDLE_PROCESSOR_HWP_REQUEST) |
| } |
| |
| <span class="doccomment">/// Hardware Coordination Feedback Capability |
| /// |
| /// Presence of IA32_MPERF and IA32_APERF. |
| /// |
| /// The capability to provide a measure of delivered processor performance |
| /// (since last reset of the counters), as a percentage of expected |
| /// processor performance at frequency specified in CPUID Brand String Bits |
| /// 02 - 01 |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="kw">pub fn </span>has_hw_coord_feedback(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx |
| .contains(ThermalPowerFeaturesEcx::HW_COORD_FEEDBACK) |
| } |
| |
| <span class="doccomment">/// The processor supports performance-energy bias preference if |
| /// CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a |
| /// new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H) |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="kw">pub fn </span>has_energy_bias_pref(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ThermalPowerFeaturesEcx::ENERGY_BIAS_PREF) |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ThermalPowerInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"ThermalPowerInfo"</span>) |
| .field(<span class="string">"dts_irq_threshold"</span>, <span class="kw-2">&</span><span class="self">self</span>.dts_irq_threshold()) |
| .field(<span class="string">"has_dts"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_dts()) |
| .field(<span class="string">"has_arat"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_arat()) |
| .field(<span class="string">"has_pln"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_pln()) |
| .field(<span class="string">"has_ecmd"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_ecmd()) |
| .field(<span class="string">"has_ptm"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_ptm()) |
| .field(<span class="string">"has_hwp"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp()) |
| .field(<span class="string">"has_hwp_notification"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp_notification()) |
| .field(<span class="string">"has_hwp_activity_window"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp_activity_window()) |
| .field( |
| <span class="string">"has_hwp_energy_performance_preference"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_hwp_energy_performance_preference(), |
| ) |
| .field( |
| <span class="string">"has_hwp_package_level_request"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_hwp_package_level_request(), |
| ) |
| .field(<span class="string">"has_hdc"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hdc()) |
| .field(<span class="string">"has_turbo_boost3"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_turbo_boost3()) |
| .field(<span class="string">"has_hwp_capabilities"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp_capabilities()) |
| .field(<span class="string">"has_hwp_peci_override"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp_peci_override()) |
| .field(<span class="string">"has_flexible_hwp"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_flexible_hwp()) |
| .field(<span class="string">"has_hwp_fast_access_mode"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hwp_fast_access_mode()) |
| .field( |
| <span class="string">"has_ignore_idle_processor_hwp_request"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_ignore_idle_processor_hwp_request(), |
| ) |
| .field(<span class="string">"has_hw_coord_feedback"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_hw_coord_feedback()) |
| .field(<span class="string">"has_energy_bias_pref"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_energy_bias_pref()) |
| .finish() |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ThermalPowerFeaturesEax: u32 { |
| <span class="doccomment">/// Digital temperature sensor is supported if set. (Bit 00) |
| </span><span class="kw">const </span>DTS = <span class="number">1 </span><< <span class="number">0</span>; |
| <span class="doccomment">/// Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]). (Bit 01) |
| </span><span class="kw">const </span>TURBO_BOOST = <span class="number">1 </span><< <span class="number">1</span>; |
| <span class="doccomment">/// ARAT. APIC-Timer-always-running feature is supported if set. (Bit 02) |
| </span><span class="kw">const </span>ARAT = <span class="number">1 </span><< <span class="number">2</span>; |
| <span class="doccomment">/// Bit 3: Reserved. |
| </span><span class="kw">const </span>RESERVED_3 = <span class="number">1 </span><< <span class="number">3</span>; |
| <span class="doccomment">/// PLN. Power limit notification controls are supported if set. (Bit 04) |
| </span><span class="kw">const </span>PLN = <span class="number">1 </span><< <span class="number">4</span>; |
| <span class="doccomment">/// ECMD. Clock modulation duty cycle extension is supported if set. (Bit 05) |
| </span><span class="kw">const </span>ECMD = <span class="number">1 </span><< <span class="number">5</span>; |
| <span class="doccomment">/// PTM. Package thermal management is supported if set. (Bit 06) |
| </span><span class="kw">const </span>PTM = <span class="number">1 </span><< <span class="number">6</span>; |
| <span class="doccomment">/// Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. |
| </span><span class="kw">const </span>HWP = <span class="number">1 </span><< <span class="number">7</span>; |
| <span class="doccomment">/// Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set. |
| </span><span class="kw">const </span>HWP_NOTIFICATION = <span class="number">1 </span><< <span class="number">8</span>; |
| <span class="doccomment">/// Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set. |
| </span><span class="kw">const </span>HWP_ACTIVITY_WINDOW = <span class="number">1 </span><< <span class="number">9</span>; |
| <span class="doccomment">/// Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set. |
| </span><span class="kw">const </span>HWP_ENERGY_PERFORMANCE_PREFERENCE = <span class="number">1 </span><< <span class="number">10</span>; |
| <span class="doccomment">/// Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set. |
| </span><span class="kw">const </span>HWP_PACKAGE_LEVEL_REQUEST = <span class="number">1 </span><< <span class="number">11</span>; |
| <span class="doccomment">/// Bit 12: Reserved. |
| </span><span class="kw">const </span>RESERVED_12 = <span class="number">1 </span><< <span class="number">12</span>; |
| <span class="doccomment">/// Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set. |
| </span><span class="kw">const </span>HDC = <span class="number">1 </span><< <span class="number">13</span>; |
| <span class="doccomment">/// Bit 14: Intel® Turbo Boost Max Technology 3.0 available. |
| </span><span class="kw">const </span>TURBO_BOOST_3 = <span class="number">1 </span><< <span class="number">14</span>; |
| <span class="doccomment">/// Bit 15: HWP Capabilities. Highest Performance change is supported if set. |
| </span><span class="kw">const </span>HWP_CAPABILITIES = <span class="number">1 </span><< <span class="number">15</span>; |
| <span class="doccomment">/// Bit 16: HWP PECI override is supported if set. |
| </span><span class="kw">const </span>HWP_PECI_OVERRIDE = <span class="number">1 </span><< <span class="number">16</span>; |
| <span class="doccomment">/// Bit 17: Flexible HWP is supported if set. |
| </span><span class="kw">const </span>FLEXIBLE_HWP = <span class="number">1 </span><< <span class="number">17</span>; |
| <span class="doccomment">/// Bit 18: Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. |
| </span><span class="kw">const </span>HWP_REQUEST_MSR_FAST_ACCESS = <span class="number">1 </span><< <span class="number">18</span>; |
| <span class="doccomment">/// Bit 19: Reserved. |
| </span><span class="kw">const </span>RESERVED_19 = <span class="number">1 </span><< <span class="number">19</span>; |
| <span class="doccomment">/// Bit 20: Ignoring Idle Logical Processor HWP request is supported if set. |
| </span><span class="kw">const </span>IGNORE_IDLE_PROCESSOR_HWP_REQUEST = <span class="number">1 </span><< <span class="number">20</span>; |
| <span class="comment">// Bits 31 - 21: Reserved |
| </span>} |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ThermalPowerFeaturesEcx: u32 { |
| <span class="kw">const </span>HW_COORD_FEEDBACK = <span class="number">1 </span><< <span class="number">0</span>; |
| |
| <span class="doccomment">/// The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H) |
| </span><span class="kw">const </span>ENERGY_BIAS_PREF = <span class="number">1 </span><< <span class="number">3</span>; |
| } |
| } |
| |
| <span class="doccomment">/// Structured Extended Feature Identifiers (LEAF=0x07). |
| /// |
| /// # Platforms |
| /// 🟡 AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedFeatures { |
| _eax: u32, |
| ebx: ExtendedFeaturesEbx, |
| ecx: ExtendedFeaturesEcx, |
| _edx: u32, |
| } |
| |
| <span class="kw">impl </span>ExtendedFeatures { |
| <span class="doccomment">/// FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_fsgsbase(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::FSGSBASE) |
| } |
| |
| <span class="doccomment">/// IA32_TSC_ADJUST MSR is supported if 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_tsc_adjust_msr(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::ADJUST_MSR) |
| } |
| |
| <span class="doccomment">/// BMI1 |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_bmi1(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::BMI1) |
| } |
| |
| <span class="doccomment">/// HLE |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_hle(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::HLE) |
| } |
| |
| <span class="doccomment">/// AVX2 |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx2(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX2) |
| } |
| |
| <span class="doccomment">/// FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if |
| /// 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_fdp(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::FDP) |
| } |
| |
| <span class="doccomment">/// SMEP. Supports Supervisor-Mode Execution Prevention if 1. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_smep(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::SMEP) |
| } |
| |
| <span class="doccomment">/// BMI2 |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_bmi2(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::BMI2) |
| } |
| |
| <span class="doccomment">/// Supports Enhanced REP MOVSB/STOSB if 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rep_movsb_stosb(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::REP_MOVSB_STOSB) |
| } |
| |
| <span class="doccomment">/// INVPCID. If 1, supports INVPCID instruction for system software that |
| /// manages process-context identifiers. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_invpcid(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::INVPCID) |
| } |
| |
| <span class="doccomment">/// RTM |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rtm(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::RTM) |
| } |
| |
| <span class="doccomment">/// Supports Intel Resource Director Technology (RDT) Monitoring capability. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rdtm(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::RDTM) |
| } |
| |
| <span class="doccomment">/// Deprecates FPU CS and FPU DS values if 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_fpu_cs_ds_deprecated(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::DEPRECATE_FPU_CS_DS) |
| } |
| |
| <span class="doccomment">/// MPX. Supports Intel Memory Protection Extensions if 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_mpx(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::MPX) |
| } |
| |
| <span class="doccomment">/// Supports Intel Resource Director Technology (RDT) Allocation capability. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rdta(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::RDTA) |
| } |
| |
| <span class="doccomment">/// Supports RDSEED. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rdseed(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::RDSEED) |
| } |
| |
| <span class="doccomment">/// Supports ADX. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_adx(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::ADX) |
| } |
| |
| <span class="doccomment">/// SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC |
| /// instructions) if 1. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_smap(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::SMAP) |
| } |
| |
| <span class="doccomment">/// Supports CLFLUSHOPT. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_clflushopt(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::CLFLUSHOPT) |
| } |
| |
| <span class="doccomment">/// Supports Intel Processor Trace. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_processor_trace(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::PROCESSOR_TRACE) |
| } |
| |
| <span class="doccomment">/// Supports SHA Instructions. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_sha(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::SHA) |
| } |
| |
| <span class="doccomment">/// Supports Intel® Software Guard Extensions (Intel® SGX Extensions). |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_sgx(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::SGX) |
| } |
| |
| <span class="doccomment">/// Supports AVX512F. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512f(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512F) |
| } |
| |
| <span class="doccomment">/// Supports AVX512DQ. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512dq(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512DQ) |
| } |
| |
| <span class="doccomment">/// AVX512_IFMA |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512_ifma(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512_IFMA) |
| } |
| |
| <span class="doccomment">/// AVX512PF |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512pf(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512PF) |
| } |
| |
| <span class="doccomment">/// AVX512ER |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512er(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512ER) |
| } |
| |
| <span class="doccomment">/// AVX512CD |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512cd(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512CD) |
| } |
| |
| <span class="doccomment">/// AVX512BW |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512bw(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512BW) |
| } |
| |
| <span class="doccomment">/// AVX512VL |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512vl(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::AVX512VL) |
| } |
| |
| <span class="doccomment">/// CLWB |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_clwb(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ebx.contains(ExtendedFeaturesEbx::CLWB) |
| } |
| |
| <span class="doccomment">/// Has PREFETCHWT1 (Intel® Xeon Phi™ only). |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_prefetchwt1(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::PREFETCHWT1) |
| } |
| |
| <span class="doccomment">/// Supports user-mode instruction prevention if 1. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_umip(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::UMIP) |
| } |
| |
| <span class="doccomment">/// Supports protection keys for user-mode pages. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_pku(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::PKU) |
| } |
| |
| <span class="doccomment">/// OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU |
| /// instructions. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_ospke(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::OSPKE) |
| } |
| |
| <span class="doccomment">/// WAITPKG |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_waitpkg(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::WAITPKG) |
| } |
| |
| <span class="doccomment">/// AVX512VBMI2 |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_av512vbmi2(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::AVX512VBMI2) |
| } |
| |
| <span class="doccomment">/// Supports CET shadow stack features. Processors that set this bit define bits 0..2 of the |
| /// IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs: |
| /// IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and IA32_PL0_SSP. |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_cet_ss(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::GFNI) |
| } |
| |
| <span class="doccomment">/// GFNI |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_gfni(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::GFNI) |
| } |
| |
| <span class="doccomment">/// VAES |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_vaes(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::VAES) |
| } |
| |
| <span class="doccomment">/// VPCLMULQDQ |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_vpclmulqdq(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::VPCLMULQDQ) |
| } |
| |
| <span class="doccomment">/// AVX512VNNI |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512vnni(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::AVX512VNNI) |
| } |
| |
| <span class="doccomment">/// AVX512BITALG |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512bitalg(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::AVX512BITALG) |
| } |
| |
| <span class="doccomment">/// Indicates the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, |
| /// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_tme_en(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::TMEEN) |
| } |
| |
| <span class="doccomment">/// AVX512VPOPCNTDQ |
| /// |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_avx512vpopcntdq(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::AVX512VPOPCNTDQ) |
| } |
| |
| <span class="doccomment">/// Supports 57-bit linear addresses and five-level paging if 1. |
| /// |
| /// # Platforms |
| /// ❓ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_la57(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::LA57) |
| } |
| |
| <span class="doccomment">/// RDPID and IA32_TSC_AUX are available. |
| /// |
| /// # Bug |
| /// The Intel manual lists RDPID as bit 22 in the ECX register, but AMD |
| /// lists it as bit 22 in the ebx register. We assumed that the AMD manual |
| /// was wrong and query ecx, let's see what happens. |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_rdpid(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::RDPID) |
| } |
| |
| <span class="doccomment">/// Supports SGX Launch Configuration. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub const fn </span>has_sgx_lc(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx.contains(ExtendedFeaturesEcx::SGX_LC) |
| } |
| |
| <span class="doccomment">/// The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[inline] |
| </span><span class="kw">pub fn </span>mawau_value(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ecx.bits(), <span class="number">17</span>, <span class="number">21</span>) <span class="kw">as </span>u8 |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ExtendedFeatures { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"ExtendedFeatures"</span>) |
| .field(<span class="string">"ebx"</span>, <span class="kw-2">&</span><span class="self">self</span>.ebx) |
| .field(<span class="string">"ecx"</span>, <span class="kw-2">&</span><span class="self">self</span>.ecx) |
| .field(<span class="string">"mawau_value"</span>, <span class="kw-2">&</span><span class="self">self</span>.mawau_value()) |
| .finish() |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ExtendedFeaturesEbx: u32 { |
| <span class="doccomment">/// FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. (Bit 00) |
| </span><span class="kw">const </span>FSGSBASE = <span class="number">1 </span><< <span class="number">0</span>; |
| <span class="doccomment">/// IA32_TSC_ADJUST MSR is supported if 1. (Bit 01) |
| </span><span class="kw">const </span>ADJUST_MSR = <span class="number">1 </span><< <span class="number">1</span>; |
| <span class="doccomment">/// Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1. |
| </span><span class="kw">const </span>SGX = <span class="number">1 </span><< <span class="number">2</span>; |
| <span class="doccomment">/// BMI1 (Bit 03) |
| </span><span class="kw">const </span>BMI1 = <span class="number">1 </span><< <span class="number">3</span>; |
| <span class="doccomment">/// HLE (Bit 04) |
| </span><span class="kw">const </span>HLE = <span class="number">1 </span><< <span class="number">4</span>; |
| <span class="doccomment">/// AVX2 (Bit 05) |
| </span><span class="kw">const </span>AVX2 = <span class="number">1 </span><< <span class="number">5</span>; |
| <span class="doccomment">/// FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1. |
| </span><span class="kw">const </span>FDP = <span class="number">1 </span><< <span class="number">6</span>; |
| <span class="doccomment">/// SMEP. Supports Supervisor-Mode Execution Prevention if 1. (Bit 07) |
| </span><span class="kw">const </span>SMEP = <span class="number">1 </span><< <span class="number">7</span>; |
| <span class="doccomment">/// BMI2 (Bit 08) |
| </span><span class="kw">const </span>BMI2 = <span class="number">1 </span><< <span class="number">8</span>; |
| <span class="doccomment">/// Supports Enhanced REP MOVSB/STOSB if 1. (Bit 09) |
| </span><span class="kw">const </span>REP_MOVSB_STOSB = <span class="number">1 </span><< <span class="number">9</span>; |
| <span class="doccomment">/// INVPCID. If 1, supports INVPCID instruction for system software that manages process-context identifiers. (Bit 10) |
| </span><span class="kw">const </span>INVPCID = <span class="number">1 </span><< <span class="number">10</span>; |
| <span class="doccomment">/// RTM (Bit 11) |
| </span><span class="kw">const </span>RTM = <span class="number">1 </span><< <span class="number">11</span>; |
| <span class="doccomment">/// Supports Intel Resource Director Technology (RDT) Monitoring. (Bit 12) |
| </span><span class="kw">const </span>RDTM = <span class="number">1 </span><< <span class="number">12</span>; |
| <span class="doccomment">/// Deprecates FPU CS and FPU DS values if 1. (Bit 13) |
| </span><span class="kw">const </span>DEPRECATE_FPU_CS_DS = <span class="number">1 </span><< <span class="number">13</span>; |
| <span class="doccomment">/// Deprecates FPU CS and FPU DS values if 1. (Bit 14) |
| </span><span class="kw">const </span>MPX = <span class="number">1 </span><< <span class="number">14</span>; |
| <span class="doccomment">/// Supports Intel Resource Director Technology (RDT) Allocation capability if 1. |
| </span><span class="kw">const </span>RDTA = <span class="number">1 </span><< <span class="number">15</span>; |
| <span class="doccomment">/// Bit 16: AVX512F. |
| </span><span class="kw">const </span>AVX512F = <span class="number">1 </span><< <span class="number">16</span>; |
| <span class="doccomment">/// Bit 17: AVX512DQ. |
| </span><span class="kw">const </span>AVX512DQ = <span class="number">1 </span><< <span class="number">17</span>; |
| <span class="doccomment">/// Supports RDSEED. |
| </span><span class="kw">const </span>RDSEED = <span class="number">1 </span><< <span class="number">18</span>; |
| <span class="doccomment">/// Supports ADX. |
| </span><span class="kw">const </span>ADX = <span class="number">1 </span><< <span class="number">19</span>; |
| <span class="doccomment">/// SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1. |
| </span><span class="kw">const </span>SMAP = <span class="number">1 </span><< <span class="number">20</span>; |
| <span class="doccomment">/// Bit 21: AVX512_IFMA. |
| </span><span class="kw">const </span>AVX512_IFMA = <span class="number">1 </span><< <span class="number">21</span>; |
| <span class="comment">// Bit 22: Reserved. |
| </span><span class="doccomment">/// Bit 23: CLFLUSHOPT |
| </span><span class="kw">const </span>CLFLUSHOPT = <span class="number">1 </span><< <span class="number">23</span>; |
| <span class="doccomment">/// Bit 24: CLWB. |
| </span><span class="kw">const </span>CLWB = <span class="number">1 </span><< <span class="number">24</span>; |
| <span class="doccomment">/// Bit 25: Intel Processor Trace |
| </span><span class="kw">const </span>PROCESSOR_TRACE = <span class="number">1 </span><< <span class="number">25</span>; |
| <span class="doccomment">/// Bit 26: AVX512PF. (Intel® Xeon Phi™ only.) |
| </span><span class="kw">const </span>AVX512PF = <span class="number">1 </span><< <span class="number">26</span>; |
| <span class="doccomment">/// Bit 27: AVX512ER. (Intel® Xeon Phi™ only.) |
| </span><span class="kw">const </span>AVX512ER = <span class="number">1 </span><< <span class="number">27</span>; |
| <span class="doccomment">/// Bit 28: AVX512CD. |
| </span><span class="kw">const </span>AVX512CD = <span class="number">1 </span><< <span class="number">28</span>; |
| <span class="doccomment">/// Bit 29: Intel SHA Extensions |
| </span><span class="kw">const </span>SHA = <span class="number">1 </span><< <span class="number">29</span>; |
| <span class="doccomment">/// Bit 30: AVX512BW. |
| </span><span class="kw">const </span>AVX512BW = <span class="number">1 </span><< <span class="number">30</span>; |
| <span class="doccomment">/// Bit 31: AVX512VL. |
| </span><span class="kw">const </span>AVX512VL = <span class="number">1 </span><< <span class="number">31</span>; |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ExtendedFeaturesEcx: u32 { |
| <span class="doccomment">/// Bit 0: Prefetch WT1. (Intel® Xeon Phi™ only). |
| </span><span class="kw">const </span>PREFETCHWT1 = <span class="number">1 </span><< <span class="number">0</span>; |
| <span class="comment">// Bit 01: AVX512_VBMI |
| </span><span class="kw">const </span>AVX512VBMI = <span class="number">1 </span><< <span class="number">1</span>; |
| <span class="doccomment">/// Bit 02: UMIP. Supports user-mode instruction prevention if 1. |
| </span><span class="kw">const </span>UMIP = <span class="number">1 </span><< <span class="number">2</span>; |
| <span class="doccomment">/// Bit 03: PKU. Supports protection keys for user-mode pages if 1. |
| </span><span class="kw">const </span>PKU = <span class="number">1 </span><< <span class="number">3</span>; |
| <span class="doccomment">/// Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instruc-tions). |
| </span><span class="kw">const </span>OSPKE = <span class="number">1 </span><< <span class="number">4</span>; |
| <span class="doccomment">/// Bit 5: WAITPKG |
| </span><span class="kw">const </span>WAITPKG = <span class="number">1 </span>>> <span class="number">5</span>; |
| <span class="doccomment">/// Bit 6: AV512_VBMI2 |
| </span><span class="kw">const </span>AVX512VBMI2 = <span class="number">1 </span><< <span class="number">6</span>; |
| <span class="doccomment">/// Bit 7: CET_SS. Supports CET shadow stack features if 1. Processors that set this bit define bits 0..2 of the |
| /// IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs: |
| /// IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and IA32_PL0_SSP. |
| </span><span class="kw">const </span>CETSS = <span class="number">1 </span><< <span class="number">7</span>; |
| <span class="doccomment">/// Bit 8: GFNI |
| </span><span class="kw">const </span>GFNI = <span class="number">1 </span><< <span class="number">8</span>; |
| <span class="doccomment">/// Bit 9: VAES |
| </span><span class="kw">const </span>VAES = <span class="number">1 </span><< <span class="number">9</span>; |
| <span class="doccomment">/// Bit 10: VPCLMULQDQ |
| </span><span class="kw">const </span>VPCLMULQDQ = <span class="number">1 </span><< <span class="number">10</span>; |
| <span class="doccomment">/// Bit 11: AVX512_VNNI |
| </span><span class="kw">const </span>AVX512VNNI = <span class="number">1 </span><< <span class="number">11</span>; |
| <span class="doccomment">/// Bit 12: AVX512_BITALG |
| </span><span class="kw">const </span>AVX512BITALG = <span class="number">1 </span><< <span class="number">12</span>; |
| <span class="doccomment">/// Bit 13: TME_EN. If 1, the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, |
| /// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
| </span><span class="kw">const </span>TMEEN = <span class="number">1 </span><< <span class="number">13</span>; |
| <span class="doccomment">/// Bit 14: AVX512_VPOPCNTDQ |
| </span><span class="kw">const </span>AVX512VPOPCNTDQ = <span class="number">1 </span><< <span class="number">14</span>; |
| |
| <span class="comment">// Bit 15: Reserved. |
| |
| </span><span class="doccomment">/// Bit 16: Supports 57-bit linear addresses and five-level paging if 1. |
| </span><span class="kw">const </span>LA57 = <span class="number">1 </span><< <span class="number">16</span>; |
| |
| <span class="comment">// Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode |
| |
| </span><span class="doccomment">/// Bit 22: RDPID. RDPID and IA32_TSC_AUX are available if 1. |
| </span><span class="kw">const </span>RDPID = <span class="number">1 </span><< <span class="number">22</span>; |
| |
| <span class="comment">// Bits 29 - 23: Reserved. |
| |
| </span><span class="doccomment">/// Bit 30: SGX_LC. Supports SGX Launch Configuration if 1. |
| </span><span class="kw">const </span>SGX_LC = <span class="number">1 </span><< <span class="number">30</span>; |
| } |
| } |
| |
| <span class="doccomment">/// Direct cache access info (LEAF=0x09). |
| /// |
| /// # Platforms |
| /// ❌ AMD (reserved) ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>DirectCacheAccessInfo { |
| eax: u32, |
| } |
| |
| <span class="kw">impl </span>DirectCacheAccessInfo { |
| <span class="doccomment">/// Value of bits \[31:0\] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H) |
| </span><span class="kw">pub fn </span>get_dca_cap_value(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.eax |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>DirectCacheAccessInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"DirectCacheAccessInfo"</span>) |
| .field(<span class="string">"dca_cap_value"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_dca_cap_value()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Info about performance monitoring -- how many counters etc. (LEAF=0x0A) |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>PerformanceMonitoringInfo { |
| eax: u32, |
| ebx: PerformanceMonitoringFeaturesEbx, |
| _ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>PerformanceMonitoringInfo { |
| <span class="doccomment">/// Version ID of architectural performance monitoring. (Bits 07 - 00) |
| </span><span class="kw">pub fn </span>version_id(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Number of general-purpose performance monitoring counter per logical processor. (Bits 15- 08) |
| </span><span class="kw">pub fn </span>number_of_counters(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">8</span>, <span class="number">15</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Bit width of general-purpose, performance monitoring counter. (Bits 23 - 16) |
| </span><span class="kw">pub fn </span>counter_bit_width(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">16</span>, <span class="number">23</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Length of EBX bit vector to enumerate architectural performance monitoring events. (Bits 31 - 24) |
| </span><span class="kw">pub fn </span>ebx_length(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">24</span>, <span class="number">31</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Number of fixed-function performance counters (if Version ID > 1). (Bits 04 - 00) |
| </span><span class="kw">pub fn </span>fixed_function_counters(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">4</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Bit width of fixed-function performance counters (if Version ID > 1). (Bits 12- 05) |
| </span><span class="kw">pub fn </span>fixed_function_counters_bit_width(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">5</span>, <span class="number">12</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"AnyThread deprecation"</span>, |
| has_any_thread_deprecation, |
| edx, |
| <span class="number">15 |
| </span>); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Core cycle event not available if 1."</span>, |
| is_core_cyc_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::CORE_CYC_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Instruction retired event not available if 1."</span>, |
| is_inst_ret_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::INST_RET_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Reference cycles event not available if 1."</span>, |
| is_ref_cycle_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::REF_CYC_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Last-level cache reference event not available if 1."</span>, |
| is_cache_ref_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::CACHE_REF_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Last-level cache misses event not available if 1."</span>, |
| is_ll_cache_miss_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::LL_CACHE_MISS_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Branch instruction retired event not available if 1."</span>, |
| is_branch_inst_ret_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::BRANCH_INST_RET_EV_UNAVAILABLE |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Branch mispredict retired event not available if 1."</span>, |
| is_branch_midpred_ev_unavailable, |
| ebx, |
| PerformanceMonitoringFeaturesEbx::BRANCH_MISPRED_EV_UNAVAILABLE |
| ); |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>PerformanceMonitoringInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"PerformanceMonitoringInfo"</span>) |
| .field(<span class="string">"version_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.version_id()) |
| .field(<span class="string">"number_of_counters"</span>, <span class="kw-2">&</span><span class="self">self</span>.number_of_counters()) |
| .field(<span class="string">"counter_bit_width"</span>, <span class="kw-2">&</span><span class="self">self</span>.counter_bit_width()) |
| .field(<span class="string">"ebx_length"</span>, <span class="kw-2">&</span><span class="self">self</span>.ebx_length()) |
| .field(<span class="string">"fixed_function_counters"</span>, <span class="kw-2">&</span><span class="self">self</span>.fixed_function_counters()) |
| .field( |
| <span class="string">"fixed_function_counters_bit_width"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.fixed_function_counters_bit_width(), |
| ) |
| .finish() |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>PerformanceMonitoringFeaturesEbx: u32 { |
| <span class="doccomment">/// Core cycle event not available if 1. (Bit 0) |
| </span><span class="kw">const </span>CORE_CYC_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">0</span>; |
| <span class="doccomment">/// Instruction retired event not available if 1. (Bit 01) |
| </span><span class="kw">const </span>INST_RET_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">1</span>; |
| <span class="doccomment">/// Reference cycles event not available if 1. (Bit 02) |
| </span><span class="kw">const </span>REF_CYC_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">2</span>; |
| <span class="doccomment">/// Last-level cache reference event not available if 1. (Bit 03) |
| </span><span class="kw">const </span>CACHE_REF_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">3</span>; |
| <span class="doccomment">/// Last-level cache misses event not available if 1. (Bit 04) |
| </span><span class="kw">const </span>LL_CACHE_MISS_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">4</span>; |
| <span class="doccomment">/// Branch instruction retired event not available if 1. (Bit 05) |
| </span><span class="kw">const </span>BRANCH_INST_RET_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">5</span>; |
| <span class="doccomment">/// Branch mispredict retired event not available if 1. (Bit 06) |
| </span><span class="kw">const </span>BRANCH_MISPRED_EV_UNAVAILABLE = <span class="number">1 </span><< <span class="number">6</span>; |
| } |
| } |
| |
| <span class="doccomment">/// Information about topology (LEAF=0x0B). |
| /// |
| /// Iterates over the system topology in order to retrieve more system |
| /// information at each level of the topology: how many cores and what kind of |
| /// cores |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[derive(Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedTopologyIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| level: u32, |
| is_v2: bool, |
| } |
| |
| <span class="doccomment">/// Gives information about the current level in the topology. |
| /// |
| /// How many cores, what type etc. |
| </span><span class="attribute">#[derive(PartialEq, Eq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedTopologyLevel { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>fmt::Debug <span class="kw">for </span>ExtendedTopologyLevel { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| f.debug_struct(<span class="string">"ExtendedTopologyLevel"</span>) |
| .field(<span class="string">"processors"</span>, <span class="kw-2">&</span><span class="self">self</span>.processors()) |
| .field(<span class="string">"number"</span>, <span class="kw-2">&</span><span class="self">self</span>.level_number()) |
| .field(<span class="string">"type"</span>, <span class="kw-2">&</span><span class="self">self</span>.level_type()) |
| .field(<span class="string">"x2apic_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.x2apic_id()) |
| .field(<span class="string">"next_apic_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.shift_right_for_next_apic_id()) |
| .finish() |
| } |
| } |
| |
| <span class="kw">impl </span>ExtendedTopologyLevel { |
| <span class="doccomment">/// Number of logical processors at this level type. |
| /// The number reflects configuration as shipped. |
| </span><span class="kw">pub fn </span>processors(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Level number. |
| </span><span class="kw">pub fn </span>level_number(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ecx, <span class="number">0</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="comment">// Level type. |
| </span><span class="kw">pub fn </span>level_type(<span class="kw-2">&</span><span class="self">self</span>) -> TopologyType { |
| <span class="kw">match </span>get_bits(<span class="self">self</span>.ecx, <span class="number">8</span>, <span class="number">15</span>) { |
| <span class="number">0 </span>=> TopologyType::Invalid, |
| <span class="number">1 </span>=> TopologyType::SMT, |
| <span class="number">2 </span>=> TopologyType::Core, |
| <span class="number">3 </span>=> TopologyType::Module, |
| <span class="number">4 </span>=> TopologyType::Tile, |
| <span class="number">5 </span>=> TopologyType::Die, |
| <span class="kw">_ </span>=> <span class="macro">unreachable!</span>(), |
| } |
| } |
| |
| <span class="doccomment">/// x2APIC ID the current logical processor. (Bits 31-00) |
| </span><span class="kw">pub fn </span>x2apic_id(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.edx |
| } |
| |
| <span class="doccomment">/// Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type. (Bits 04-00) |
| /// All logical processors with the same next level ID share current level. |
| </span><span class="kw">pub fn </span>shift_right_for_next_apic_id(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">4</span>) |
| } |
| } |
| |
| <span class="doccomment">/// What type of core we have at this level in the topology (real CPU or hyper-threaded). |
| </span><span class="attribute">#[derive(PartialEq, Eq, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>TopologyType { |
| Invalid = <span class="number">0</span>, |
| <span class="doccomment">/// Hyper-thread (Simultaneous multithreading) |
| </span>SMT = <span class="number">1</span>, |
| Core = <span class="number">2</span>, |
| Module = <span class="number">3</span>, |
| Tile = <span class="number">4</span>, |
| Die = <span class="number">5</span>, |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>TopologyType { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="kw">let </span>data = <span class="kw">match </span><span class="self">self </span>{ |
| TopologyType::Invalid => <span class="string">"Invalid"</span>, |
| TopologyType::SMT => <span class="string">"SMT"</span>, |
| TopologyType::Core => <span class="string">"Core"</span>, |
| TopologyType::Module => <span class="string">"Module"</span>, |
| TopologyType::Tile => <span class="string">"Tile"</span>, |
| TopologyType::Die => <span class="string">"Die"</span>, |
| }; |
| |
| f.write_str(data) |
| } |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>ExtendedTopologyIter { |
| <span class="kw">type </span>Item = ExtendedTopologyLevel; |
| |
| <span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedTopologyLevel> { |
| <span class="kw">let </span>res = <span class="kw">if </span><span class="self">self</span>.is_v2 { |
| <span class="self">self</span>.read.cpuid2(EAX_EXTENDED_TOPOLOGY_INFO_V2, <span class="self">self</span>.level) |
| } <span class="kw">else </span>{ |
| <span class="self">self</span>.read.cpuid2(EAX_EXTENDED_TOPOLOGY_INFO, <span class="self">self</span>.level) |
| }; |
| <span class="self">self</span>.level += <span class="number">1</span>; |
| |
| <span class="kw">let </span>et = ExtendedTopologyLevel { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }; |
| |
| <span class="kw">match </span>et.level_type() { |
| TopologyType::Invalid => <span class="prelude-val">None</span>, |
| <span class="kw">_ </span>=> <span class="prelude-val">Some</span>(et), |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ExtendedTopologyIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ExtendedStateInfoXCR0Flags: u32 { |
| <span class="doccomment">/// legacy x87 (Bit 00). |
| </span><span class="kw">const </span>LEGACY_X87 = <span class="number">1 </span><< <span class="number">0</span>; |
| |
| <span class="doccomment">/// 128-bit SSE (Bit 01). |
| </span><span class="kw">const </span>SSE128 = <span class="number">1 </span><< <span class="number">1</span>; |
| |
| <span class="doccomment">/// 256-bit AVX (Bit 02). |
| </span><span class="kw">const </span>AVX256 = <span class="number">1 </span><< <span class="number">2</span>; |
| |
| <span class="doccomment">/// MPX BNDREGS (Bit 03). |
| </span><span class="kw">const </span>MPX_BNDREGS = <span class="number">1 </span><< <span class="number">3</span>; |
| |
| <span class="doccomment">/// MPX BNDCSR (Bit 04). |
| </span><span class="kw">const </span>MPX_BNDCSR = <span class="number">1 </span><< <span class="number">4</span>; |
| |
| <span class="doccomment">/// AVX512 OPMASK (Bit 05). |
| </span><span class="kw">const </span>AVX512_OPMASK = <span class="number">1 </span><< <span class="number">5</span>; |
| |
| <span class="doccomment">/// AVX ZMM Hi256 (Bit 06). |
| </span><span class="kw">const </span>AVX512_ZMM_HI256 = <span class="number">1 </span><< <span class="number">6</span>; |
| |
| <span class="doccomment">/// AVX 512 ZMM Hi16 (Bit 07). |
| </span><span class="kw">const </span>AVX512_ZMM_HI16 = <span class="number">1 </span><< <span class="number">7</span>; |
| |
| <span class="doccomment">/// PKRU state (Bit 09). |
| </span><span class="kw">const </span>PKRU = <span class="number">1 </span><< <span class="number">9</span>; |
| |
| <span class="doccomment">/// IA32_XSS HDC State (Bit 13). |
| </span><span class="kw">const </span>IA32_XSS_HDC = <span class="number">1 </span><< <span class="number">13</span>; |
| } |
| } |
| |
| <span class="macro">bitflags! </span>{ |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">struct </span>ExtendedStateInfoXSSFlags: u32 { |
| <span class="doccomment">/// IA32_XSS PT (Trace Packet) State (Bit 08). |
| </span><span class="kw">const </span>PT = <span class="number">1 </span><< <span class="number">8</span>; |
| |
| <span class="doccomment">/// IA32_XSS HDC State (Bit 13). |
| </span><span class="kw">const </span>HDC = <span class="number">1 </span><< <span class="number">13</span>; |
| } |
| } |
| |
| <span class="doccomment">/// Information for saving/restoring extended register state (LEAF=0x0D). |
| /// |
| /// # Platforms |
| /// ✅ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedStateInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| eax: ExtendedStateInfoXCR0Flags, |
| ebx: u32, |
| ecx: u32, |
| _edx: u32, |
| eax1: u32, |
| ebx1: u32, |
| ecx1: ExtendedStateInfoXSSFlags, |
| _edx1: u32, |
| } |
| |
| <span class="kw">impl </span>ExtendedStateInfo { |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for legacy x87 in XCR0."</span>, |
| xcr0_supports_legacy_x87, |
| eax, |
| ExtendedStateInfoXCR0Flags::LEGACY_X87 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for SSE 128-bit in XCR0."</span>, |
| xcr0_supports_sse_128, |
| eax, |
| ExtendedStateInfoXCR0Flags::SSE128 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for AVX 256-bit in XCR0."</span>, |
| xcr0_supports_avx_256, |
| eax, |
| ExtendedStateInfoXCR0Flags::AVX256 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for MPX BNDREGS in XCR0."</span>, |
| xcr0_supports_mpx_bndregs, |
| eax, |
| ExtendedStateInfoXCR0Flags::MPX_BNDREGS |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for MPX BNDCSR in XCR0."</span>, |
| xcr0_supports_mpx_bndcsr, |
| eax, |
| ExtendedStateInfoXCR0Flags::MPX_BNDCSR |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for AVX512 OPMASK in XCR0."</span>, |
| xcr0_supports_avx512_opmask, |
| eax, |
| ExtendedStateInfoXCR0Flags::AVX512_OPMASK |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for AVX512 ZMM Hi256 XCR0."</span>, |
| xcr0_supports_avx512_zmm_hi256, |
| eax, |
| ExtendedStateInfoXCR0Flags::AVX512_ZMM_HI256 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for AVX512 ZMM Hi16 in XCR0."</span>, |
| xcr0_supports_avx512_zmm_hi16, |
| eax, |
| ExtendedStateInfoXCR0Flags::AVX512_ZMM_HI16 |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for PKRU in XCR0."</span>, |
| xcr0_supports_pkru, |
| eax, |
| ExtendedStateInfoXCR0Flags::PKRU |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for PT in IA32_XSS."</span>, |
| ia32_xss_supports_pt, |
| ecx1, |
| ExtendedStateInfoXSSFlags::PT |
| ); |
| |
| <span class="macro">check_flag!</span>( |
| doc = <span class="string">"Support for HDC in IA32_XSS."</span>, |
| ia32_xss_supports_hdc, |
| ecx1, |
| ExtendedStateInfoXSSFlags::HDC |
| ); |
| |
| <span class="doccomment">/// Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by |
| /// enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area |
| /// are not enabled. |
| </span><span class="kw">pub fn </span>xsave_area_size_enabled_features(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the |
| /// XSAVE/XRSTOR save area required by all supported features in the processor, |
| /// i.e all the valid bit fields in XCR0. |
| </span><span class="kw">pub fn </span>xsave_area_size_supported_features(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="doccomment">/// CPU has xsaveopt feature. |
| </span><span class="kw">pub fn </span>has_xsaveopt(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax1 & <span class="number">0x1 </span>> <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// Supports XSAVEC and the compacted form of XRSTOR if set. |
| </span><span class="kw">pub fn </span>has_xsavec(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax1 & <span class="number">0b10 </span>> <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// Supports XGETBV with ECX = 1 if set. |
| </span><span class="kw">pub fn </span>has_xgetbv(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax1 & <span class="number">0b100 </span>> <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// Supports XSAVES/XRSTORS and IA32_XSS if set. |
| </span><span class="kw">pub fn </span>has_xsaves_xrstors(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.eax1 & <span class="number">0b1000 </span>> <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS. |
| </span><span class="kw">pub fn </span>xsave_size(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx1 |
| } |
| |
| <span class="doccomment">/// Iterator over extended state enumeration levels >= 2. |
| </span><span class="kw">pub fn </span>iter(<span class="kw-2">&</span><span class="self">self</span>) -> ExtendedStateIter { |
| ExtendedStateIter { |
| read: <span class="self">self</span>.read, |
| level: <span class="number">1</span>, |
| supported_xcr0: <span class="self">self</span>.eax.bits(), |
| supported_xss: <span class="self">self</span>.ecx1.bits(), |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ExtendedStateInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"ExtendedStateInfo"</span>) |
| .field(<span class="string">"eax"</span>, <span class="kw-2">&</span><span class="self">self</span>.eax) |
| .field(<span class="string">"ecx1"</span>, <span class="kw-2">&</span><span class="self">self</span>.ecx1) |
| .field( |
| <span class="string">"xsave_area_size_enabled_features"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.xsave_area_size_enabled_features(), |
| ) |
| .field( |
| <span class="string">"xsave_area_size_supported_features"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.xsave_area_size_supported_features(), |
| ) |
| .field(<span class="string">"has_xsaveopt"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_xsaveopt()) |
| .field(<span class="string">"has_xsavec"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_xsavec()) |
| .field(<span class="string">"has_xgetbv"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_xgetbv()) |
| .field(<span class="string">"has_xsaves_xrstors"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_xsaves_xrstors()) |
| .field(<span class="string">"xsave_size"</span>, <span class="kw-2">&</span><span class="self">self</span>.xsave_size()) |
| .field(<span class="string">"extended_state_iter"</span>, <span class="kw-2">&</span><span class="self">self</span>.iter()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Yields [ExtendedState] structs. |
| </span><span class="attribute">#[derive(Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedStateIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| level: u32, |
| supported_xcr0: u32, |
| supported_xss: u32, |
| } |
| |
| <span class="doccomment">/// When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid |
| /// sub-leaf index), the processor returns information about the size and offset |
| /// of each processor extended state save area within the XSAVE/XRSTOR area. |
| /// |
| /// The iterator goes over the valid sub-leaves and obtain size and offset |
| /// information for each processor extended state save area: |
| </span><span class="kw">impl </span>Iterator <span class="kw">for </span>ExtendedStateIter { |
| <span class="kw">type </span>Item = ExtendedState; |
| |
| <span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><ExtendedState> { |
| <span class="self">self</span>.level += <span class="number">1</span>; |
| <span class="kw">if </span><span class="self">self</span>.level > <span class="number">31 </span>{ |
| <span class="kw">return </span><span class="prelude-val">None</span>; |
| } |
| |
| <span class="kw">let </span>bit = <span class="number">1 </span><< <span class="self">self</span>.level; |
| <span class="kw">if </span>(<span class="self">self</span>.supported_xcr0 & bit > <span class="number">0</span>) || (<span class="self">self</span>.supported_xss & bit > <span class="number">0</span>) { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_EXTENDED_STATE_INFO, <span class="self">self</span>.level); |
| <span class="kw">return </span><span class="prelude-val">Some</span>(ExtendedState { |
| subleaf: <span class="self">self</span>.level, |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| }); |
| } |
| |
| <span class="self">self</span>.next() |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ExtendedStateIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="doccomment">/// What kidn of extended register state this is. |
| </span><span class="attribute">#[derive(PartialEq, Eq, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| #[repr(u32)] |
| </span><span class="kw">pub enum </span>ExtendedRegisterType { |
| Avx, |
| MpxBndregs, |
| MpxBndcsr, |
| Avx512Opmask, |
| Avx512ZmmHi256, |
| Avx512ZmmHi16, |
| Pt, |
| Pkru, |
| Hdc, |
| Unknown(u32), |
| } |
| |
| <span class="kw">impl </span>From<u32> <span class="kw">for </span>ExtendedRegisterType { |
| <span class="kw">fn </span>from(value: u32) -> ExtendedRegisterType { |
| <span class="kw">match </span>value { |
| <span class="number">0x2 </span>=> ExtendedRegisterType::Avx, |
| <span class="number">0x3 </span>=> ExtendedRegisterType::MpxBndregs, |
| <span class="number">0x4 </span>=> ExtendedRegisterType::MpxBndcsr, |
| <span class="number">0x5 </span>=> ExtendedRegisterType::Avx512Opmask, |
| <span class="number">0x6 </span>=> ExtendedRegisterType::Avx512ZmmHi256, |
| <span class="number">0x7 </span>=> ExtendedRegisterType::Avx512ZmmHi16, |
| <span class="number">0x8 </span>=> ExtendedRegisterType::Pt, |
| <span class="number">0x9 </span>=> ExtendedRegisterType::Pkru, |
| <span class="number">0xd </span>=> ExtendedRegisterType::Hdc, |
| x => ExtendedRegisterType::Unknown(x), |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>ExtendedRegisterType { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="kw">let </span>data = <span class="kw">match </span><span class="self">self </span>{ |
| ExtendedRegisterType::Avx => <span class="string">"AVX/YMM"</span>, |
| ExtendedRegisterType::MpxBndregs => <span class="string">"MPX BNDREGS"</span>, |
| ExtendedRegisterType::MpxBndcsr => <span class="string">"MPX BNDCSR"</span>, |
| ExtendedRegisterType::Avx512Opmask => <span class="string">"AVX-512 opmask"</span>, |
| ExtendedRegisterType::Avx512ZmmHi256 => <span class="string">"AVX-512 ZMM_Hi256"</span>, |
| ExtendedRegisterType::Avx512ZmmHi16 => <span class="string">"AVX-512 Hi16_ZMM"</span>, |
| ExtendedRegisterType::Pkru => <span class="string">"PKRU"</span>, |
| ExtendedRegisterType::Pt => <span class="string">"PT"</span>, |
| ExtendedRegisterType::Hdc => <span class="string">"HDC"</span>, |
| ExtendedRegisterType::Unknown(t) => { |
| <span class="kw">return </span><span class="macro">write!</span>(f, <span class="string">"Unknown({})"</span>, t); |
| } |
| }; |
| |
| f.write_str(data) |
| } |
| } |
| |
| <span class="doccomment">/// Where the extended register state is stored. |
| </span><span class="attribute">#[derive(PartialEq, Eq, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>ExtendedRegisterStateLocation { |
| Xcr0, |
| Ia32Xss, |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>ExtendedRegisterStateLocation { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="kw">let </span>data = <span class="kw">match </span><span class="self">self </span>{ |
| ExtendedRegisterStateLocation::Xcr0 => <span class="string">"XCR0 (user state)"</span>, |
| ExtendedRegisterStateLocation::Ia32Xss => <span class="string">"IA32_XSS (supervisor state)"</span>, |
| }; |
| |
| f.write_str(data) |
| } |
| } |
| |
| <span class="doccomment">/// ExtendedState subleaf structure for things that need to be restored. |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ExtendedState { |
| <span class="kw">pub </span>subleaf: u32, |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| } |
| |
| <span class="kw">impl </span>ExtendedState { |
| <span class="doccomment">/// Returns which register this specific extended subleaf contains information for. |
| </span><span class="kw">pub fn </span>register(<span class="kw-2">&</span><span class="self">self</span>) -> ExtendedRegisterType { |
| <span class="self">self</span>.subleaf.into() |
| } |
| |
| <span class="doccomment">/// The size in bytes (from the offset specified in EBX) of the save area |
| /// for an extended state feature associated with a valid sub-leaf index, n. |
| /// This field reports 0 if the sub-leaf index, n, is invalid. |
| </span><span class="kw">pub fn </span>size(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.eax |
| } |
| |
| <span class="doccomment">/// The offset in bytes of this extended state components save area |
| /// from the beginning of the XSAVE/XRSTOR area. |
| </span><span class="kw">pub fn </span>offset(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="kw">pub fn </span>location(<span class="kw-2">&</span><span class="self">self</span>) -> ExtendedRegisterStateLocation { |
| <span class="kw">if </span><span class="self">self</span>.is_in_xcr0() { |
| ExtendedRegisterStateLocation::Xcr0 |
| } <span class="kw">else </span>{ |
| ExtendedRegisterStateLocation::Ia32Xss |
| } |
| } |
| |
| <span class="doccomment">/// True if the bit n (corresponding to the sub-leaf index) |
| /// is supported in the IA32_XSS MSR; |
| /// |
| /// # Deprecation note |
| /// This will likely be removed in the future. Use `location()` instead. |
| </span><span class="kw">pub fn </span>is_in_ia32_xss(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx & <span class="number">0b1 </span>> <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// True if bit n is supported in XCR0. |
| /// |
| /// # Deprecation note |
| /// This will likely be removed in the future. Use `location()` instead. |
| </span><span class="kw">pub fn </span>is_in_xcr0(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx & <span class="number">0b1 </span>== <span class="number">0 |
| </span>} |
| |
| <span class="doccomment">/// Returns true when the compacted format of an XSAVE area is used, |
| /// this extended state component located on the next 64-byte |
| /// boundary following the preceding state component |
| /// (otherwise, it is located immediately following the preceding state component). |
| </span><span class="kw">pub fn </span>is_compacted_format(<span class="kw-2">&</span><span class="self">self</span>) -> bool { |
| <span class="self">self</span>.ecx & <span class="number">0b10 </span>> <span class="number">0 |
| </span>} |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ExtendedState { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| f.debug_struct(<span class="string">"ExtendedState"</span>) |
| .field(<span class="string">"size"</span>, <span class="kw-2">&</span><span class="self">self</span>.size()) |
| .field(<span class="string">"offset"</span>, <span class="kw-2">&</span><span class="self">self</span>.offset()) |
| .field(<span class="string">"is_in_ia32_xss"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_in_ia32_xss()) |
| .field(<span class="string">"is_in_xcr0"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_in_xcr0()) |
| .field(<span class="string">"is_compacted_format"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_compacted_format()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Intel Resource Director Technology RDT (LEAF=0x0F). |
| /// |
| /// Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0 and ECX = 1) |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>RdtMonitoringInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| ebx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>RdtMonitoringInfo { |
| <span class="doccomment">/// Maximum range (zero-based) of RMID within this physical processor of all types. |
| </span><span class="kw">pub fn </span>rmid_range(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports L3 Cache Intel RDT Monitoring."</span>, |
| has_l3_monitoring, |
| edx, |
| <span class="number">1 |
| </span>); |
| |
| <span class="doccomment">/// L3 Cache Monitoring. |
| </span><span class="kw">pub fn </span>l3_monitoring(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><L3MonitoringInfo> { |
| <span class="kw">if </span><span class="self">self</span>.has_l3_monitoring() { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_RDT_MONITORING, <span class="number">1</span>); |
| <span class="prelude-val">Some</span>(L3MonitoringInfo { |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>RdtMonitoringInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"RdtMonitoringInfo"</span>) |
| .field(<span class="string">"rmid_range"</span>, <span class="kw-2">&</span><span class="self">self</span>.rmid_range()) |
| .field(<span class="string">"l3_monitoring"</span>, <span class="kw-2">&</span><span class="self">self</span>.l3_monitoring()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Information about L3 cache monitoring. |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>L3MonitoringInfo { |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>L3MonitoringInfo { |
| <span class="doccomment">/// Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). |
| </span><span class="kw">pub fn </span>conversion_factor(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// Maximum range (zero-based) of RMID of L3. |
| </span><span class="kw">pub fn </span>maximum_rmid_range(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports occupancy monitoring."</span>, |
| has_occupancy_monitoring, |
| edx, |
| <span class="number">0 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports total bandwidth monitoring."</span>, |
| has_total_bandwidth_monitoring, |
| edx, |
| <span class="number">1 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports local bandwidth monitoring."</span>, |
| has_local_bandwidth_monitoring, |
| edx, |
| <span class="number">2 |
| </span>); |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>L3MonitoringInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"L3MonitoringInfo"</span>) |
| .field(<span class="string">"conversion_factor"</span>, <span class="kw-2">&</span><span class="self">self</span>.conversion_factor()) |
| .field(<span class="string">"maximum_rmid_range"</span>, <span class="kw-2">&</span><span class="self">self</span>.maximum_rmid_range()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Quality of service enforcement information (LEAF=0x10). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>RdtAllocationInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| ebx: u32, |
| } |
| |
| <span class="kw">impl </span>RdtAllocationInfo { |
| <span class="macro">check_bit_fn!</span>(doc = <span class="string">"Supports L3 Cache Allocation."</span>, has_l3_cat, ebx, <span class="number">1</span>); |
| |
| <span class="macro">check_bit_fn!</span>(doc = <span class="string">"Supports L2 Cache Allocation."</span>, has_l2_cat, ebx, <span class="number">2</span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports Memory Bandwidth Allocation."</span>, |
| has_memory_bandwidth_allocation, |
| ebx, |
| <span class="number">3 |
| </span>); |
| |
| <span class="doccomment">/// L3 Cache Allocation Information. |
| </span><span class="kw">pub fn </span>l3_cat(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><L3CatInfo> { |
| <span class="kw">if </span><span class="self">self</span>.has_l3_cat() { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_RDT_ALLOCATION, <span class="number">1</span>); |
| <span class="prelude-val">Some</span>(L3CatInfo { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// L2 Cache Allocation Information. |
| </span><span class="kw">pub fn </span>l2_cat(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><L2CatInfo> { |
| <span class="kw">if </span><span class="self">self</span>.has_l2_cat() { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_RDT_ALLOCATION, <span class="number">2</span>); |
| <span class="prelude-val">Some</span>(L2CatInfo { |
| eax: res.eax, |
| ebx: res.ebx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// Memory Bandwidth Allocation Information. |
| </span><span class="kw">pub fn </span>memory_bandwidth_allocation(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><MemBwAllocationInfo> { |
| <span class="kw">if </span><span class="self">self</span>.has_memory_bandwidth_allocation() { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_RDT_ALLOCATION, <span class="number">3</span>); |
| <span class="prelude-val">Some</span>(MemBwAllocationInfo { |
| eax: res.eax, |
| ecx: res.ecx, |
| edx: res.edx, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>RdtAllocationInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"RdtAllocationInfo"</span>) |
| .field(<span class="string">"l3_cat"</span>, <span class="kw-2">&</span><span class="self">self</span>.l3_cat()) |
| .field(<span class="string">"l2_cat"</span>, <span class="kw-2">&</span><span class="self">self</span>.l2_cat()) |
| .field( |
| <span class="string">"memory_bandwidth_allocation"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.memory_bandwidth_allocation(), |
| ) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// L3 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=1). |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>L3CatInfo { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>L3CatInfo { |
| <span class="doccomment">/// Length of the capacity bit mask. |
| </span><span class="kw">pub fn </span>capacity_mask_length(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| (get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">4</span>) + <span class="number">1</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Bit-granular map of isolation/contention of allocation units. |
| </span><span class="kw">pub fn </span>isolation_bitmap(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// Highest COS number supported for this Leaf. |
| </span><span class="kw">pub fn </span>highest_cos(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Is Code and Data Prioritization Technology supported?"</span>, |
| has_code_data_prioritization, |
| ecx, |
| <span class="number">2 |
| </span>); |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>L3CatInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"L3CatInfo"</span>) |
| .field(<span class="string">"capacity_mask_length"</span>, <span class="kw-2">&</span><span class="self">self</span>.capacity_mask_length()) |
| .field(<span class="string">"isolation_bitmap"</span>, <span class="kw-2">&</span><span class="self">self</span>.isolation_bitmap()) |
| .field(<span class="string">"highest_cos"</span>, <span class="kw-2">&</span><span class="self">self</span>.highest_cos()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// L2 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=2). |
| </span><span class="attribute">#[derive(Eq, PartialEq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>L2CatInfo { |
| eax: u32, |
| ebx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>L2CatInfo { |
| <span class="doccomment">/// Length of the capacity bit mask. |
| </span><span class="kw">pub fn </span>capacity_mask_length(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| (get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">4</span>) + <span class="number">1</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Bit-granular map of isolation/contention of allocation units. |
| </span><span class="kw">pub fn </span>isolation_bitmap(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// Highest COS number supported for this Leaf. |
| </span><span class="kw">pub fn </span>highest_cos(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>L2CatInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"L2CatInfo"</span>) |
| .field(<span class="string">"capacity_mask_length"</span>, <span class="kw-2">&</span><span class="self">self</span>.capacity_mask_length()) |
| .field(<span class="string">"isolation_bitmap"</span>, <span class="kw-2">&</span><span class="self">self</span>.isolation_bitmap()) |
| .field(<span class="string">"highest_cos"</span>, <span class="kw-2">&</span><span class="self">self</span>.highest_cos()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Memory Bandwidth Allocation Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=3). |
| </span><span class="attribute">#[derive(Eq, PartialEq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>MemBwAllocationInfo { |
| eax: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>MemBwAllocationInfo { |
| <span class="doccomment">/// Reports the maximum MBA throttling value supported for the corresponding ResID. |
| </span><span class="kw">pub fn </span>max_hba_throttling(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| (get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">11</span>) + <span class="number">1</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Highest COS number supported for this Leaf. |
| </span><span class="kw">pub fn </span>highest_cos(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Reports whether the response of the delay values is linear."</span>, |
| has_linear_response_delay, |
| ecx, |
| <span class="number">2 |
| </span>); |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>MemBwAllocationInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"MemBwAllocationInfo"</span>) |
| .field(<span class="string">"max_hba_throttling"</span>, <span class="kw-2">&</span><span class="self">self</span>.max_hba_throttling()) |
| .field(<span class="string">"highest_cos"</span>, <span class="kw-2">&</span><span class="self">self</span>.highest_cos()) |
| .field( |
| <span class="string">"has_linear_response_delay"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_linear_response_delay(), |
| ) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Intel SGX Capability Enumeration Leaf (LEAF=0x12). |
| /// |
| /// Two sub-leafs: (EAX = 12H, ECX = 0 and ECX = 1) |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>SgxInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| eax: u32, |
| ebx: u32, |
| _ecx: u32, |
| edx: u32, |
| eax1: u32, |
| ebx1: u32, |
| ecx1: u32, |
| edx1: u32, |
| } |
| |
| <span class="kw">impl </span>SgxInfo { |
| <span class="macro">check_bit_fn!</span>(doc = <span class="string">"Has SGX1 support."</span>, has_sgx1, eax, <span class="number">0</span>); |
| <span class="macro">check_bit_fn!</span>(doc = <span class="string">"Has SGX2 support."</span>, has_sgx2, eax, <span class="number">1</span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports ENCLV instruction leaves EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT."</span>, |
| has_enclv_leaves_einvirtchild_edecvirtchild_esetcontext, |
| eax, |
| <span class="number">5 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Supports ENCLS instruction leaves ETRACKC, ERDINFO, ELDBC, and ELDUC."</span>, |
| has_encls_leaves_etrackc_erdinfo_eldbc_elduc, |
| eax, |
| <span class="number">6 |
| </span>); |
| |
| <span class="doccomment">/// Bit vector of supported extended SGX features. |
| </span><span class="kw">pub fn </span>miscselect(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// The maximum supported enclave size in non-64-bit mode is 2^retval. |
| </span><span class="kw">pub fn </span>max_enclave_size_non_64bit(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// The maximum supported enclave size in 64-bit mode is 2^retval. |
| </span><span class="kw">pub fn </span>max_enclave_size_64bit(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">8</span>, <span class="number">15</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Reports the valid bits of SECS.ATTRIBUTES\[127:0\] that software can set with ECREATE. |
| </span><span class="kw">pub fn </span>secs_attributes(<span class="kw-2">&</span><span class="self">self</span>) -> (u64, u64) { |
| <span class="kw">let </span>lower = <span class="self">self</span>.eax1 <span class="kw">as </span>u64 | (<span class="self">self</span>.ebx1 <span class="kw">as </span>u64) << <span class="number">32</span>; |
| <span class="kw">let </span>upper = <span class="self">self</span>.ecx1 <span class="kw">as </span>u64 | (<span class="self">self</span>.edx1 <span class="kw">as </span>u64) << <span class="number">32</span>; |
| (lower, upper) |
| } |
| <span class="doccomment">/// Iterator over SGX sub-leafs. |
| </span><span class="kw">pub fn </span>iter(<span class="kw-2">&</span><span class="self">self</span>) -> SgxSectionIter { |
| SgxSectionIter { |
| read: <span class="self">self</span>.read, |
| current: <span class="number">2</span>, |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>SgxInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"SgxInfo"</span>) |
| .field(<span class="string">"has_sgx1"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_sgx1()) |
| .field(<span class="string">"has_sgx2"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_sgx2()) |
| .field(<span class="string">"miscselect"</span>, <span class="kw-2">&</span><span class="self">self</span>.miscselect()) |
| .field( |
| <span class="string">"max_enclave_size_non_64bit"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.max_enclave_size_non_64bit(), |
| ) |
| .field(<span class="string">"max_enclave_size_64bit"</span>, <span class="kw-2">&</span><span class="self">self</span>.max_enclave_size_64bit()) |
| .field( |
| <span class="string">"has_encls_leaves_etrackc_erdinfo_eldbc_elduc"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_encls_leaves_etrackc_erdinfo_eldbc_elduc(), |
| ) |
| .field( |
| <span class="string">"has_enclv_leaves_einvirtchild_edecvirtchild_esetcontext"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.has_enclv_leaves_einvirtchild_edecvirtchild_esetcontext(), |
| ) |
| .field(<span class="string">"sgx_section_iter"</span>, <span class="kw-2">&</span><span class="self">self</span>.iter()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Iterator over the SGX sub-leafs (ECX >= 2). |
| </span><span class="attribute">#[derive(Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>SgxSectionIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| current: u32, |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>SgxSectionIter { |
| <span class="kw">type </span>Item = SgxSectionInfo; |
| |
| <span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SgxSectionInfo> { |
| <span class="kw">let </span>res = <span class="self">self</span>.read.cpuid2(EAX_SGX, <span class="self">self</span>.current); |
| <span class="self">self</span>.current += <span class="number">1</span>; |
| <span class="kw">match </span>get_bits(res.eax, <span class="number">0</span>, <span class="number">3</span>) { |
| <span class="number">0b0001 </span>=> <span class="prelude-val">Some</span>(SgxSectionInfo::Epc(EpcSection { |
| eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| })), |
| <span class="kw">_ </span>=> <span class="prelude-val">None</span>, |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>SgxSectionIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="doccomment">/// Intel SGX EPC Enumeration Leaf |
| /// |
| /// Sub-leaves 2 or higher. |
| </span><span class="attribute">#[derive(Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>SgxSectionInfo { |
| <span class="comment">// This would be nice: https://github.com/rust-lang/rfcs/pull/1450 |
| </span>Epc(EpcSection), |
| } |
| |
| <span class="doccomment">/// EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section |
| </span><span class="attribute">#[derive(Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>EpcSection { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>EpcSection { |
| <span class="doccomment">/// The physical address of the base of the EPC section |
| </span><span class="kw">pub fn </span>physical_base(<span class="kw-2">&</span><span class="self">self</span>) -> u64 { |
| <span class="kw">let </span>lower = (get_bits(<span class="self">self</span>.eax, <span class="number">12</span>, <span class="number">31</span>) << <span class="number">12</span>) <span class="kw">as </span>u64; |
| <span class="kw">let </span>upper = (get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">19</span>) <span class="kw">as </span>u64) << <span class="number">32</span>; |
| lower | upper |
| } |
| |
| <span class="doccomment">/// Size of the corresponding EPC section within the Processor Reserved Memory. |
| </span><span class="kw">pub fn </span>size(<span class="kw-2">&</span><span class="self">self</span>) -> u64 { |
| <span class="kw">let </span>lower = (get_bits(<span class="self">self</span>.ecx, <span class="number">12</span>, <span class="number">31</span>) << <span class="number">12</span>) <span class="kw">as </span>u64; |
| <span class="kw">let </span>upper = (get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">19</span>) <span class="kw">as </span>u64) << <span class="number">32</span>; |
| lower | upper |
| } |
| } |
| |
| <span class="doccomment">/// Intel Processor Trace Information (LEAF=0x14). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ProcessorTraceInfo { |
| _eax: u32, |
| ebx: u32, |
| ecx: u32, |
| _edx: u32, |
| leaf1: <span class="prelude-ty">Option</span><CpuIdResult>, |
| } |
| |
| <span class="kw">impl </span>ProcessorTraceInfo { |
| <span class="comment">// EBX features |
| </span><span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and \ |
| that IA32_RTIT_CR3_MATCH MSR can be accessed."</span>, |
| has_rtit_cr3_match, |
| ebx, |
| <span class="number">0 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates support of Configurable PSB and Cycle-Accurate Mode."</span>, |
| has_configurable_psb_and_cycle_accurate_mode, |
| ebx, |
| <span class="number">1 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates support of IP Filtering, TraceStop filtering, and \ |
| preservation of Intel PT MSRs across warm reset."</span>, |
| has_ip_tracestop_filtering, |
| ebx, |
| <span class="number">2 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates support of MTC timing packet and suppression of \ |
| COFI-based packets."</span>, |
| has_mtc_timing_packet_coefi_suppression, |
| ebx, |
| <span class="number">3 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Indicates support of PTWRITE. Writes can set IA32_RTIT_CTL\\[12\\] (PTWEn \ |
| and IA32_RTIT_CTL\\[5\\] (FUPonPTW), and PTWRITE can generate packets"</span>, |
| has_ptwrite, |
| ebx, |
| <span class="number">4 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Support of Power Event Trace. Writes can set IA32_RTIT_CTL\\[4\\] (PwrEvtEn) \ |
| enabling Power Event Trace packet generation."</span>, |
| has_power_event_trace, |
| ebx, |
| <span class="number">5 |
| </span>); |
| |
| <span class="comment">// ECX features |
| </span><span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence \ |
| utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and \ |
| IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed."</span>, |
| has_topa, |
| ecx, |
| <span class="number">0 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, ToPA tables can hold any number of output entries, up to the \ |
| maximum allowed by the MaskOrTableOffset field of \ |
| IA32_RTIT_OUTPUT_MASK_PTRS."</span>, |
| has_topa_maximum_entries, |
| ecx, |
| <span class="number">1 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates support of Single-Range Output scheme."</span>, |
| has_single_range_output_scheme, |
| ecx, |
| <span class="number">2 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Indicates support of output to Trace Transport subsystem."</span>, |
| has_trace_transport_subsystem, |
| ecx, |
| <span class="number">3 |
| </span>); |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"If true, Generated packets which contain IP payloads have LIP values, \ |
| which include the CS base component."</span>, |
| has_lip_with_cs_base, |
| ecx, |
| <span class="number">31 |
| </span>); |
| |
| <span class="doccomment">/// Number of configurable Address Ranges for filtering (Bits 2:0). |
| </span><span class="kw">pub fn </span>configurable_address_ranges(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| <span class="self">self</span>.leaf1.map_or(<span class="number">0</span>, |res| get_bits(res.eax, <span class="number">0</span>, <span class="number">2</span>) <span class="kw">as </span>u8) |
| } |
| |
| <span class="doccomment">/// Bitmap of supported MTC period encodings (Bit 31:16). |
| </span><span class="kw">pub fn </span>supported_mtc_period_encodings(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| <span class="self">self</span>.leaf1.map_or(<span class="number">0</span>, |res| get_bits(res.eax, <span class="number">16</span>, <span class="number">31</span>) <span class="kw">as </span>u16) |
| } |
| |
| <span class="doccomment">/// Bitmap of supported Cycle Threshold value encodings (Bits 15-0). |
| </span><span class="kw">pub fn </span>supported_cycle_threshold_value_encodings(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| <span class="self">self</span>.leaf1.map_or(<span class="number">0</span>, |res| get_bits(res.ebx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16) |
| } |
| |
| <span class="doccomment">/// Bitmap of supported Configurable PSB frequency encodings (Bit 31:16) |
| </span><span class="kw">pub fn </span>supported_psb_frequency_encodings(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| <span class="self">self</span>.leaf1.map_or(<span class="number">0</span>, |res| get_bits(res.ebx, <span class="number">16</span>, <span class="number">31</span>) <span class="kw">as </span>u16) |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>ProcessorTraceInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> core::fmt::Result { |
| f.debug_struct(<span class="string">"ProcessorTraceInfo"</span>) |
| .field( |
| <span class="string">"configurable_address_ranges"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.configurable_address_ranges(), |
| ) |
| .field( |
| <span class="string">"supported_mtc_period_encodings"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.supported_mtc_period_encodings(), |
| ) |
| .field( |
| <span class="string">"supported_cycle_threshold_value_encodings"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.supported_cycle_threshold_value_encodings(), |
| ) |
| .field( |
| <span class="string">"supported_psb_frequency_encodings"</span>, |
| <span class="kw-2">&</span><span class="self">self</span>.supported_psb_frequency_encodings(), |
| ) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Time Stamp Counter/Core Crystal Clock Information (LEAF=0x15). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>TscInfo { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| } |
| |
| <span class="kw">impl </span>fmt::Debug <span class="kw">for </span>TscInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| f.debug_struct(<span class="string">"TscInfo"</span>) |
| .field(<span class="string">"denominator"</span>, <span class="kw-2">&</span><span class="self">self</span>.denominator()) |
| .field(<span class="string">"numerator"</span>, <span class="kw-2">&</span><span class="self">self</span>.numerator()) |
| .field(<span class="string">"nominal_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.nominal_frequency()) |
| .field(<span class="string">"tsc_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.tsc_frequency()) |
| .finish() |
| } |
| } |
| |
| <span class="kw">impl </span>TscInfo { |
| <span class="doccomment">/// An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio. |
| </span><span class="kw">pub fn </span>denominator(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.eax |
| } |
| |
| <span class="doccomment">/// An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio. |
| /// |
| /// If this is 0, the TSC/”core crystal clock” ratio is not enumerated. |
| </span><span class="kw">pub fn </span>numerator(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ebx |
| } |
| |
| <span class="doccomment">/// An unsigned integer which is the nominal frequency of the core crystal clock in Hz. |
| /// |
| /// If this is 0, the nominal core crystal clock frequency is not enumerated. |
| </span><span class="kw">pub fn </span>nominal_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="doccomment">/// “TSC frequency” = “core crystal clock frequency” * EBX/EAX. |
| </span><span class="kw">pub fn </span>tsc_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><u64> { |
| <span class="comment">// In some case TscInfo is a valid leaf, but the values reported are still 0 |
| // we should avoid a division by zero in case denominator ends up being 0. |
| </span><span class="kw">if </span><span class="self">self</span>.nominal_frequency() == <span class="number">0 </span>|| <span class="self">self</span>.numerator() == <span class="number">0 </span>|| <span class="self">self</span>.denominator() == <span class="number">0 </span>{ |
| <span class="kw">return </span><span class="prelude-val">None</span>; |
| } |
| |
| <span class="prelude-val">Some</span>(<span class="self">self</span>.nominal_frequency() <span class="kw">as </span>u64 * <span class="self">self</span>.numerator() <span class="kw">as </span>u64 / <span class="self">self</span>.denominator() <span class="kw">as </span>u64) |
| } |
| } |
| |
| <span class="doccomment">/// Processor Frequency Information (LEAF=0x16). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>ProcessorFrequencyInfo { |
| eax: u32, |
| ebx: u32, |
| ecx: u32, |
| } |
| |
| <span class="kw">impl </span>ProcessorFrequencyInfo { |
| <span class="doccomment">/// Processor Base Frequency (in MHz). |
| </span><span class="kw">pub fn </span>processor_base_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.eax, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Maximum Frequency (in MHz). |
| </span><span class="kw">pub fn </span>processor_max_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Bus (Reference) Frequency (in MHz). |
| </span><span class="kw">pub fn </span>bus_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ecx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Debug <span class="kw">for </span>ProcessorFrequencyInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| f.debug_struct(<span class="string">"ProcessorFrequencyInfo"</span>) |
| .field(<span class="string">"processor_base_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.processor_base_frequency()) |
| .field(<span class="string">"processor_max_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.processor_max_frequency()) |
| .field(<span class="string">"bus_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.bus_frequency()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Deterministic Address Translation Structure Iterator (LEAF=0x18). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[derive(Clone)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>DatIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| current: u32, |
| count: u32, |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>DatIter { |
| <span class="kw">type </span>Item = DatInfo; |
| |
| <span class="doccomment">/// Iterate over each sub-leaf with an address translation structure. |
| </span><span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><DatInfo> { |
| <span class="kw">loop </span>{ |
| <span class="comment">// Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX |
| </span><span class="kw">if </span><span class="self">self</span>.current > <span class="self">self</span>.count { |
| <span class="kw">return </span><span class="prelude-val">None</span>; |
| } |
| |
| <span class="kw">let </span>res = <span class="self">self |
| </span>.read |
| .cpuid2(EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO, <span class="self">self</span>.current); |
| <span class="self">self</span>.current += <span class="number">1</span>; |
| |
| <span class="comment">// A sub-leaf index is also invalid if EDX[4:0] returns 0. |
| </span><span class="kw">if </span>get_bits(res.edx, <span class="number">0</span>, <span class="number">4</span>) == <span class="number">0 </span>{ |
| <span class="comment">// Valid sub-leaves do not need to be contiguous or in any particular order. |
| // A valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf |
| // or than a valid sub-leaf of a higher or lower-level struc-ture |
| </span><span class="kw">continue</span>; |
| } |
| |
| <span class="kw">return </span><span class="prelude-val">Some</span>(DatInfo { |
| _eax: res.eax, |
| ebx: res.ebx, |
| ecx: res.ecx, |
| edx: res.edx, |
| }); |
| } |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>DatIter { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| <span class="kw">let </span><span class="kw-2">mut </span>debug = f.debug_list(); |
| <span class="self">self</span>.clone().for_each(|<span class="kw-2">ref </span>item| { |
| debug.entry(item); |
| }); |
| debug.finish() |
| } |
| } |
| |
| <span class="doccomment">/// Deterministic Address Translation Structure |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>DatInfo { |
| _eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>DatInfo { |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"4K page size entries supported by this structure"</span>, |
| has_4k_entries, |
| ebx, |
| <span class="number">0 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"2MB page size entries supported by this structure"</span>, |
| has_2mb_entries, |
| ebx, |
| <span class="number">1 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"4MB page size entries supported by this structure"</span>, |
| has_4mb_entries, |
| ebx, |
| <span class="number">2 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"1GB page size entries supported by this structure"</span>, |
| has_1gb_entries, |
| ebx, |
| <span class="number">3 |
| </span>); |
| |
| <span class="macro">check_bit_fn!</span>( |
| doc = <span class="string">"Fully associative structure"</span>, |
| is_fully_associative, |
| edx, |
| <span class="number">8 |
| </span>); |
| |
| <span class="doccomment">/// Partitioning (0: Soft partitioning between the logical processors sharing this structure). |
| </span><span class="kw">pub fn </span>partitioning(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">8</span>, <span class="number">10</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Ways of associativity. |
| </span><span class="kw">pub fn </span>ways(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">16</span>, <span class="number">31</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="doccomment">/// Number of Sets. |
| </span><span class="kw">pub fn </span>sets(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="doccomment">/// Translation cache type field. |
| </span><span class="kw">pub fn </span>cache_type(<span class="kw-2">&</span><span class="self">self</span>) -> DatType { |
| <span class="kw">match </span>get_bits(<span class="self">self</span>.edx, <span class="number">0</span>, <span class="number">4</span>) <span class="kw">as </span>u8 { |
| <span class="number">0b00001 </span>=> DatType::DataTLB, |
| <span class="number">0b00010 </span>=> DatType::InstructionTLB, |
| <span class="number">0b00011 </span>=> DatType::UnifiedTLB, |
| <span class="number">0b00000 </span>=> DatType::Null, <span class="comment">// should never be returned as this indicates invalid struct! |
| </span><span class="number">0b00100 </span>=> DatType::LoadOnly, |
| <span class="number">0b00101 </span>=> DatType::StoreOnly, |
| <span class="kw">_ </span>=> DatType::Unknown, |
| } |
| } |
| |
| <span class="doccomment">/// Translation cache level (starts at 1) |
| </span><span class="kw">pub fn </span>cache_level(<span class="kw-2">&</span><span class="self">self</span>) -> u8 { |
| get_bits(<span class="self">self</span>.edx, <span class="number">5</span>, <span class="number">7</span>) <span class="kw">as </span>u8 |
| } |
| |
| <span class="doccomment">/// Maximum number of addressable IDs for logical processors sharing this translation cache |
| </span><span class="kw">pub fn </span>max_addressable_ids(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| <span class="comment">// Add one to the return value to get the result: |
| </span>(get_bits(<span class="self">self</span>.edx, <span class="number">14</span>, <span class="number">25</span>) + <span class="number">1</span>) <span class="kw">as </span>u16 |
| } |
| } |
| |
| <span class="kw">impl </span>Debug <span class="kw">for </span>DatInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| f.debug_struct(<span class="string">"DatInfo"</span>) |
| .field(<span class="string">"has_4k_entries"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_4k_entries()) |
| .field(<span class="string">"has_2mb_entries"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_2mb_entries()) |
| .field(<span class="string">"has_4mb_entries"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_4mb_entries()) |
| .field(<span class="string">"has_1gb_entries"</span>, <span class="kw-2">&</span><span class="self">self</span>.has_1gb_entries()) |
| .field(<span class="string">"is_fully_associative"</span>, <span class="kw-2">&</span><span class="self">self</span>.is_fully_associative()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Deterministic Address Translation cache type (EDX bits 04 -- 00) |
| </span><span class="attribute">#[derive(Eq, PartialEq, Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub enum </span>DatType { |
| <span class="doccomment">/// Null (indicates this sub-leaf is not valid). |
| </span>Null = <span class="number">0b00000</span>, |
| DataTLB = <span class="number">0b00001</span>, |
| InstructionTLB = <span class="number">0b00010</span>, |
| <span class="doccomment">/// Some unified TLBs will allow a single TLB entry to satisfy data read/write |
| /// and instruction fetches. Others will require separate entries (e.g., one |
| /// loaded on data read/write and another loaded on an instruction fetch) . |
| /// Please see the Intel® 64 and IA-32 Architectures Optimization Reference Manual |
| /// for details of a particular product. |
| </span>UnifiedTLB = <span class="number">0b00011</span>, |
| LoadOnly = <span class="number">0b0100</span>, |
| StoreOnly = <span class="number">0b0101</span>, |
| Unknown, |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>DatType { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>Formatter<<span class="lifetime">'_</span>>) -> fmt::Result { |
| <span class="kw">let </span>t = <span class="kw">match </span><span class="self">self </span>{ |
| DatType::Null => <span class="string">"invalid (0)"</span>, |
| DatType::DataTLB => <span class="string">"Data TLB"</span>, |
| DatType::InstructionTLB => <span class="string">"Instruction TLB"</span>, |
| DatType::UnifiedTLB => <span class="string">"Unified TLB"</span>, |
| DatType::LoadOnly => <span class="string">"Load Only"</span>, |
| DatType::StoreOnly => <span class="string">"Store Only"</span>, |
| DatType::Unknown => <span class="string">"Unknown"</span>, |
| }; |
| f.write_str(t) |
| } |
| } |
| |
| <span class="doccomment">/// SoC vendor specific information (LEAF=0x17). |
| /// |
| /// # Platforms |
| /// ❌ AMD ✅ Intel |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>SoCVendorInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| <span class="doccomment">/// MaxSOCID_Index |
| </span>eax: u32, |
| ebx: u32, |
| ecx: u32, |
| edx: u32, |
| } |
| |
| <span class="kw">impl </span>SoCVendorInfo { |
| <span class="kw">pub fn </span>get_soc_vendor_id(<span class="kw-2">&</span><span class="self">self</span>) -> u16 { |
| get_bits(<span class="self">self</span>.ebx, <span class="number">0</span>, <span class="number">15</span>) <span class="kw">as </span>u16 |
| } |
| |
| <span class="kw">pub fn </span>get_project_id(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.ecx |
| } |
| |
| <span class="kw">pub fn </span>get_stepping_id(<span class="kw-2">&</span><span class="self">self</span>) -> u32 { |
| <span class="self">self</span>.edx |
| } |
| |
| <span class="kw">pub fn </span>get_vendor_brand(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SoCVendorBrand> { |
| <span class="comment">// Leaf 17H is valid if MaxSOCID_Index >= 3. |
| </span><span class="kw">if </span><span class="self">self</span>.eax >= <span class="number">3 </span>{ |
| <span class="kw">let </span>r1 = <span class="self">self</span>.read.cpuid2(EAX_SOC_VENDOR_INFO, <span class="number">1</span>); |
| <span class="kw">let </span>r2 = <span class="self">self</span>.read.cpuid2(EAX_SOC_VENDOR_INFO, <span class="number">2</span>); |
| <span class="kw">let </span>r3 = <span class="self">self</span>.read.cpuid2(EAX_SOC_VENDOR_INFO, <span class="number">3</span>); |
| <span class="prelude-val">Some</span>(SoCVendorBrand { data: [r1, r2, r3] }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="kw">pub fn </span>get_vendor_attributes(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><SoCVendorAttributesIter> { |
| <span class="kw">if </span><span class="self">self</span>.eax > <span class="number">3 </span>{ |
| <span class="prelude-val">Some</span>(SoCVendorAttributesIter { |
| read: <span class="self">self</span>.read, |
| count: <span class="self">self</span>.eax, |
| current: <span class="number">3</span>, |
| }) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Debug <span class="kw">for </span>SoCVendorInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| f.debug_struct(<span class="string">"SoCVendorInfo"</span>) |
| .field(<span class="string">"soc_vendor_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_soc_vendor_id()) |
| .field(<span class="string">"project_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_project_id()) |
| .field(<span class="string">"stepping_id"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_stepping_id()) |
| .field(<span class="string">"vendor_brand"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_vendor_brand()) |
| .field(<span class="string">"vendor_attributes"</span>, <span class="kw-2">&</span><span class="self">self</span>.get_vendor_attributes()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Iterator for SoC vendor attributes. |
| </span><span class="attribute">#[derive(Debug)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>SoCVendorAttributesIter { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| count: u32, |
| current: u32, |
| } |
| |
| <span class="kw">impl </span>Iterator <span class="kw">for </span>SoCVendorAttributesIter { |
| <span class="kw">type </span>Item = CpuIdResult; |
| |
| <span class="doccomment">/// Iterate over all SoC vendor specific attributes. |
| </span><span class="kw">fn </span>next(<span class="kw-2">&mut </span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><CpuIdResult> { |
| <span class="kw">if </span><span class="self">self</span>.current > <span class="self">self</span>.count { |
| <span class="kw">return </span><span class="prelude-val">None</span>; |
| } |
| <span class="self">self</span>.count += <span class="number">1</span>; |
| <span class="prelude-val">Some</span>(<span class="self">self</span>.read.cpuid2(EAX_SOC_VENDOR_INFO, <span class="self">self</span>.count)) |
| } |
| } |
| |
| <span class="doccomment">/// A vendor brand string as queried from the cpuid leaf. |
| </span><span class="attribute">#[derive(Debug, PartialEq, Eq)] |
| #[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| #[repr(C)] |
| </span><span class="kw">pub struct </span>SoCVendorBrand { |
| data: [CpuIdResult; <span class="number">3</span>], |
| } |
| |
| <span class="kw">impl </span>SoCVendorBrand { |
| <span class="doccomment">/// Return the SocVendorBrand as a string. |
| </span><span class="kw">pub fn </span>as_str(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>str { |
| <span class="kw">let </span>brand_string_start = <span class="self">self </span><span class="kw">as </span><span class="kw-2">*const </span>SoCVendorBrand <span class="kw">as </span><span class="kw-2">*const </span>u8; |
| <span class="kw">let </span>slice = <span class="kw">unsafe </span>{ |
| <span class="comment">// Safety: SoCVendorBrand is laid out with repr(C). |
| </span>slice::from_raw_parts(brand_string_start, size_of::<SoCVendorBrand>()) |
| }; |
| str::from_utf8(slice).unwrap_or(<span class="string">"InvalidSoCVendorString"</span>) |
| } |
| |
| <span class="attribute">#[deprecated( |
| since = <span class="string">"10.0.0"</span>, |
| note = <span class="string">"Use idiomatic function name `as_str` instead" |
| </span>)] |
| </span><span class="kw">pub fn </span>as_string(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>str { |
| <span class="self">self</span>.as_str() |
| } |
| } |
| |
| <span class="kw">impl </span>fmt::Display <span class="kw">for </span>SoCVendorBrand { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| <span class="macro">write!</span>(f, <span class="string">"{}"</span>, <span class="self">self</span>.as_str()) |
| } |
| } |
| |
| <span class="doccomment">/// Information about Hypervisor (LEAF=0x4000_0001) |
| /// |
| /// More information about this semi-official leaf can be found here |
| /// <https://lwn.net/Articles/301888/> |
| </span><span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, derive(Serialize, Deserialize))] |
| </span><span class="kw">pub struct </span>HypervisorInfo { |
| <span class="attribute">#[cfg_attr(feature = <span class="string">"serialize"</span>, serde(skip))] |
| </span>read: CpuIdReader, |
| res: CpuIdResult, |
| } |
| |
| <span class="kw">impl </span>fmt::Debug <span class="kw">for </span>HypervisorInfo { |
| <span class="kw">fn </span>fmt(<span class="kw-2">&</span><span class="self">self</span>, f: <span class="kw-2">&mut </span>fmt::Formatter) -> fmt::Result { |
| f.debug_struct(<span class="string">"HypervisorInfo"</span>) |
| .field(<span class="string">"identify"</span>, <span class="kw-2">&</span><span class="self">self</span>.identify()) |
| .field(<span class="string">"tsc_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.tsc_frequency()) |
| .field(<span class="string">"apic_frequency"</span>, <span class="kw-2">&</span><span class="self">self</span>.apic_frequency()) |
| .finish() |
| } |
| } |
| |
| <span class="doccomment">/// Identifies the different Hypervisor products. |
| </span><span class="attribute">#[derive(Debug, Eq, PartialEq)] |
| </span><span class="kw">pub enum </span>Hypervisor { |
| Xen, |
| VMware, |
| HyperV, |
| KVM, |
| <span class="doccomment">/// QEMU is the hypervisor identity when QEMU is used |
| /// without an accelerator, such as KVM. |
| </span>QEMU, |
| Bhyve, |
| QNX, |
| ACRN, |
| Unknown(u32, u32, u32), |
| } |
| |
| <span class="kw">impl </span>HypervisorInfo { |
| <span class="doccomment">/// Returns the identity of the [`Hypervisor`]. |
| /// |
| /// ## Technical Background |
| /// |
| /// The value is a 12-byte (12 character) fixed-length ASCII string. |
| /// |
| /// Usually all of these IDs can be found in the original source code on |
| /// Github relatively easy (if the project is open source). Once you |
| /// have an ID, you find cumulated lists with all kinds of IDs on Github |
| /// relatively easy. |
| </span><span class="kw">pub fn </span>identify(<span class="kw-2">&</span><span class="self">self</span>) -> Hypervisor { |
| <span class="kw">match </span>(<span class="self">self</span>.res.ebx, <span class="self">self</span>.res.ecx, <span class="self">self</span>.res.edx) { |
| <span class="comment">// "VMwareVMware" (0x56 => V, 0x4d => M, ...) |
| </span>(<span class="number">0x61774d56</span>, <span class="number">0x4d566572</span>, <span class="number">0x65726177</span>) => Hypervisor::VMware, |
| <span class="comment">// "XenVMMXenVMM" |
| </span>(<span class="number">0x566e6558</span>, <span class="number">0x65584d4d</span>, <span class="number">0x4d4d566e</span>) => Hypervisor::Xen, |
| <span class="comment">// "Microsoft Hv" |
| </span>(<span class="number">0x7263694d</span>, <span class="number">0x666f736f</span>, <span class="number">0x76482074</span>) => Hypervisor::HyperV, |
| <span class="comment">// "KVMKVMKVM\0\0\0" |
| </span>(<span class="number">0x4b4d564b</span>, <span class="number">0x564b4d56</span>, <span class="number">0x0000004d</span>) => Hypervisor::KVM, |
| <span class="comment">// "TCGTCGTCGTCG" |
| // see https://github.com/qemu/qemu/blob/6512fa497c2fa9751b9d774ab32d87a9764d1958/target/i386/cpu.c |
| </span>(<span class="number">0x54474354</span>, <span class="number">0x43544743</span>, <span class="number">0x47435447</span>) => Hypervisor::QEMU, |
| <span class="comment">// "bhyve bhyve " |
| // found this in another library ("heim-virt") |
| </span>(<span class="number">0x76796862</span>, <span class="number">0x68622065</span>, <span class="number">0x20657679</span>) => Hypervisor::Bhyve, |
| <span class="comment">// "BHyVE BHyVE " |
| // But this value is in the original source code. To be safe, we keep both. |
| // See https://github.com/lattera/bhyve/blob/5946a9115d2771a1d27f14a835c7fbc05b30f7f9/sys/amd64/vmm/x86.c#L165 |
| </span>(<span class="number">0x56794842</span>, <span class="number">0x48422045</span>, <span class="number">0x20455679</span>) => Hypervisor::Bhyve, |
| <span class="comment">// "QNXQVMBSQG" |
| // This can be verified in multiple Git repos (e.g. by Intel) |
| // https://github.com/search?q=QNXQVMBSQG&type=code |
| </span>(<span class="number">0x51584e51</span>, <span class="number">0x53424d56</span>, <span class="number">0x00004751</span>) => Hypervisor::QNX, |
| <span class="comment">// "ACRNACRNACRN" |
| </span>(<span class="number">0x4e524341</span>, <span class="number">0x4e524341</span>, <span class="number">0x4e524341</span>) => Hypervisor::ACRN, |
| (ebx, ecx, edx) => Hypervisor::Unknown(ebx, ecx, edx), |
| } |
| } |
| |
| <span class="doccomment">/// TSC frequency in kHz. |
| </span><span class="kw">pub fn </span>tsc_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><u32> { |
| <span class="comment">// vm aware tsc frequency retrieval: |
| // # EAX: (Virtual) TSC frequency in kHz. |
| </span><span class="kw">if </span><span class="self">self</span>.res.eax >= <span class="number">0x40000010 </span>{ |
| <span class="kw">let </span>virt_tinfo = <span class="self">self</span>.read.cpuid2(<span class="number">0x40000010</span>, <span class="number">0</span>); |
| <span class="prelude-val">Some</span>(virt_tinfo.eax) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| |
| <span class="doccomment">/// (Virtual) Bus (local apic timer) frequency in kHz. |
| </span><span class="kw">pub fn </span>apic_frequency(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="prelude-ty">Option</span><u32> { |
| <span class="comment">// # EBX: (Virtual) Bus (local apic timer) frequency in kHz. |
| </span><span class="kw">if </span><span class="self">self</span>.res.eax >= <span class="number">0x40000010 </span>{ |
| <span class="kw">let </span>virt_tinfo = <span class="self">self</span>.read.cpuid2(<span class="number">0x40000010</span>, <span class="number">0</span>); |
| <span class="prelude-val">Some</span>(virt_tinfo.ebx) |
| } <span class="kw">else </span>{ |
| <span class="prelude-val">None |
| </span>} |
| } |
| } |
| |
| <span class="attribute">#[cfg(doctest)] |
| </span><span class="kw">mod </span>test_readme { |
| <span class="macro">macro_rules! </span>external_doc_test { |
| (<span class="macro-nonterminal">$x</span>:expr) => { |
| <span class="attribute">#[doc = <span class="macro-nonterminal">$x</span>] |
| </span><span class="kw">extern </span><span class="string">"C" </span>{} |
| }; |
| } |
| |
| <span class="macro">external_doc_test!</span>(<span class="macro">include_str!</span>(<span class="string">"../README.md"</span>)); |
| } |
| </code></pre></div> |
| </section></div></main><div id="rustdoc-vars" data-root-path="../../" data-current-crate="raw_cpuid" data-themes="ayu,dark,light" data-resource-suffix="" data-rustdoc-version="1.66.0-nightly (5c8bff74b 2022-10-21)" ></div></body></html> |
