)]}' { "log": [ { "commit": "d4a15f627d5cc9762a82270d1be60a136e6af9c2", "tree": "f5cd9d381148994bdd44a133d5a50109de3d8713", "parents": [ "36a91576edf633479c78649e050f18dd2ddc8103" ], "author": { "name": "Kevin Laeufer", "email": "laeufer@cs.berkeley.edu", "time": "Thu Jan 27 13:25:39 2022 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jan 27 13:25:39 2022 -0800" }, "message": "Port to new Chisel stable release (3.5) (#37)\n\n* upgrade to stable chisel 3.5.0\r\n\r\n* fix chiesl 3.5 warnings\r\n\r\n* port tests to chiseltest\r\n\r\n* change chisel hardware makefile to use sbt test to run unittests" }, { "commit": "36a91576edf633479c78649e050f18dd2ddc8103", "tree": "055e1bc8ab88ca73ce415e693d0507c285898d11", "parents": [ "5b5375729dab081bff1f4afb929a3d94784200b5" ], "author": { "name": "Anton Sorokin", "email": "anton.a.sorokin@intel.com", "time": "Wed Sep 08 18:10:14 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 08 18:10:14 2021 -0700" }, "message": "VTA Chisel Wide memory interface. (#32)\n\n* VTA Chisel Wide memory interface.\r\n* Added SyncQueue with tests - Implementation uses sync memory to implement larger queues.\r\n* AXI 64/128/256/512 data bits support by AXIParams-\u003edataBits\r\n A wide implementation of load/store is used when AXI interface data width\r\n is larger than number of bits in a tesor.\r\n Instructions are stored as 64bit tensors to allow 64bit address alignment\r\n* TensorLoad is modified to replace all VME load operations.\r\n Multiple simultaneous requests can be generated. Load is pipelined\r\n and separated from request generation.\r\n* TensorStore -\u003e TensorStoreNarrowVME TensorStoreWideVME. The narrow one is the original one\r\n* TensorLoad -\u003e TensorLoadSimple (original) TensorLoadWideVME TensorStoreNarrowVME\r\n* LoadUop -\u003e LoadUopSimple is the original one. The new one is based on TensorLoad\r\n* Fetch -\u003e FetchVME64 FetchWideVME. Reuse communication part from TensorLoad.\r\n* DPI intreface changed to transfer more than 64bit. svOpenArrayHandle is used. tsim library compilation now requires verilator\r\n* Compute is changed to use TensorLoad style of load uop.\r\n* VME changed to generate/queue/respond to multiple simultaneous load requests\r\n\r\n* code formatting fix\r\n\r\n* Update to Chisel 3.4.3 PR Port to the latest stable Chisel release (#33)\r\n* Fix Makefile to use Chisel -o instead of top name and .sv instead of .v\r\n* fix reset to reset.asBool\r\n* fix SyncQueue to deprecated module.io\r\n* fix toBools to asBools\r\n\r\n* include Verialted.cpp verilated_dpi.cpp directly in module.cc to provide verilator array acces fuctionality and avoid compilation warnings\r\n\r\n* fix module io warnings\r\n\r\n* comments\r\n\r\n* Jenkinsfile ci pipeline fix\r\n\r\n* Jenkinsfile ci pipeline fix. only for lint,cpu,i386\r\n\r\n* Reenable tsim tests\r\n\r\n* style fix\r\n\r\n* comments cleanup\r\n\r\n* AXI constants commented. Moved write id to VME\r\n\r\n* comments cleanup\r\n\r\n* comments cleanup" }, { "commit": "5b5375729dab081bff1f4afb929a3d94784200b5", "tree": "ddfe8efaacbcf7eed41d37093bdeeb08d4007878", "parents": [ "981bf2f32729b37b2ad302052d6c74c3734a17c9" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Tue Aug 31 11:27:24 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Aug 31 11:27:24 2021 -0700" }, "message": "update ci files (#36)\n\n" }, { "commit": "981bf2f32729b37b2ad302052d6c74c3734a17c9", "tree": "a5c5d5bb85f5e273a0074f624d9347f774bdb173", "parents": [ "3ec5f21a3c962c559d38f84a02a2ad15908664b4" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Sun Aug 22 18:37:22 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Aug 22 18:37:22 2021 -0700" }, "message": "fix types (#34)\n\n" }, { "commit": "3ec5f21a3c962c559d38f84a02a2ad15908664b4", "tree": "abf8ba5a9b2a8e7d19cb6c79b4dce0836ae07c78", "parents": [ "4f7d2497c1655354f23c108d120c4ba030244d80" ], "author": { "name": "Kevin Laeufer", "email": "electron.kiwi@gmail.com", "time": "Thu Aug 19 18:35:44 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Aug 19 18:35:44 2021 -0700" }, "message": "Port to the latest stable Chisel release (#33)\n\n* modernize build.sbt\r\n\r\n* fix some imports\r\n\r\n* ignore target directory generated by sbt\r\n\r\n* TensorGemm: explicitly define adder interface\r\n\r\n* use ChiselStage instead of Driver\r\n\r\n* setResource is now addResource\r\n\r\n* add toInt in order to fix warning" }, { "commit": "4f7d2497c1655354f23c108d120c4ba030244d80", "tree": "524a093de9ea5a108f0aaea8baa90a078765d702", "parents": [ "c18a22475d8ccb5447da4591c709d347687fb2b8" ], "author": { "name": "Lunderberg", "email": "Lunderberg@users.noreply.github.com", "time": "Thu Aug 19 15:38:44 2021 -0500" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Aug 19 13:38:44 2021 -0700" }, "message": "Renamed graph_runtime references to graph_executor. (#31)\n\nFollowing TVM\u0027s rename in https://github.com/apache/tvm/pull/7653,\r\nupdate to avoid errors when tvm.contrib.graph_runtime is removed\r\nentirely." }, { "commit": "c18a22475d8ccb5447da4591c709d347687fb2b8", "tree": "dee39349a9bea3082da0c8f27ebeed4d83986cab", "parents": [ "1954ff58264384de8241cc155ffe33829f0e616a" ], "author": { "name": "Abhijit Davare", "email": "abhijit.davare@intel.com", "time": "Tue Jun 22 18:03:09 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 23 09:03:09 2021 +0800" }, "message": "Chisel Pipelined GEMM (#30)\n\n* Reset to 644 file permissions\r\n\r\n* Add json files to src/test/resources for testing\r\n\r\n* Add new TensorGemmPipelinedSplit module and rename existing TensorGemm to TensorGemmOrig\r\n\r\n* Tests for TensorGemmPipelinedSplit, TensorGemmOrig, and associated submodules\r\n\r\n* Add jackson plugin dependency and stricter Scala checks\r\n\r\n* Remove debug prints\r\n\r\n* Rename x.json and y.json to gemm_1uop_overflow_offset.json and gemm_2uop_overflow_cascaded.json respectively\r\n\r\n* All occurrences of \u0027\\( \u0027 replaced with \u0027\\(\u0027\r\n\r\n* Add linting rule to flag spaces after lparen characters\r\n\r\n* Remove comment\r\n\r\n* Rename TensorGemmOrig to TensorGemmSimple" }, { "commit": "1954ff58264384de8241cc155ffe33829f0e616a", "tree": "44eb07b749b53fbe7e0a0f70342b31d6bf1c0fd6", "parents": [ "d5e8117ce1535c527c536e115b4e58d53817b82f" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Tue Jun 08 17:07:35 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 08 17:07:35 2021 -0700" }, "message": "add unittest (#29)\n\n" }, { "commit": "d5e8117ce1535c527c536e115b4e58d53817b82f", "tree": "0f4ac9aaed6758f245d02abaf7adb56d02f6dfa5", "parents": [ "74f23fff285d4f57cad4afdb05e2bff08fd71f98" ], "author": { "name": "Abhijit Davare", "email": "abhijit.davare@intel.com", "time": "Mon Jun 07 18:26:41 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 07 18:26:41 2021 -0700" }, "message": "Chisel Pipelined ALU (#27)\n\n* Remove parameter values from case class\r\n\r\n* Add new blockOutFactor parameter with default value \u003d 1\r\n\r\n* Support split access\r\n\r\n* Modify to support split interface, minor refactoring\r\n\r\n* Use split read/write intefaces\r\n\r\n* Pipelined ALU with split interfaces\r\n\r\n* Modify instantiation and usage of pipelined ALU and split interfaces\r\n\r\n* Don\u0027t use internal Random by default\r\n\r\n* Change tester name\r\n\r\n* Add generic tester class\r\n\r\n* Derive from GenericTest, minor refactoring\r\n\r\n* Test ALU index generator and pipelined ALU\r\n\r\n* Add ASF header\r\n\r\n* Bugfix: delay slicing index by a cycle to match SyncReadMem read delay\r\n\r\n* Formatting, comment, and minor refactoring changes for clarity\r\n\r\n* Fix scalastyle issues for test files" }, { "commit": "74f23fff285d4f57cad4afdb05e2bff08fd71f98", "tree": "e73b47192130ba538c5c2c9dd86be2b7f01876f6", "parents": [ "dfe9f572a43d41e0c1ecdf036cea97042a0febfe" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Mon Jun 07 13:31:14 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 07 13:31:14 2021 -0700" }, "message": "add scalastyle to test (#28)\n\n" }, { "commit": "dfe9f572a43d41e0c1ecdf036cea97042a0febfe", "tree": "ef4cc87f5a994a38d15bbff4694bfea5f2d26ef3", "parents": [ "43194178b4e570a5f1dd4f3f9d37ee16fc1b65be" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Mon May 03 09:36:01 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon May 03 09:36:01 2021 -0700" }, "message": "[App][Verilator] change scalar add to parametric-vector-add (#26)\n\n* refactor verilator app\r\n\r\n* update makefile variable" }, { "commit": "43194178b4e570a5f1dd4f3f9d37ee16fc1b65be", "tree": "22c31bd87869a4ae994237aaafa4e7fe858db782", "parents": [ "b61fe1329cd7813852de443c525f6aa99b32df3a" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Sat Apr 17 09:43:52 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Apr 17 09:43:52 2021 -0700" }, "message": "adapt chisel impl to new VTA ISA (#24)\n\n* adapt chisel impl to new VTA ISA\r\n\r\n* add comment\r\n\r\n* rename variable\r\n\r\n* update comment\r\n\r\n* remove comment" }, { "commit": "b61fe1329cd7813852de443c525f6aa99b32df3a", "tree": "762ffdda2d37a99de4b8d72cd164ebcb8df701fd", "parents": [ "f11ca65fb23d37d50bc214e149f4bdd9722cb3eb" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Fri Apr 16 14:50:41 2021 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Apr 16 11:50:41 2021 -0700" }, "message": "[CI] Fix build on main (#25)\n\n* [CI] Fix build on main\r\n\r\n* Increase jenkins timeout" }, { "commit": "f11ca65fb23d37d50bc214e149f4bdd9722cb3eb", "tree": "4aae689c8eb0d3cb66494cd5f7586561769d8a32", "parents": [ "f187a39f273961b1c2acc52088cc0a2305e5b247" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Thu Mar 18 13:44:32 2021 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 18 16:44:32 2021 -0400" }, "message": "Use TVMArrayCopyFromBytes API to replace VTA internal function VTABufferCPUPtr (#23)\n\nIssue:\r\nCurrent vta deploy example directly use VTABufferCPUPtr function to\r\naccess VTA memory, this method may have issue once the VTA memory need\r\ncache flush/invalide and such logic not leverage VTA runtime memory\r\nmovement logic which can default handle cache related issue.\r\n\r\nSolution:\r\nVTA runtime already implemented memory copy logic which integrate with\r\nTVMArrayCopy* API and here we use TVMArrayCopyFromBytes function replace this\r\nVTABufferCPUPtr function." }, { "commit": "f187a39f273961b1c2acc52088cc0a2305e5b247", "tree": "e7b3d792cd34ff2ae261fe4ea403cf245ac85578", "parents": [ "5bd9c6a8b487234e18069c887b3f6271c97292f7" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Thu Mar 11 06:41:04 2021 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 11 09:41:04 2021 -0500" }, "message": "Make VTA C++ Deploy Compatible with latest TVM. (#22)\n\nIssue:\r\nc++ deployment get broken after recently TVM change,\r\nfirst issue is lastest TVM use some c++14 feature in\r\nheader file that caused current compile fail.\r\n\r\nsecond issue is lastest TVM did more strict format/type\r\ncheck that make the restnet export logic failed.\r\n\r\nSolution:\r\nFix the said issue to make logic work." }, { "commit": "5bd9c6a8b487234e18069c887b3f6271c97292f7", "tree": "d161f3682f5f945a4a4d930e65f113b3e191d125", "parents": [ "57db5a718c74a788c98120ebbe1230797be698c8" ], "author": { "name": "ZHANG Hao", "email": "zhanghao@4paradigm.com", "time": "Fri Dec 11 10:12:58 2020 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Dec 10 18:12:58 2020 -0800" }, "message": "[Hardware][OpenCL] Intelfocl support (#9)\n\n* - static auto-tune sample config\r\n- add mul, load_int8\r\n- some bugfix for bits width\r\n\r\n* Extract hw_spec_const.h out of hw_spec.h\r\nRename VTA_MEM_ID_ACC_8 to VTA_MEM_ID_ACC_8BIT\r\n\r\n* Add OpenCL kernel sources for Intel OpenCL for FPGA devices\r\n\r\n* Add driver sources to support Intel OpenCL for FPGA devices\r\n\r\n* intelfocl sample configuration for VTA added\r\n\r\n* Workaround for Signedness bug in Intel OpenCL for FPGA compiler\r\n\r\n* remove some comments\r\n\r\n* rename cpp to cc\r\n\r\n* change UOP src_idx size to max(inp, acc)\r\n\r\n* Move AOCLUtils into 3rdpary directory on TVM\r\n\r\n* bump the intelfocl HW_VER to 0.0.2\r\n\r\n* Bump all the HW_VER to 0.0.2 as there is a ISA change\r\n\r\n* Address cpplint issues\r\n\r\n* Fix cpplint errors for indentations\r\n\r\n* api to init device from outside\r\n\r\n* Split OpenCL init and FPGA setup code\r\n\r\n* Add comment for cleanup() callback\r\n\r\n* Assert error for unsupported input/weight/accu types\r\n\r\n* Add Apache Software Foundation headers\r\n\r\n* Address cpplint issues\r\n\r\n* Drop dependency on 3rd party library aoclutils, preparing for Xilinx support\r\n\r\n* Xilinx Vitis does not allow local_work_size to be omitted\r\n\r\n* Suppress warnings for deprecated clCreateCommandQueue\r\n(clCreateCommandQueueWithProperties not supported by Xilinx)\r\n\r\n* Rename intelfocl_ to oclfpga_ as both Intel \u0026 Xilinx are supported\r\n\r\n* Rename string literals and code structures for Xilinx Vitis support\r\n\r\n* Rename aocx to bitstream as part of Xilinx Vitis support\r\n\r\n* Remove obsolete vta-cost python script\r\n\r\n* Add comments for MEM_ADDR_IDENTIFIER constant\r\n\r\n* Apply CamelCase for function names\r\n\r\n* Add comments for OCLFPGADevice member functions\r\n\r\n* 2-space indentation for .cl files\r\n\r\n* Add README to hardware/intelfocl\r\n\r\n* Update README.rst\r\n\r\n* Update README.rst\r\n\r\n* update to trigger ci\r\n\r\n* disable tsim test: quick fix for test fails due to ISA changes\r\n\r\n* TESTING\r\n\r\n* disable tsim test in docker_bash.sh\r\n\r\n* cleanup code\r\n\r\nCo-authored-by: Li Jiashu \u003clijiashu@4paradigm\u003e" }, { "commit": "57db5a718c74a788c98120ebbe1230797be698c8", "tree": "99f836abad4792c005fa7fe77709fed3134b2b7c", "parents": [ "6096ca0a88191f0d2b31d2131c95c491a01e7f62" ], "author": { "name": "Daniel Steger", "email": "dstegs@gmail.com", "time": "Wed Dec 09 19:34:15 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Dec 10 11:34:15 2020 +0800" }, "message": "Enable Supported Xilinx target ZCU104 with Hardware Preset (#20)\n\n* targets: Added zcu104 vta target\r\n\r\nThis commit adds support for the Xilinx zcu104 development board.\r\nCurrently, TVM-VTA does not support a production board thus this\r\ncommit. Leveraging a supported board which is integrated into vivado\r\nprovides board presets properly configuring peripherals and IO for\r\ndevelopment. This means that the project can be used for further\r\nbsp development using the xsa.\r\n\r\n* scripts: Enable applying board preset in vivado\r\n\r\nEnable fpga_board and fpga_board_ver properties for\r\nXilinx Platforms. This enables the hardware project to\r\nproduce a usable xsa which contains the board presets.\r\nThe board preset contains board specific config such as\r\nIO/PS/DDR settings.\r\n\r\nThe end goal of this commit is to allow the output products\r\nof TVM-VTA to be used in bsp creation and.. produce more\r\nmeaningful output products." }, { "commit": "6096ca0a88191f0d2b31d2131c95c491a01e7f62", "tree": "52fbe696161429c7f0ed59d6e3a840b8ecf7d2e9", "parents": [ "9a23bc8adf6fd41b53759d564a153e0f0947cdc2" ], "author": { "name": "Daniel Steger", "email": "dstegs@gmail.com", "time": "Fri Dec 04 10:48:16 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 04 10:48:16 2020 -0800" }, "message": "vta: Update VTA to use load_pad_2d in compute (#17)\n\nUpdate compute instruction VTA_MEM_ID_ACC to load using\r\nthe load_pad_2d method instead of the load_2d. This resolves\r\nfailing unit testing test_padded_load()." }, { "commit": "9a23bc8adf6fd41b53759d564a153e0f0947cdc2", "tree": "953293fdb175b5362cb8d6e30879c51f35a8b6c7", "parents": [ "12fb486a491b75d70ec4c5e0a0cd112ab49a95bc" ], "author": { "name": "Daniel Steger", "email": "dstegs@gmail.com", "time": "Fri Dec 04 07:23:33 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 04 10:23:33 2020 -0500" }, "message": "config: small spelling fix (#19)\n\n" }, { "commit": "12fb486a491b75d70ec4c5e0a0cd112ab49a95bc", "tree": "b6882845ace5830bb10ef23be9f6a4bf693a468b", "parents": [ "519263cc45de40449702fd7942fa0a745297180f" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Fri Nov 27 11:31:04 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 27 11:31:04 2020 -0800" }, "message": "[Hardware][Verilator] Integrating and simulating hardware accelerators in TVM (#18)\n\n* add files\r\n\r\n* fix paths\r\n\r\n* add apache header to readme" }, { "commit": "519263cc45de40449702fd7942fa0a745297180f", "tree": "1ccd35dc310f585b21b1f6f01aa4ab51d481dd79", "parents": [ "ce8efad0312b6ab55319f96b9512bcda4b19a234" ], "author": { "name": "Daniel Steger", "email": "dstegs@gmail.com", "time": "Wed Nov 25 12:03:34 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Nov 25 12:03:34 2020 -0800" }, "message": "scripts: update processor core ip version (#15)\n\n" }, { "commit": "ce8efad0312b6ab55319f96b9512bcda4b19a234", "tree": "0581f1d03ab1f8d7c9738381ff86c59c396fa39c", "parents": [ "66e0a7281d6e458ebc872d354e695d8e061bc6a7" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Nov 24 14:40:45 2020 -0500" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 24 14:40:45 2020 -0500" }, "message": "Update to reflect repo name change (#16)\n\n" }, { "commit": "66e0a7281d6e458ebc872d354e695d8e061bc6a7", "tree": "084227abd737188c1290fe47c851ee46f73b531e", "parents": [ "5e9c9f5e3cd7ac06ac3fe7360a6ff874cb308264" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Nov 03 20:56:58 2020 -0500" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 03 20:56:58 2020 -0500" }, "message": "[SETUP] branch protection setup (#14)\n\n" }, { "commit": "5e9c9f5e3cd7ac06ac3fe7360a6ff874cb308264", "tree": "8c896fc2afd32b6180504243d1b3efffe0242026", "parents": [ "1454c96232a15f7b9d9ad800969d82fc59ab02be" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Nov 03 20:45:19 2020 -0500" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 03 20:45:19 2020 -0500" }, "message": "Update git branch and links (#13)\n\n" }, { "commit": "1454c96232a15f7b9d9ad800969d82fc59ab02be", "tree": "684cae39e28d7a3e632f9b9cbbf2bcf7533ccca8", "parents": [ "87ce9acfae550d1a487746e9d06c2e250076e54c" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sat Sep 19 12:10:53 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Sep 19 12:10:53 2020 -0700" }, "message": "Update CI badge location (#12)\n\n" }, { "commit": "87ce9acfae550d1a487746e9d06c2e250076e54c", "tree": "1d6935656e51c00791d2c8520f576fbd87313741", "parents": [ "9b178fdb387bffc708f2448a82e85b4737239aed" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Wed Sep 16 10:24:22 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 16 10:24:22 2020 -0700" }, "message": "[Vivado] Export VTA configuration variables to TCL for hardware builds (#11)\n\n* generate tcl file for hardware tools from vta_config.py\r\n\r\n* add comment to function\r\n\r\n* remove this" }, { "commit": "9b178fdb387bffc708f2448a82e85b4737239aed", "tree": "ab6fd6f235a4d5237b29b449c396beeb9d619ddd", "parents": [ "f1c3385e2042e876c719d1b30dd90ed533c51ed7" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Wed Sep 02 11:13:11 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 02 11:13:11 2020 -0700" }, "message": "fixes for vivado 2020.1 (#10)\n\n" }, { "commit": "f1c3385e2042e876c719d1b30dd90ed533c51ed7", "tree": "e40003a08cbe23f1a66d6e64b4db80ffa3f8a14d", "parents": [ "21937a067fe0e831244766b41ae915c833ff15ba" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Wed Jun 10 17:57:43 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 17:57:43 2020 -0700" }, "message": "Add c++ and python local deploy example (#5)\n\n* add deploy example\r\n\r\n* fix pylint complain and add more information into readme.\r\n\r\n* Test deploy in xilinx FPGA board and udpate ReadMe.md\r\n\r\n* Fix python deploy bug.\r\n\r\n* add synset support and fix error report\r\n\r\n* add bitstream flash logic\r\n\r\n* address review comments.\r\n\r\n* add bitstream flash file\r\n\r\n* change file name\r\n\r\n* fix plint complain\r\n\r\n* return once no input parameter" }, { "commit": "21937a067fe0e831244766b41ae915c833ff15ba", "tree": "f085dd5abd2e232ca659029035a142f3f7904102", "parents": [ "22e4b88060d26cc4c309cbbbf6fba66770c20e5b" ], "author": { "name": "ZHANG Hao", "email": "zhanghaohit@gmail.com", "time": "Fri May 01 13:42:48 2020 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Apr 30 22:42:48 2020 -0700" }, "message": "[pynq_driver] fix device early return (#7)\n\nCo-authored-by: Zhang Hao \u003czhanghao@4paradigm.com\u003e" }, { "commit": "22e4b88060d26cc4c309cbbbf6fba66770c20e5b", "tree": "a36e5198b6112714523d9c59e515365d149b8fbf", "parents": [ "db65157208ec8fabb7b548c94596211b9db04190" ], "author": { "name": "ZHANG Hao", "email": "zhanghaohit@gmail.com", "time": "Wed Apr 29 23:57:04 2020 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Apr 29 08:57:04 2020 -0700" }, "message": "[Hardware][Xilinx] utilize uram (#6)\n\nCo-authored-by: Zhang Hao \u003czhanghao@4paradigm.com\u003e" }, { "commit": "db65157208ec8fabb7b548c94596211b9db04190", "tree": "2809cd8850f17fffced319b226a7217b9b4c8221", "parents": [ "6beda213d50ce97cc4b22d66d0aa8b7f99553104" ], "author": { "name": "ga", "email": "gaurav@kargo.com", "time": "Mon Mar 30 14:40:41 2020 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 30 11:40:41 2020 -0700" }, "message": "[xilinx] correct assert statement (#4)\n\n" }, { "commit": "6beda213d50ce97cc4b22d66d0aa8b7f99553104", "tree": "24229305d03a0c6b4469bb9fbb9fae2e56e11c92", "parents": [ "6905fc33b8fdf17ded52303ad933234a47827b76" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Mar 30 11:26:16 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 30 11:26:16 2020 -0700" }, "message": "[CI] Add vta path to cpptest (#3)\n\n* [CI] Add vta path to cpptest\r\n\r\n* [DOCS] Points docs to the ASF site" }, { "commit": "6905fc33b8fdf17ded52303ad933234a47827b76", "tree": "d49f39c3db6bd8430de9650d0641e37fd44608ac", "parents": [ "401a5328f13e6fc699e227701e0404b37a19b6cd" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Mar 30 09:44:32 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 30 09:44:32 2020 -0700" }, "message": "Update ASF yaml (#2)\n\n* Update ASF yaml\r\n\r\n* Update lint script" }, { "commit": "401a5328f13e6fc699e227701e0404b37a19b6cd", "tree": "12c4f2fc0230bcf7f1006fda74153ae84c94e714", "parents": [ "37e05a131c18ab5ec7a6b03f96e606e0e7f942ca" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Mar 29 22:02:17 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Mar 29 22:02:17 2020 -0700" }, "message": "[CI] Add build status badge (#1)\n\n" }, { "commit": "37e05a131c18ab5ec7a6b03f96e606e0e7f942ca", "tree": "ae792955ed051f91eed2a846181d0cd42bd79789", "parents": [ "b097f0143c30c3126d41f35df4d5be197561af11" ], "author": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Sun Mar 29 18:06:20 2020 -0700" }, "committer": { "name": "tqchen", "email": "tqchenml@gmail.com", "time": "Sun Mar 29 20:46:55 2020 -0700" }, "message": "[CI] Setup VTA CI\n" }, { "commit": "b097f0143c30c3126d41f35df4d5be197561af11", "tree": "3ee5203e792c38300cd4212f7772795cf42bb452", "parents": [ "ed30d7b3461793feb579f0a2072d1b53df34553b" ], "author": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Sun Mar 29 16:57:20 2020 -0700" }, "committer": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Sun Mar 29 18:21:04 2020 -0700" }, "message": "[REFACTOR] VTA-HW setup\n" }, { "commit": "ed30d7b3461793feb579f0a2072d1b53df34553b", "tree": "ec46890d1e8c01c2ec9016cf42a1860fb433a78a", "parents": [ "36828b8daab5f8fecdf9d51a5065116384b22b4e" ], "author": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Sun Mar 29 18:20:35 2020 -0700" }, "committer": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Sun Mar 29 18:21:04 2020 -0700" }, "message": "License notice\n" }, { "commit": "36828b8daab5f8fecdf9d51a5065116384b22b4e", "tree": "4354d12184d8b8d8507413be93bd1ef0aa92edd1", "parents": [ "48fa54b6ecc3f2cee425401f054a54257fb30537" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sat Mar 28 22:33:38 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Mar 28 22:33:38 2020 -0700" }, "message": "[BUILD] Fix VTA build in CI (#5165)\n\n" }, { "commit": "48fa54b6ecc3f2cee425401f054a54257fb30537", "tree": "cb197802a4fa9b5b592a7e6b6d9cea2eb553e878", "parents": [ "66223ef1ee04237485058343a4791991b7aecda8" ], "author": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Sat Mar 28 17:26:40 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Mar 28 17:26:40 2020 -0700" }, "message": "[VTA][Refactor] Introducing VTA_HW_PATH for easier migration (#5163)\n\n" }, { "commit": "66223ef1ee04237485058343a4791991b7aecda8", "tree": "e28360ae887126b2fa401fd872e2379a67fc0a8e", "parents": [ "40f7116bcfe503ca5908e30374c36562e8e42061" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Wed Mar 18 16:39:18 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Mar 18 16:39:18 2020 -0700" }, "message": "[TUTORIAL] Fix vta tutorial after relay function refactor (#5095)\n\n" }, { "commit": "40f7116bcfe503ca5908e30374c36562e8e42061", "tree": "129f14883c6fb4d95469db44bb92cba8de936ffa", "parents": [ "38da7912924c25dd02ae1da533d4dfa194c1eec3" ], "author": { "name": "Haichen Shen", "email": "shenhaichen@gmail.com", "time": "Thu Mar 12 10:01:22 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 12 10:01:22 2020 -0700" }, "message": "[Autotvm] Fix autotvm customized template (#5034)\n\n* init\r\n\r\n* fix template\r\n\r\n* tweak naming" }, { "commit": "38da7912924c25dd02ae1da533d4dfa194c1eec3", "tree": "f424725886c4709737843f57ae73257ba3a87c61", "parents": [ "164f3e0dc71b17121b9750c75aa9582fdafbbf57" ], "author": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Wed Mar 11 20:59:03 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Mar 11 20:59:03 2020 -0700" }, "message": "[VTA] VTA hardware/software codebase re-org (#5037)\n\n" }, { "commit": "164f3e0dc71b17121b9750c75aa9582fdafbbf57", "tree": "5d9d565ccf1eebeabba5ef831c5a1f7d02a3ec2c", "parents": [ "495428cdb77493fb94a18a82cc9f26ceda2f65f9" ], "author": { "name": "Pasquale Cocchini", "email": "61704028+pasqoc@users.noreply.github.com", "time": "Mon Mar 09 10:09:13 2020 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 09 10:09:13 2020 -0700" }, "message": "[VTA][Chisel,de10nano] Chisel fixes and de10nano support (#4986)\n\n* [VTA][de10nano] Enable user defined target frequency.\r\n\r\nIssue:\r\nThe VTA target frequency on the DE10-Nano is hardcoded to 50MHz\r\nunnecessarily limiting performance.\r\n\r\nSolution:\r\nAdd a PLL to the FPGA sub-system along with support for the\r\nselection of a user specified frequency at build time. The board\r\nsuccessfully builds and runs at 100MHz.\r\n\r\n* Added a PLL in the soc_system.tcl platform designer generator\r\n script.\r\n\r\n* Modified the Makefile to automatically set the target frequency\r\n from that specified in the pkg_config.py file.\r\n\r\n* Modified the Makefile to generate a bitstream with an RBF\r\n format that enables programming of the FPGA directly from\r\n the on-board processor. Specifically, the RBF is generated in\r\n FastParallel32 mode with compression, which corresponds to the\r\n default MSEL switch setting on the board, i.e. 01010.\r\n\r\n* Added a false path override to file set_clocks.sdc to turn off\r\n unconstrained path warnings on the VTA pulse LED.\r\n\r\n* [VTA][TSIM] Add more debug and tracing options.\r\n\r\n* Modified Makefile to change default config to DafaultDe10Config.\r\n\r\n* Added option in Makefile to produce more detailed tracing\r\n for extra observability in debugging complex scenarios.\r\n\r\n* Added option in Makefile to produce traces in FST format which\r\n are 2 orders of magnitude smaller, although much slower to\r\n generate.\r\n\r\n* Added option in Makefile to build the simulator with GCC address\r\n sanitizer.\r\n\r\n* Modified Makefile to not lint the scala code by default avoiding\r\n unintended wrong indentation. Linting should be better performed\r\n manually on a per-need basis.\r\n\r\n* [VTA][de10nano] Enable remote programming of FPGA.\r\n\r\nIssue:\r\nThe Cyclone V FPGA on board of the DE10-Nano can only be programmed\r\nusing the JTAG port, which is a limiting option for users.\r\n\r\nSolution:\r\nAdd support for the remote programming of the FPGA implementing\r\nthe FPGA programming manager protocol published in the Cyclone V\r\nuser manual.\r\n\r\n* Added file de10nano_mgr.h implementing an FPGA manager class\r\n that supports handling of control and status registers as well\r\n as a push-button option to program the FPGA. The class can be\r\n easily extended to include more registers if needed.\r\n\r\n* Used an instance of the FPGA manager to implement function\r\n VTAProgram also warning users when incompatible bitstream\r\n files are used.\r\n\r\n* Registered VTAProgram as a global function and modified\r\n the program_bitstream python class to use it.\r\n\r\n* [VTA][de10nano] Enhance de10nano runtime support.\r\n\r\nIssue:\r\nThe de10nano target has incomplete, non-working support\r\nfor runtime reconfiguration, bitstream programming, and\r\nexamples of usage.\r\n\r\nSolution:\r\nComplete runtime support for the de10nano target.\r\n\r\n* Modified VTA.cmake to comment out a default override for\r\n VTA_MAX_XFER to 21 bit wide.\r\n\r\n* Modified VTA.cmake to add needed de10nano include dirs.\r\n\r\n* Modified relevant files to support de10nano same way as\r\n other targets for VTA runtime reconfiguration and FPGA\r\n programming.\r\n\r\n* Added test_program_rpc.py example as a runtime FPGA\r\n programming example. Note that unlike the pynq target\r\n no bitstream is either downloaded or programmed when\r\n the bitstream argument is set to None.\r\n\r\n* Cosmetic changes to vta config files.\r\n\r\n* [VTA][Chisel] LoadUop FSM bug fix.\r\n\r\nIssue:\r\nThe LoadUop FSM incorrectly advances the address of the next\r\nuop to read from DRAM when the DRAM data valid bit is deasserted\r\nand asserted at the end of a read. This is caused by a mismatch\r\nin the logic of the state and output portions of the FSM.\r\nThis is one of two issues that was gating the correct operation\r\nof VTA on the DE10-Nano target.\r\n\r\nSolution:\r\nModify the logic of the output section of the FSM to include\r\na check on the DRAM read valid bit or fold the output assignemnt\r\ninto the state section.\r\n\r\n* Folded the assignemnt of the next uop address in the state\r\n section of the FSM.\r\n\r\n* [VTA][Chisel] Dynamically adjust DMA tranfer size.\r\n\r\nIssue:\r\nIn the DE10-Nano target and possibly in others, DMA transfers that\r\ncross the boundaries of memory pages result in incorrect reads and\r\nwrites from and to DRAM. When this happens depending on different\r\ninput values, VTA loads and stores exhibit incorrect results for\r\nDMA pulses at the end of a transfer. This is one of two issues that\r\nwere gating the DE10-Nano target from functioning correctly, but may\r\naffect other Chisel based targets.\r\n\r\nSolution:\r\nAdd support for dynamically adjustble DMA transfer sizes in load\r\nand store operations. For a more elegant and modular implementation\r\nthe feature can be enabled at compile time with a static constant\r\nthat can be passed as a configuration option.\r\n\r\n* Modified the load and store finite state machines to dynamically\r\n adjust the size of initial and stride DMA transfers. The feature\r\n is enabled by default by virtue of the static constant\r\n ADAPTIVE_DMA_XFER_ENABLE.\r\n\r\n* [VTA][Chisel] Improve FSIM/TSIM/FPGA xref debug.\r\n\r\nIssue:\r\nCross reference between FSIM, TSIM, and Chisel based FPGA traces\r\nis an invaluable instrument that enables fast analysis on FSIM,\r\nand analysis/debug on TSIM and FPGA, especially for complex flows\r\nlike conv2d or full inferences. Currently this cannot be done\r\neasily since a suitable reference is missing. The clock cycle\r\nevent counter cannot be used since it is undefined in FSIM and\r\nnot reliable between TSIM and FPGA because of different latencies.\r\n\r\nSolution:\r\nIntroduce a new event counter that preserves a program order across\r\nFSIM, TSIM, FPGA. We propose adding the accumulator write event\r\ncounter in the Chisel EventCounter class and a simple instrumentation\r\nin the FSIM runtime code. Note that this technique enabled finding the\r\nChisel issues reportes in the PR, which would have been otherwise\r\nfar more difficult.\r\n\r\n* Added the acc_wr_count event counter and changed interfaces\r\n accordingly.\r\n\r\n* [VTA][de10nano] Comply with linting rules.\r\n\r\n* [VTA] Appease make lint.\r\n\r\n* [VTA] Disable pylint import not top level error.\r\n\r\n* [VTA][Chisel,de10nano] Linting changes.\r\n\r\n* Use CamelCase class names.\r\n\r\n* Use C++ style C include header files.\r\n\r\n* Add comments to Chisel makefile.\r\n\r\n* [VTA][de10nano]\r\n\r\n* Reorder C and C++ includes in de10nano_mgr.h.\r\n\r\n* Restore lint as default target in Chisel Makefile.\r\n\r\n* [VTA][de10nano] Do not use f string in pkg_config.py.\r\n\r\n* [VTA][de10nano] Remove overlooked f strings in pkg_config.py.\r\n\r\n* [VTA][de10nano] Fixed typo.\r\n\r\n* [VTA][TSIM] Check if gcc has align-new.\r\n\r\n* [VTA][Chisel] Make adaptive DMA transfer default.\r\n\r\n* [VTA][RPC] Renamed VTA_PYNQ_RPC_* to VTA_RPC_*.\r\n\r\nIssue:\r\nWith more FPGA targets coming online the initial method of\r\nusing individual environment variables to specify target IP and port\r\ndoes not scale well.\r\n\r\nSolution:\r\nUse a single VTA_RPC_HOST, VTA_RPC_PORT pair to be changed\r\nevery time a different target is used. For instance in a script\r\nused to benchmark all targets.\r\n\r\n* Replaced every instance of VTA_PYNQ_RPC_HOST and VTA_PYNQ_RPC_PORT\r\n with VTA_RPC_HOST and VTA_RPC_PORT, respectively.\r\n\r\n* [VTA][Chisel] Comply with new linter." }, { "commit": "495428cdb77493fb94a18a82cc9f26ceda2f65f9", "tree": "4d085a4a4ff72dadcae740058b98fe4a76ec1c46", "parents": [ "28958c621c577f6cd21f5accecaf18126dbeefe2" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Sun Mar 08 02:42:44 2020 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Mar 07 10:42:44 2020 -0800" }, "message": "[VTA][Chisel] Change Scala Linter scalafmt \u003d\u003e scalastyle (#4998)\n\n* scalafmt \u003d\u003e scalastyle\r\n\r\nChange-Id: Ifc590e7cb63585f35dfdc9efcf3c6287b1afb1dd\r\n\r\n* scalafmt \u003d\u003e scalastyle\r\n\r\nChange-Id: I8aff2632dadda05d2896e28bdaf6f780a160a15a\r\n\r\n* add indentation constraint\r\n\r\nChange-Id: Ibeb00c11a5718ea47322ea2b82e757828af8af91\r\n\r\n* trigger ci again" }, { "commit": "28958c621c577f6cd21f5accecaf18126dbeefe2", "tree": "fdb2b7c4b877ceba560c339de11380a063ba129a", "parents": [ "23657d26a869e71bed8373ecdc90340e47ebfbec" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Thu Feb 27 14:27:37 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Feb 27 14:27:37 2020 -0800" }, "message": "[DOCS] Sphinx -- Introduce alias detection. (#4954)\n\n* [DOCS] Sphinx -- Introduce alias detection.\r\n\r\nBackground: some of our namespaces import function from another\r\nnamespace. For example tvm.te imports most of the operators from tvm.tir.\r\n\r\nPreviously we manually exclude these aliases from the doc.\r\nHowever that means we can not link them by the alias name.\r\n\r\nThis PR adds a sphinx callback plugin to detect such aliases, and create a rubric block\r\non the button of its current docstring `Alias of the original class`.\r\nIt is done in a way so that we can refer to the generated docs.\r\n\r\nWe also fixed a few docs errors.\r\n\r\n* Fix most of the issues\r\n" }, { "commit": "23657d26a869e71bed8373ecdc90340e47ebfbec", "tree": "1b133b91b624463fa0c50520b545ab8838a37d07", "parents": [ "bbe20bb347da90909c2ae9d345c2efb3481a5abd" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Wed Feb 26 21:10:47 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 26 21:10:47 2020 -0800" }, "message": "[REFACTOR][PY][API-CHANGE] Remove legacy python files. (#4943)\n\n* [REFACTOR][PY][API-CHANGE] Remove legacy python files.\r\n\r\nRemove legacy python files.\r\nUse the te namespace for most of the tensor expression primitives.\r\n\r\n- tvm.create_schedule -\u003e tvm.te.create_schedule\r\n- tvm.placeholder -\u003e tvm.te.placeholder\r\n- tvm.compute -\u003e tvm.te.compute\r\n\r\n* Remove top-level exposures.\r\n" }, { "commit": "bbe20bb347da90909c2ae9d345c2efb3481a5abd", "tree": "7fa622264a624337ac6333003c60b7d888177aba", "parents": [ "436850fe7ec6576b28b7148cf9b6548fd6ca3f7d" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Wed Feb 26 15:52:28 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 26 15:52:28 2020 -0800" }, "message": "[VTA] YoloV3 Support (#4887)\n\n* [VTA] YoloV3 Support\r\n\r\nIssue:\r\nYoloV3 use some operator and logic that not get good support by\r\nexisting vta logic, like nn.pad, upsample, and 255 output channel.\r\n\r\nSolution:\r\nadd related logic to let darknet YoloV3 can running on VTA\r\n\r\n* Fix small(0, or 1 heigh/width) detect frame issue.\r\n\r\n* add yolov3-tiny turtorial\r\n\r\n* add os import\r\n\r\n* address review comments.\r\n\r\n* rename tutorial file with a short name.\r\n\r\n* rename deploy_vision_on_vta.py into deploy_classification.py.\r\n\r\n* address review comment, fix plint eror in deploy_detection.py\r\n" }, { "commit": "436850fe7ec6576b28b7148cf9b6548fd6ca3f7d", "tree": "4b126bcd823c79de7e13a0f332a31909d28338bb", "parents": [ "7fa68ba876a304a7badd747476fbd0f1d308c674" ], "author": { "name": "Neo Chien", "email": "cchung100m@cs.ccu.edu.tw", "time": "Wed Feb 26 12:23:27 2020 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Feb 25 20:23:27 2020 -0800" }, "message": "[DOCS] Fix Sphinx Warning: the target found for cross-reference (#4925)\n\n* [DOCS] Fix Sphinx Warnings: the target found for cross-reference warnings\r\n\r\n* Fix the warning: undefined label\r\n" }, { "commit": "7fa68ba876a304a7badd747476fbd0f1d308c674", "tree": "751044d195a6d1029639f0a66677ff828274e3d5", "parents": [ "2753b8b49baf99b470075a6b8d5c0c7bf77f6a7f" ], "author": { "name": "Haichen Shen", "email": "shenhaichen@gmail.com", "time": "Mon Feb 24 13:12:03 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 24 13:12:03 2020 -0800" }, "message": "[Relay][AutoTVM] Relay op strategy (#4644)\n\n* relay op strategy\r\n\r\nfix lint\r\n\r\nbitpack strategy\r\n\r\nbitserial_dense (#6)\r\n\r\n* update strategy\r\n\r\n* address comments\r\n\r\nfix a few topi test\r\n\r\nDense strategy (#5)\r\n\r\n* dense\r\n\r\n* add biforst; remove comments\r\n\r\n* address comment\r\n\r\nRefactor x86 conv2d_NCHWc (#4)\r\n\r\n* Refactor x86 conv2d\r\n\r\n* Add x86 depthwise_conv2d_NCHWc\r\n\r\n* Add back topi x86 conv2d_nchw\r\n\r\n* Merge x86 conv2d_nchw and conv2d_NCHWc\r\n\r\n* Minor fix for x86 conv2d\r\n\r\nfix more strategy\r\n\r\nAdd x86 conv2d_NCHWc_int8 strategy (#8)\r\n\r\n* Add x86 conv2d_NCHWc_int8 strategy\r\n\r\n* Remove contrib_conv2d_nchwc_int8\r\n\r\n* Fix generic conv2d_NCHWc for int8\r\n\r\n* Fix topi arm_cpu conv2d_NCHWc_int8\r\n\r\nupdate x86 conv2d\r\n\r\nenable specify relay ops to be tuned for autotvm\r\n\r\nadd cuda conv2d strategy\r\n\r\nadd conv2d strategy for rocm\r\n\r\nadd conv2d strategy for hls\r\n\r\nadd conv2d strategy for arm cpu\r\n\r\nadd conv2d strategy for mali\r\n\r\nadd conv2d strategy for bifrost\r\n\r\nadd conv2d strategy for intel graphics\r\n\r\nclean up and fix lint\r\n\r\nremove template keys from autotvm\r\n\r\nremove 2 in the func name\r\n\r\naddress comments\r\n\r\nfix\r\n\r\n* fix bugs\r\n\r\n* lint\r\n\r\n* address comments\r\n\r\n* add name to op implement\r\n\r\n* Modify topi tests (#9)\r\n\r\n* Add pooling, reorg, softmax and vision\r\n\r\n* Add lrn\r\n\r\n* fix topi test\r\n\r\n* fix more topi test\r\n\r\n* lint\r\n\r\n* address comments\r\n\r\n* x\r\n\r\n* fix more tests \u0026 bugs\r\n\r\n* Modify more tests (#10)\r\n\r\n* Modify tests for bitserial_conv2d, bitserial_dense, bitserial_conv2d_rasp and bnn\r\n\r\n* Minor fix\r\n\r\n* More minor fix\r\n\r\n* fix more test\r\n\r\n* try to update vta using strategy\r\n\r\n* fix cpptest\r\n\r\n* x\r\n\r\n* fix rebase err\r\n\r\n* Fix two tests (#11)\r\n\r\n* change autotvm log format\r\n\r\n* lint\r\n\r\n* minor fix\r\n\r\n* try fix vta test\r\n\r\n* fix rebase err\r\n\r\n* tweak\r\n\r\n* tmp hack for vta pass\r\n\r\n* fix tutorial\r\n\r\n* fix\r\n\r\n* fix more tutorials\r\n\r\n* fix vta tutorial\r\n\r\n* minor\r\n\r\n* address comments\r\n\r\n* fix\r\n\r\n* address comments\r\n\r\n* fix cpptest\r\n\r\n* fix docs\r\n\r\n* change data structure name and api\r\n\r\n* address comments\r\n\r\n* lint\r\n\r\n* fix rebase err\r\n\r\n* updates\r\n\r\n* fix winograd test\r\n\r\n* fix doc\r\n\r\n* rebase\r\n\r\n* upgrade tophub version number\r\n\r\n* fix bug\r\n\r\n* re-enable vta tsim test after tophub is upgraded\r\n\r\n* fix vta test to use the correct args so the config can be found in tophub\r\n\r\nCo-authored-by: Yao Wang \u003ckevinthesunwy@gmail.com\u003e\r\n" }, { "commit": "2753b8b49baf99b470075a6b8d5c0c7bf77f6a7f", "tree": "7cc1810d36a267dc9e9dd93f60049730145c1f7c", "parents": [ "17fe77395141e66a2d4fe93e09e351b600caa53f" ], "author": { "name": "Cody Yu", "email": "comaniac0422@gmail.com", "time": "Thu Feb 20 14:09:34 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Feb 20 14:09:34 2020 -0800" }, "message": "[DOCS] Fix Sphinx Warnings (RST indent, cross-ref, and image scale) (#4920)\n\n* fix indents\r\n\r\n* Fix image scale and cross-ref\r\n" }, { "commit": "17fe77395141e66a2d4fe93e09e351b600caa53f", "tree": "cfd70a52e6ba021052d4fbe4338c805a19bacb43", "parents": [ "8558e4ee77a9aa104ec0397d3f9433e4a15337a3" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Feb 18 08:14:12 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Feb 18 08:14:12 2020 -0800" }, "message": "[REFACTOR][PY] Establish tvm.arith (#4904)\n\n" }, { "commit": "8558e4ee77a9aa104ec0397d3f9433e4a15337a3", "tree": "af330064a93f6c1ea650d6e4cc3f6a0005958497", "parents": [ "8bf06c3577569745128a3c1442fd80e728f82402" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Feb 17 18:47:09 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 17 18:47:09 2020 -0800" }, "message": "[REFACTOR][PY] Establish tvm.te and tvm.driver (#4900)\n\n- Move the related files to tvm.te\r\n- Move build_module.py to tvm.driver" }, { "commit": "8bf06c3577569745128a3c1442fd80e728f82402", "tree": "0ab8683e335eaa6b7fe0e5adfeca98e5b4de7b06", "parents": [ "a38b85121694e1eae5356e920e670ee39d3968eb" ], "author": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Wed Feb 12 15:38:39 2020 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Thu Feb 13 20:24:01 2020 -0800" }, "message": "[REFACTOR][PY] Establish tvm.tir\n\n- Move related files into the corresponding location as in C++\n- Keep the top-level TVM API backward compatible to make minimum changes in topi\n" }, { "commit": "a38b85121694e1eae5356e920e670ee39d3968eb", "tree": "99d24774f35cb35cff1e01ef63bc856317d4e6ba", "parents": [ "36e08acbc3c1c7fc5fe6706720920216e658cf3b" ], "author": { "name": "tqchen", "email": "tqchen@octoml.ai", "time": "Wed Feb 12 13:39:45 2020 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Wed Feb 12 16:36:23 2020 -0800" }, "message": "[REFACTOR][PY][API-CHANGE] Establish tvm.target\n\nMove the related target modules into tvm.target.\n\nAPI change:\n- tvm.target.current_target -\u003e tvm.target.Target.current\n- tvm.datatype -\u003e tvm.target.datatype\n" }, { "commit": "36e08acbc3c1c7fc5fe6706720920216e658cf3b", "tree": "2fe0b2602077ab941a74039595b4d14474a3b315", "parents": [ "651bdc4533edd6171910b065efbbfacb2b5af29a" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Feb 11 20:01:36 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Feb 11 20:01:36 2020 -0800" }, "message": "[REFACTOR][PY][API-CHANGE] establish tvm.ir, migrate corresponding files (#4862)\n\n* [REFACTOR][PY][API-CHANGE] establish tvm.ir, migrate corresponding relay files.\r\n\r\nThis PR establishes tvm.ir and migrates the corresponding relay\r\nfiles into the new folder.\r\n\r\nAPI Change:\r\n- relay.Module -\u003e tvm.IRModule\r\n\r\n* Update with ADT\r\n\r\n* Migrate transform\r\n\r\n* address comments\r\n\r\n* Migrate module\r\n\r\n* Migrate json_compact\r\n\r\n* Migrate attrs\r\n\r\n* Move LoweredFunc to stmt temporarily\r\n\r\n* temp migrate container\r\n\r\n* Finish migrate container\r\n" }, { "commit": "651bdc4533edd6171910b065efbbfacb2b5af29a", "tree": "3d2a01b3e579ded74233e2ab235a1426564351e8", "parents": [ "2614c308f6ba0a844a79e7b7ebf9ccb8e19d26ad" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sat Feb 08 19:45:17 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Feb 08 19:45:17 2020 -0800" }, "message": "[LINT][PY] Fixes for pylint\u003d\u003d2.4.4 (#4849)\n\n" }, { "commit": "2614c308f6ba0a844a79e7b7ebf9ccb8e19d26ad", "tree": "26c712eb225541c041ddabe4e385d6b205774314", "parents": [ "076cacbcb1c526161d3ba0d5f2a4e2473dfcac4e" ], "author": { "name": "Cody Yu", "email": "comaniac0422@gmail.com", "time": "Fri Feb 07 14:34:14 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Feb 07 17:34:14 2020 -0500" }, "message": "[Doc][AutoTVM] Fix bugs that override n_trials (#4842)\n\n" }, { "commit": "076cacbcb1c526161d3ba0d5f2a4e2473dfcac4e", "tree": "f9f4b5786773b09ef9fee397ca9911559378b1b0", "parents": [ "d60fb1c9a683738b877de02b7bb048fc943f76d4" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Fri Feb 07 09:15:08 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Feb 07 09:15:08 2020 -0800" }, "message": "[REFACTOR][PY][API-Change] Polish tvm.runtime, tvm.runtime.module API update (#4837)\n\n* [REFACTOR][PY-API] Polish tvm.runtime, tvm.runtime.module API update\r\n\r\nThis PR updates the tvm.runtime to use the new FFI style.\r\n\r\n- Remove top-level tvm.module to avoid confusion between runtime.Module and IRModule\r\n- API changes wrt to runtime.Module\r\n - tvm.module.load -\u003e tvm.runtime.load_module\r\n - tvm.module.enabled -\u003e tvm.runtime.enabled\r\n - tvm.module.system_lib -\u003e tvm.runtime.system_lib\r\n- Remove dep on api_internal from runtime.\r\n\r\n* Update module.load in the latest API\r\n" }, { "commit": "d60fb1c9a683738b877de02b7bb048fc943f76d4", "tree": "29ba4773c59862357d92c91cf58d200bd0619bd4", "parents": [ "81dc28db5a41b259cdb89ed59216355b06687ecb" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Feb 04 09:21:51 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Feb 04 09:21:51 2020 -0800" }, "message": "[DOCS] Fix vta tutorial (#4809)\n\n" }, { "commit": "81dc28db5a41b259cdb89ed59216355b06687ecb", "tree": "fc29f5a1ac17d8ed290d00855147ce3cbdd43dfe", "parents": [ "01ed0cd0b65577bb9f8c7dab21a1bcfd87461920" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Feb 03 20:47:51 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 03 18:47:51 2020 -1000" }, "message": "[LINT] Fix -Wextra (#4804)\n\n* [LINT] Fix -Wextra\r\n\r\n* Fix virtual-dtor\r\n" }, { "commit": "01ed0cd0b65577bb9f8c7dab21a1bcfd87461920", "tree": "822c11c54df0f290eb9bb014dd476750e8bc5e26", "parents": [ "3a669d6216eefd718073ae9b91989913a1b25f03" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Thu Jan 23 14:05:07 2020 -0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Thu Jan 23 14:05:07 2020 -0800" }, "message": "[VTA] Support network which have no unique operator as start/stop name for graph pack. (#4703)\n\n* [VTA] Support network which have no unique operator as start/stop name\r\nfor graph pack.\r\n\r\n[Issue]\r\n Current vta use \u0027start\u0027 and \u0027stop\u0027 name to define the pack start point\r\n and end point, but this method not work for these network which have\r\n no 2 unique operator as start point and stop point.\r\n\r\n[Solution]\r\n In this solution we give 2 addtional parameters start_name_indx and\r\n stop_name_indx to make vta pack logic work with the said network,\r\n for exampl for following networks which have no unique operator,\r\n\r\n %0 \u003d nn.add\r\n %1 \u003d nn.conv2d\r\n %2 \u003d nn.batch_norm\r\n %3 \u003d nn.leaky_relu\r\n %4 \u003d nn.add\r\n %5 \u003d nn.conv2d\r\n %6 \u003d nn.batch_norm\r\n %7 \u003d nn.leaky_relu\r\n %8 \u003d nn.add\r\n\r\n with this solution we can use following parameter format to make\r\n vta work on it.\r\n\r\n relay_prog \u003d graph_pack(\r\n //....\r\n start_name\u003d\"nn.add\",\r\n stop_name\u003d\"nn.add\",\r\n start_name_idx\u003d0,\r\n stop_name_idx\u003d4)\r\n\r\n to apply on new network, by printing the network we can get index information like following.\r\n\r\n print(mod.astext(show_meta_data\u003dFalse))\r\n relay_prog \u003d graph_pack(mod\r\n ...\r\n start_name\u003d\"nn.add\",\r\n stop_name\u003d\"nn.add\",\r\n start_name_idx\u003d0,\r\n stop_name_idx\u003d4)\r\n\r\n* address review comments and fix index count bug\r\n\r\nissue:\r\nwhen do print(mod), the output not only the Call is also have other type\r\nlike Var, need add logic to count all except meta.\r\n\r\nsolution:\r\nadd related logic\r\n\r\n* address review comments.\r\n\r\n* address review comments\r\n\r\n* add more detail comments.\r\n" }, { "commit": "3a669d6216eefd718073ae9b91989913a1b25f03", "tree": "067f4b2bbe003328d721b55a83fb4da4820f4ca5", "parents": [ "6bb74c0efd64c30f43353364a9bfb6923585d628" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Jan 19 09:53:22 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jan 19 09:53:22 2020 -0800" }, "message": "[REFACTOR][CODEGEN] codegen-\u003etarget, build_module-\u003edriver (#4742)\n\nThis PR moves the codegen related code into the target folder,\r\nas they are target specific functionalities.\r\n\r\nWe also adopt the term \"compiler driver\" in common compiler infra\r\nsuch as rust, GHC and clang.\r\nAs a result, build_module is moved into the driver folder." }, { "commit": "6bb74c0efd64c30f43353364a9bfb6923585d628", "tree": "bb2eb87573dc9e21ce810d1a69833520ed6bb82e", "parents": [ "57f9d7f44bbf3ad65c6123d8e902eec0398a683b" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@harman.com", "time": "Sat Jan 18 07:23:49 2020 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Fri Jan 17 15:23:49 2020 -0800" }, "message": "[VTA][TSIM] Enable TSIM CI Testing (#4407)\n\n* Update task_python_vta.sh\r\n\r\n* install sbt\u003d1.1.1 with apt-get\r\n\r\n* update verilator_opt\r\n\r\n* install verilator with major version 4.0\r\n\r\n* disable multi-threading for now\r\n\r\n* bug fix for correcting uop fetch address in LoadUop module\r\n\r\n* bug fix for correcting uop fetch address in LoadUop module\r\n\r\n* adjustment to read from dram_offset\r\n\r\n* enable USE_THREADS with verilator 4.x\r\n\r\n* DEBUG: try avoid core dump with verilator 4.x\r\n\r\n* bug fix in LoadUop module\r\n\r\n* log mega cycles in tsim\r\n\r\n* download cat.png to avoid fetching in each run\r\n\r\n* bug fix in LoadUop module\r\n\r\n* solve dram_even/sram_even issue\r\n\r\n* bug fix\r\n\r\n* introduce scalalint in ci\r\n\r\n* speedup tsim in ci\r\n\r\n* bug fix\r\n\r\n* lint scala code before building\r\n\r\n* disable multi-threading\r\n\r\n* split fsim/tsim script\r\n\r\n* update Jenkins settings\r\n\r\n* duplicate task_python_vta_fsim.sh as task_python_vta.sh for now\r\n\r\nCo-authored-by: Thierry Moreau \u003ctmoreau@octoml.ai\u003e\r\n" }, { "commit": "57f9d7f44bbf3ad65c6123d8e902eec0398a683b", "tree": "edcc8980dec0ed9d67fb97806a9225f96ef4331c", "parents": [ "e7e5f799203a9ad1757a8935364eacc927255462" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Wed Jan 15 19:44:39 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 15 19:44:39 2020 -0800" }, "message": "[REFACTOR][FFI] Make more clear naming for C API Type codes. (#4715)\n\nThis PR introduces more clear naming prefix for C API type codes\r\nto avoid conflict with other packages.\r\n\r\nWe also removed TVMArray and TVMType to directly use DLTensor and DLDataType." }, { "commit": "e7e5f799203a9ad1757a8935364eacc927255462", "tree": "a99f2ebb7ca960fd53b9376841b53fdf695b0d44", "parents": [ "9d7a9625cfdd71945bef40e40e859d3a3c20b155" ], "author": { "name": "Haichen Shen", "email": "shenhaichen@gmail.com", "time": "Tue Jan 14 20:03:14 2020 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Jan 14 20:03:14 2020 -0800" }, "message": "Revert \"[Relay][TOPI]Fix meaning of conv2d_transpose output_padding parameter (#4318)\" (#4708)\n\nThis reverts commit dcf7fbf1f962569e78c624755b2d612fffa81ada." }, { "commit": "9d7a9625cfdd71945bef40e40e859d3a3c20b155", "tree": "e21ea3b10ff4f63ae3388ce374c1d86b66a36acc", "parents": [ "3667499e915e4f1a6f44e9992e0db6c3f0b2a748" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Tue Jan 14 10:39:56 2020 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Mon Jan 13 18:39:55 2020 -0800" }, "message": "[VTA] Fix an issue in updating uop_idx in the TensorGemm module (#4694)\n\n" }, { "commit": "3667499e915e4f1a6f44e9992e0db6c3f0b2a748", "tree": "8a7932a4031de079f141b3cab29a7f89d701c604", "parents": [ "7ffd5c5b33a30df64ad826e2f5490d632ef7f305" ], "author": { "name": "abergeron", "email": "abergeron@gmail.com", "time": "Fri Jan 10 19:24:52 2020 -0500" }, "committer": { "name": "Wuwei Lin", "email": "wuwei@apache.org", "time": "Fri Jan 10 19:24:52 2020 -0500" }, "message": "[Relay][TOPI]Fix meaning of conv2d_transpose output_padding parameter (#4318)\n\n* Add output_padding to generic\r\n\r\n* Add output_padding to the reference impl\r\n\r\n* Add output_padding to arm_cpu\r\n\r\n* Add output_padding to the test\r\n\r\n* Add output_padding for cuda\r\n\r\n* Add output_padding for x86\r\n\r\n* Make use of the new output_padding argument in Relay\r\n\r\n* Adjust conv2d_transpose Relay test\r\n\r\n* Fix lint errors\r\n\r\n* Fix the VTA declaration of conv2d_transpose\r\n\r\n* support for output padding in conv2d transpose\r\n\r\n* some output padding will break IR pass\r\n\r\n* Fix new conv2d_transpose test\r\n\r\n* Update tophub\r\n\r\n* Fix conv1d output_padding too.\r\n\r\n* Fix the conv1d_transpose reference function.\r\n\r\n* Fix the cuda impl\r\n\r\n* fix the topi test for conv1d\r\n\r\n* Update the versions in tophub.py\r\n\r\nCo-authored-by: Thierry Moreau \u003ctmoreau@octoml.ai\u003e\r\n" }, { "commit": "7ffd5c5b33a30df64ad826e2f5490d632ef7f305", "tree": "3bd164b9c3b4f3bd19df71788a2d43d2d37e03a5", "parents": [ "453d0c87b555afcce8797b8a63e155aa8f92a020" ], "author": { "name": "Leandro Nunes", "email": "leandro.nunes@arm.com", "time": "Mon Jan 06 16:31:07 2020 +0000" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Jan 06 08:31:07 2020 -0800" }, "message": "Pin python pillow to \"\u003c7\" due to torchvision 1.2.0 dependency issue (#4632)\n\n* As a result of backwards incompatible changes released in pillow 7.0,\r\n torchvision crashes if you just \"pip install pillow\", as we do in\r\n a few places.\r\n\r\n * This patch sets pillow\u003c7 to be installed in Dockerfiles and support\r\n material as tutorials and documentation." }, { "commit": "453d0c87b555afcce8797b8a63e155aa8f92a020", "tree": "f49ee12b2295b0592923dae9b1e02f8ca1d56b83", "parents": [ "80f518a57bd9a1b59140d750413a7fb0c94a21a2" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Jan 05 21:39:33 2020 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jan 05 21:39:33 2020 -0800" }, "message": "[REFACTOR][IR] Introduce SeqStmt to replace ir::Block (#4627)\n\n* [REFACTOR][IR] Introduce SeqStmt to replace Block\r\n\r\nir::Block was used to represent a sequence of Stmts in the original low-level IR.\r\nThe nested ir::Block structure is not really friendly for recursive visits,\r\nespecially when the statements are unrolled.\r\n\r\nThis PR introduce a SeqStmt that directly stores a sequence of statements in an Array container.\r\nThe new SeqStmt will be used as a replacement of the original Block structure.\r\n\r\n* [REFACTOR] Migrate use of Block to SeqStmt.\r\n\r\n* [REFACTOR] Remove Block\r\n\r\n* Add more comments per yizhi\u0027s comment\r\n" }, { "commit": "80f518a57bd9a1b59140d750413a7fb0c94a21a2", "tree": "905bfd28658b6bd38c2685ebe466d4bfc0404dec", "parents": [ "b693922332b43b931118c59f483c18dcaf365904" ], "author": { "name": "Kevin Yuan", "email": "kevinyuan@users.noreply.github.com", "time": "Mon Jan 06 08:56:16 2020 +0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Jan 05 16:56:16 2020 -0800" }, "message": "Added declare of aluBits for TensorAlu (#4624)\n\n" }, { "commit": "b693922332b43b931118c59f483c18dcaf365904", "tree": "5171f1151c7b832da769c5e762ab15246d2797bf", "parents": [ "4e30e958f3c58af4e576123b6f7f408143aae8a2" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Sat Jan 04 01:37:50 2020 +0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Fri Jan 03 09:37:50 2020 -0800" }, "message": "[VTA] Throw exception on mis-formatted files and avoid overwrite Scala code (#4555)\n\n" }, { "commit": "4e30e958f3c58af4e576123b6f7f408143aae8a2", "tree": "44f8a6208a3cccb576958115371216a96a9796e5", "parents": [ "f99f4ef1ae84c91a82b2b68fc5a402d0518f3c6a" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Tue Dec 24 00:43:52 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Mon Dec 23 17:43:52 2019 +0100" }, "message": "[VTA][Chisel] End-to-end Inference with Chisel VTA (#4574)\n\n* [VTA][Chisel] End-to-end Inference with Chisel VTA\r\n\r\n* Update TensorAlu.scala\r\n" }, { "commit": "f99f4ef1ae84c91a82b2b68fc5a402d0518f3c6a", "tree": "b971025479512ad81b6d60d5172cd516e6d5c111", "parents": [ "919681d40514e0de8764320ed9f775fe6ba961bc" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Sun Dec 22 06:19:56 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Sat Dec 21 23:19:56 2019 +0100" }, "message": "[VTA] improved virtual memory mapping (#4545)\n\n* [VTA] improved virtual memory mapping\r\n\r\n* Update virtual_memory.cc\r\n" }, { "commit": "919681d40514e0de8764320ed9f775fe6ba961bc", "tree": "0bbd3f33c016bcfd47650849b2815a85d92de2a1", "parents": [ "81327ed8db4c623a0c2347f4573c51553b5c0095" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Tue Dec 17 02:26:54 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Mon Dec 16 10:26:54 2019 -0800" }, "message": "fix crash issue in tsim backend (#4527)\n\n" }, { "commit": "81327ed8db4c623a0c2347f4573c51553b5c0095", "tree": "5ff591cfa4c9ecb7cde50a34f08a38b4738f0e09", "parents": [ "639b9e920a632c0a424a52895c837458412584a4" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Wed Dec 11 08:53:53 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Tue Dec 10 16:53:53 2019 -0800" }, "message": "[VTA] Speedup TSIM by Multi-threading (#4491)\n\nThis PR tries to increase TSIM performance by introducing multi-threading support." }, { "commit": "639b9e920a632c0a424a52895c837458412584a4", "tree": "8c63de1d11a4b3b0afabf862a932a2924885d220", "parents": [ "2a3502319295b48e4ccc77984d0d5e72c6106b32" ], "author": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Sun Dec 08 22:08:21 2019 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Dec 08 22:08:21 2019 -0800" }, "message": "[VTA] Bringing group convolution support (#4421)\n\n* group conv operator support for VTA\r\n\r\n* autotvm tuning script for group conv2d\r\n\r\n* lint fix\r\n\r\n* lint fix\r\n\r\n* lint fix\r\n\r\n* addressing comments\r\n" }, { "commit": "2a3502319295b48e4ccc77984d0d5e72c6106b32", "tree": "d34d65eb32da504e0300edb22ce2f0a05019751d", "parents": [ "c78802e2f4e863bff656a8d03e1b397f863ff519" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@harman.com", "time": "Thu Nov 28 14:45:58 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Wed Nov 27 22:45:58 2019 -0800" }, "message": "fix multiple transfer issue in loaduop (#4442)\n\n" }, { "commit": "c78802e2f4e863bff656a8d03e1b397f863ff519", "tree": "00c9eda8529ca3b5ad33c13163d03828471f1ebf", "parents": [ "31a00821a02ec00d3afc683d3913998d0c783513" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@harman.com", "time": "Thu Nov 28 01:04:19 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Wed Nov 27 09:04:18 2019 -0800" }, "message": "[VTA] Enable streamlined GEMM execution (#4392)\n\n* disable pipelined adder and enable streamlined gemm execution\r\n\r\n* pipeline first layer of adder\r\n\r\n* explain difference between pipeadder and adder\r\n\r\n* add comment for explaining the hard-coded latency\r\n" }, { "commit": "31a00821a02ec00d3afc683d3913998d0c783513", "tree": "257fac5d2484bb110c5ff425b8ae6791c5aa534b", "parents": [ "cdffa81f4d8b9f1dfa957b95555f0f3bdf8a7482" ], "author": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Tue Nov 26 19:21:56 2019 -0800" }, "committer": { "name": "Yizhi Liu", "email": "liuyizhi@apache.org", "time": "Tue Nov 26 19:21:56 2019 -0800" }, "message": "[VTA][HotFix] Relay-\u003eVTA quantization fix (#4433)\n\n* relay -\u003e vta fix\r\n\r\n* setting optlevel to 3 for quantization to fold batchnorm\r\n" }, { "commit": "cdffa81f4d8b9f1dfa957b95555f0f3bdf8a7482", "tree": "46cb4a62a8fef46dffbd94881f4ddd88266775cd", "parents": [ "84db54804960d62a444400d59de2d5b5738df2a1" ], "author": { "name": "Thierry Moreau", "email": "tmoreau@octoml.ai", "time": "Mon Nov 25 16:18:10 2019 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Nov 25 16:18:10 2019 -0800" }, "message": "removing nnvm dep from VTA sources (#4419)\n\n" }, { "commit": "84db54804960d62a444400d59de2d5b5738df2a1", "tree": "f8aae5a55ce67452140f0fe13eea323332bff910", "parents": [ "365b03b04bc9139359411f4e7d1f1339113e71c6" ], "author": { "name": "Yizhi Liu", "email": "liuyizhi@apache.org", "time": "Sun Nov 24 09:44:38 2019 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Nov 24 09:44:38 2019 -0800" }, "message": "[License] move cma_api to 3rdparty. separate BSD 2-clause and 3-clause (#4410)\n\n* [License] move cma_api to 3rdparty. separate BSD 2-clause and 3-clause\r\n\r\n* add zlib license for blockingconcurrentqueue.h\r\n" }, { "commit": "365b03b04bc9139359411f4e7d1f1339113e71c6", "tree": "24204206f030c7a0995c963cc2679a9a1b71613a", "parents": [ "d1494bc73d4f122d52899556a9331e6298438798" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sun Nov 24 00:22:55 2019 -0800" }, "committer": { "name": "Yizhi Liu", "email": "liuyizhi@apache.org", "time": "Sun Nov 24 00:22:55 2019 -0800" }, "message": "[LINT] Remove unnecessary copyright message for files with ASF header (#4409)\n\n* [LINT] Improve the check tool to handle ASF copyright message.\r\n\r\n* [LINT] Remove unnecessary copyright message as per ASF requirement.\r\n\r\n* Fix codegen hybrid\r\n\r\n* [LINT] Broaden license checks to include html, xml\r\n\r\n* [LINT] Fix rest of the files\r\n\r\n* Fix notice\r\n\r\n* [LINT] Improve check file type error message\r\n" }, { "commit": "d1494bc73d4f122d52899556a9331e6298438798", "tree": "bf85c6a706ce1df4937350d5fecfe666404484ba", "parents": [ "8b69697e14390b79542f0aea675dd6f1356cae0a" ], "author": { "name": "Yizhi Liu", "email": "liuyizhi@apache.org", "time": "Sat Nov 23 19:39:25 2019 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sat Nov 23 19:39:25 2019 -0800" }, "message": "[Release] resolve license issues (#4408)\n\n" }, { "commit": "8b69697e14390b79542f0aea675dd6f1356cae0a", "tree": "44b93dedb95922458d59218f5a714961bfd2f263", "parents": [ "c09ec7d2d48e8a04153367c53826e2bf97947b85" ], "author": { "name": "tripley", "email": "34867417+gittripley@users.noreply.github.com", "time": "Thu Nov 21 19:12:05 2019 -0800" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Thu Nov 21 19:12:05 2019 -0800" }, "message": "update_document_after_repository_renamed (#4398)\n\n" }, { "commit": "c09ec7d2d48e8a04153367c53826e2bf97947b85", "tree": "37e82d734d1733658d124ef873786c304ac0d6a8", "parents": [ "44160866e7f7261d7d5526e6c0515f30a3f6366f" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Nov 18 10:22:25 2019 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 18 10:22:25 2019 -0800" }, "message": "[SOURCE] Add ASF header to __init__.py files (#4359)\n\n" }, { "commit": "44160866e7f7261d7d5526e6c0515f30a3f6366f", "tree": "a830f0b1d564b33147fb9b723597ac07b38eb69e", "parents": [ "779d39da2ca9fa60daf78de3747eff902b20f270" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Sat Nov 16 01:59:04 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Fri Nov 15 09:59:04 2019 -0800" }, "message": "[VTA] Bug fix for padded load with large inputs (#4293)\n\n* bug fix for padded load with large inputs\r\n\r\n* Update TensorLoad.scala\r\n\r\n* Update test_vta_insn.py\r\n" }, { "commit": "779d39da2ca9fa60daf78de3747eff902b20f270", "tree": "3fb86a3127852c6da6308fefaba9d9785fc56563", "parents": [ "834ddf1b9a9c1aa18fb6a1b00fe6f59251a97480" ], "author": { "name": "jason-song-dev", "email": "37959160+jason-song-dev@users.noreply.github.com", "time": "Thu Nov 14 12:42:22 2019 +0900" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Wed Nov 13 19:42:22 2019 -0800" }, "message": "fix error when memory_id is VTA_MEM_ID_OUT (#4330)\n\n" }, { "commit": "834ddf1b9a9c1aa18fb6a1b00fe6f59251a97480", "tree": "fc2c68db7a6635e412f21db6202cfbbaa23891ab", "parents": [ "2ad49d28fe42ec58415f5a260c70365b65b85944" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Mon Nov 11 10:09:29 2019 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 11 10:09:29 2019 -0800" }, "message": "[RUNTIME][REFACTOR] Use object protocol to support runtime::Module (#4289)\n\nPreviously runtime::Module was supported using shared_ptr.\r\nThis PR refactors the codebase to use the Object protocol.\r\n\r\nIt will open doors to allow easier interpolation between\r\nObject containers and module in the future." }, { "commit": "2ad49d28fe42ec58415f5a260c70365b65b85944", "tree": "fecfdbd0294275d74c5dd9dc1ceb272509feba32", "parents": [ "476a09c815b47e52368d9ac16c48bb41d49867c7" ], "author": { "name": "Liangfu Chen", "email": "liangfu.chen@icloud.com", "time": "Thu Nov 07 01:19:22 2019 +0800" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Wed Nov 06 09:19:22 2019 -0800" }, "message": "[VTA] Hotfix for padded load test in Chisel VTA (#4264)\n\n* Update TensorUtil.scala\r\n\r\n* Update test_vta_insn.py\r\n" }, { "commit": "476a09c815b47e52368d9ac16c48bb41d49867c7", "tree": "684f1abd93c642862dda7defc556c0844be3ec27", "parents": [ "bc133b978d6dab91fafdb777738b601acdb897db" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Tue Nov 05 16:03:04 2019 -0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 05 16:03:04 2019 -0800" }, "message": "[DOCS] Update link loc (#4257)\n\n" }, { "commit": "bc133b978d6dab91fafdb777738b601acdb897db", "tree": "fc2faf29a0894043f87098d2f3ad33220f2159a7", "parents": [ "0b530715eed08579c8c433ad994991c457fd41f9" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Fri Nov 01 20:29:54 2019 -0700" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Fri Nov 01 20:29:54 2019 -0700" }, "message": "[VTA] Performance optimize, remove unnecessary contigious memory use. (#4246)\n\n* [VTA] Performance optimize, remove unnecessary contigious memory use.\r\n\r\nIssue:\r\nUop maintain a cache vector to copy uop data into contigious DRAM memory for\r\nFPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator\r\ncore run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier\r\nfunction, we can saw such cache size keep increase, this would cause\r\nno use data copy and unnecessary contigous DRAM memory malloc.\r\n\r\nAnalysis:\r\nThis issue caused by not clear cache_ vector when do\r\nuop_queue_.Reset().\r\n\r\nSolution:\r\nOverride BaseQueue Reset function in UopQueue and add cache_ clear\r\nlogic.\r\n\r\n* address review comments, remove spacing.\r\n" }, { "commit": "0b530715eed08579c8c433ad994991c457fd41f9", "tree": "d27518357553616ef6cde6a43983a9afba097cda", "parents": [ "5b1350f2f73e5981b658a6b56cc8e5bde1192e91" ], "author": { "name": "Benjamin Tu", "email": "tu.benjamin1115@gmail.com", "time": "Sat Oct 26 17:06:49 2019 -0700" }, "committer": { "name": "Jared Roesch", "email": "roeschinc@gmail.com", "time": "Sat Oct 26 17:06:49 2019 -0700" }, "message": "[VTA][Chisel] TSIM VTA Source Refactor (#4163)\n\n* app init push\r\n\r\n* fix on readme\r\n\r\n* change name, add bit serial explanantion\r\n\r\n* rm serialLoadMM, change doc\r\n\r\n* syntax change for readme\r\n\r\n* add parallel test functionality\r\n\r\n* fix readme\r\n\r\n* add python doc\r\n\r\n* syntax\r\n\r\n* init commit\r\n\r\n* fix empty line\r\n\r\n* fix typo\r\n" }, { "commit": "5b1350f2f73e5981b658a6b56cc8e5bde1192e91", "tree": "759203631808baf11b4ed8d463c3c0c8dc91a8ea", "parents": [ "6e0dbeed3209a43ab621fdb9eea0687e3b44611d" ], "author": { "name": "Siyuan Feng", "email": "Hzfengsy@vip.qq.com", "time": "Thu Oct 24 12:04:37 2019 -0700" }, "committer": { "name": "Leyuan Wang", "email": "laurawly@gmail.com", "time": "Thu Oct 24 12:04:37 2019 -0700" }, "message": "TensorCore Support using Intrinsic (#4136)\n\n* add tensor core support\r\n\r\n* avoid memory bank conflict\r\n\r\n* fix thread sync \u0026 better performance\r\n\r\n* better performance\r\n\r\n* add schedule test for conv2d\r\n\r\n* extend into BatchMatMul\r\n\r\n* support config fragment shape and layout using intrinsic\r\n\r\n* add TensorCore tutorial\r\n\r\n* add int support and fix lint\r\n\r\n* address comment\r\n\r\n* add 32*16*8 TensorCore test\r\n\r\n* fix wmma include logic\r\n" }, { "commit": "6e0dbeed3209a43ab621fdb9eea0687e3b44611d", "tree": "6804e4750ab6b4eee4db717ed75a157dc34dffc1", "parents": [ "94354d65dcb27a47477c32178020d501daeff08c" ], "author": { "name": "Benjamin Tu", "email": "tu.benjamin1115@gmail.com", "time": "Thu Oct 10 13:37:05 2019 -0700" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Thu Oct 10 13:37:05 2019 -0700" }, "message": "[VTA][TSIM] Serial GEMM Application Added (#4082)\n\n* app init push\r\n\r\n* fix on readme\r\n\r\n* change name, add bit serial explanantion\r\n\r\n* rm serialLoadMM, change doc\r\n\r\n* syntax change for readme\r\n\r\n* add parallel test functionality\r\n\r\n* fix readme\r\n\r\n* add python doc\r\n\r\n* syntax\r\n" }, { "commit": "94354d65dcb27a47477c32178020d501daeff08c", "tree": "fc587acd3cb1a90c40ed0fe5240ab2e581efdb5a", "parents": [ "89be93339a7a2cf2a0561abbcd4039450b01d780" ], "author": { "name": "Attila Dusnoki", "email": "dati91@users.noreply.github.com", "time": "Tue Oct 08 21:24:56 2019 +0200" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Tue Oct 08 12:24:56 2019 -0700" }, "message": "Fix wrong n_trial number in autotvm tutorials\u0027 progress bar (#4070)\n\nif n_trial is larger then config space." }, { "commit": "89be93339a7a2cf2a0561abbcd4039450b01d780", "tree": "5228f7797afa675ccf39b409f5b53c8fcc8c2ae3", "parents": [ "9b58279363062c6de17a6fc81376ef9cd83f31cf" ], "author": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Sat Sep 28 14:43:44 2019 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Sep 28 14:43:44 2019 -0700" }, "message": "[ARITH] cleanup the indexmod/div on python side (#4028)\n\n" }, { "commit": "9b58279363062c6de17a6fc81376ef9cd83f31cf", "tree": "272b6a54b07bdbc5279059f024b98bf05581cba8", "parents": [ "32dbf8e9da8deb8cd6212c8957070d72e0471921" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Fri Sep 13 13:33:55 2019 -0700" }, "committer": { "name": "Tianqi Chen", "email": "tqchen@users.noreply.github.com", "time": "Fri Sep 13 13:33:55 2019 -0700" }, "message": "[VTA] RPC path update. (#3924)\n\nIssue:\r\nRPC path get changed into \"vta_rpc\" from \"pynq_rpc\", but related\r\ndocument still use old informaiton.\r\n\r\nSolution:\r\nUpdate RPC path information." }, { "commit": "32dbf8e9da8deb8cd6212c8957070d72e0471921", "tree": "160a3fcb96fcfaa35a30fb502710a9ca721d17ed", "parents": [ "cb9958a62c8e4ae694697205f79a5f6e90e709e8" ], "author": { "name": "Luis Vega", "email": "vegaluisjose@users.noreply.github.com", "time": "Mon Sep 09 10:31:31 2019 -0700" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Mon Sep 09 10:31:31 2019 -0700" }, "message": "[VTA][Config] hotfix denano10 (#3918)\n\n" }, { "commit": "cb9958a62c8e4ae694697205f79a5f6e90e709e8", "tree": "ebf7ea0af193173b0e7ec8e020ecc89183367523", "parents": [ "29a0e9a300939c34f233ae0b671c9a27ba5b77c8" ], "author": { "name": "Hua Jiang", "email": "huaj@xilinx.com", "time": "Fri Sep 06 17:03:51 2019 -0700" }, "committer": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Fri Sep 06 17:03:51 2019 -0700" }, "message": "[VTA] Support TLPP in function simulator. (#3555)\n\n* [VTA] Support TLPP in function simulator.\r\nIssue:\r\ncurrently vta function simulator just doing serialized instruction\r\nexecution, the dependency logic of runtime ISA which use for task\r\nlevel pipe line parallelism can not get verified by function simulator.\r\n\r\nSolution:\r\nmake the simulator driver to be multiple thread and support TLPP.\r\n\r\nBenefit:\r\nTLPP support VTA function simulator would make VTA logic testing/debug\r\n/change more easy.\r\n\r\nreplace boost lockfree queue\r\n\r\nadd configure control for simulator tlpp enable or disable.\r\n\r\nchange code tyle into google style.\r\n\r\nWrap queue read/write and sync logic to make function call more simple.\r\n\r\nAdd some comments.\r\n\r\nRemove MT logic, change into Single thread mode.\r\n\r\naddress review comments.\r\n\r\ncode style change to match google code style and add comments.\r\n\r\nadd cmake macro to enable/disable simulator tlpp logic.\r\n\r\nsubmodule update.\r\n\r\ncorrect file name mentioned in comments.\r\n\r\n* remove USE_VTA_FSIM_TLPP.\r\n" }, { "commit": "29a0e9a300939c34f233ae0b671c9a27ba5b77c8", "tree": "467b0b80b0c52a4319022ce49fbda1503db1d6b8", "parents": [ "51e9742c59e037dc0f3d88c7881a795326e7d50b" ], "author": { "name": "Thierry Moreau", "email": "moreau@uw.edu", "time": "Thu Sep 05 11:29:42 2019 -0700" }, "committer": { "name": "Jared Roesch", "email": "roeschinc@gmail.com", "time": "Thu Sep 05 11:29:42 2019 -0700" }, "message": "[VTA][TOPI] Conv2d transpose (deconvolution) operator support (#3777)\n\n* initial conv2d_transpose\r\n\r\n* correct select operator\r\n\r\n* cleanup\r\n\r\n* fix\r\n\r\n* fix correcness check\r\n\r\n* conv2d transpose declaration fix\r\n\r\n* autotvm conv2d_transpose tuning script\r\n\r\n* ir pass fix\r\n\r\n* fix tuning script\r\n\r\n* deriving params from env, adding bias\r\n\r\n* removing bias comp from deconvolution\r\n\r\n* lint\r\n\r\n* fix\r\n\r\n* lint\r\n\r\n* lint\r\n\r\n* turning off cpu\r\n\r\n* lint, ops\r\n\r\n* lint\r\n\r\n* import fix\r\n\r\n* removing hard coded values\r\n\r\n* lint\r\n" } ], "next": "51e9742c59e037dc0f3d88c7881a795326e7d50b" }