Port to new Chisel stable release (3.5) (#37)

* upgrade to stable chisel 3.5.0

* fix chiesl 3.5 warnings

* port tests to chiseltest

* change chisel hardware makefile to use sbt test to run unittests
33 files changed
tree: f5cd9d381148994bdd44a133d5a50109de3d8713
  1. apps/
  2. config/
  3. hardware/
  4. include/
  5. src/
  6. tests/
  7. .asf.yaml
  8. .gitignore
  9. Jenkinsfile
  11. NOTICE
  12. README.md

VTA Hardware Design Stack

Build Status

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

  • Generic, modular, open-source hardware
    • Streamlined workflow to deploy to FPGAs.
    • Simulator support to prototype compilation passes on regular workstations.
  • Driver and JIT runtime for both simulator and FPGA hardware back-end.
  • End-to-end TVM stack integration
    • Direct optimization and deployment of models from deep learning frameworks via TVM.
    • Customized and extensible TVM compiler back-end.
    • Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.