[VTA] [Chisel] Improved Data Gen, Added ALU Test (#3743)

* added alutest

* fix indent

* name change for cycle

* improved data gen and infra

* added alutest

* fix indent

* name change for cycle

* improved data gen and infra

* fix space

* fix indent

* fixes

* aluRef

* fix randomarary

* add

* Revert "add"

This reverts commit 87077daebbe055dee11f80e37da3a6291138e0f0.

* Revert "fix randomarary"

This reverts commit df386c1e660eb6ebcff1a1f905610573676f1589.

* Revert "aluRef"

This reverts commit 8665f0d4a7b12b796b2cb1ca6bf9cfe5613ee389.

* should fix dlmc-core
8 files changed
tree: b09bcbb5d70dfb147b53e2f227ebde337283aa09
  1. apps/
  2. config/
  3. hardware/
  4. include/
  5. python/
  6. scripts/
  7. src/
  8. tests/
  9. tutorials/
  10. README.md
README.md

VTA: Open, Modular, Deep Learning Accelerator Stack

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

  • Generic, modular, open-source hardware
    • Streamlined workflow to deploy to FPGAs.
    • Simulator support to prototype compilation passes on regular workstations.
  • Driver and JIT runtime for both simulator and FPGA hardware back-end.
  • End-to-end TVM stack integration
    • Direct optimization and deployment of models from deep learning frameworks via TVM.
    • Customized and extensible TVM compiler back-end.
    • Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.

Learn more about VTA here.