Chisel Pipelined ALU  (#27)

* Remove parameter values from case class

* Add new blockOutFactor parameter with default value = 1

* Support split access

* Modify to support split interface, minor refactoring

* Use split read/write intefaces

* Pipelined ALU with split interfaces

* Modify instantiation and usage of pipelined ALU and split interfaces

* Don't use internal Random by default

* Change tester name

* Add generic tester class

* Derive from GenericTest, minor refactoring

* Test ALU index generator and pipelined ALU

* Add ASF header

* Bugfix: delay slicing index by a cycle to match SyncReadMem read delay

* Formatting, comment, and minor refactoring changes for clarity

* Fix scalastyle issues for test files
14 files changed
tree: 0f4ac9aaed6758f245d02abaf7adb56d02f6dfa5
  1. .asf.yaml
  2. .gitignore
  3. Jenkinsfile
  4. LICENSE
  5. NOTICE
  6. README.md
  7. apps/
  8. config/
  9. hardware/
  10. include/
  11. src/
  12. tests/
README.md

VTA Hardware Design Stack

Build Status

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

  • Generic, modular, open-source hardware
    • Streamlined workflow to deploy to FPGAs.
    • Simulator support to prototype compilation passes on regular workstations.
  • Driver and JIT runtime for both simulator and FPGA hardware back-end.
  • End-to-end TVM stack integration
    • Direct optimization and deployment of models from deep learning frameworks via TVM.
    • Customized and extensible TVM compiler back-end.
    • Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.