commit	c5ebbe7dad59f8d5d29b18453946f0d0b39e7202	[log] [tgz]
author	Luis Vega <vegaluisjose@users.noreply.github.com>	Tue Jun 11 16:55:41 2019 -0700
committer	Thierry Moreau <moreau@uw.edu>	Tue Jun 11 16:55:41 2019 -0700
tree	474f9e34f9ee6e1c1272f2e3d632c674cd6f98e5
parent	82686b95fecda26c4da9400234a0a66fafc990ca [diff]

[VTA][TSIM] update app example (#3343)

* add initial support to cycle counter to accelerator

* remove prints from c

* add event counter support to chisel tsim example

* make it more readable

* use a config class

* update driver

* add individual Makefile to chisel

* add rule for installing vta package

* add makefile for verilog backend

* update drivers

* update

* rename

* update README

* put default sim back

* set counter to zero

apps/tsim_example/CMakeLists.txt[diff]
apps/tsim_example/Makefile[diff]
apps/tsim_example/README.md[diff]
apps/tsim_example/cmake/modules/hw.cmake[Deleted - diff]
apps/tsim_example/cmake/modules/sw.cmake[Deleted - diff]
apps/tsim_example/config/config.json[Deleted - diff]
apps/tsim_example/config/config.py[Deleted - diff]
apps/tsim_example/hardware/chisel/Makefile[diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala[diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala[diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala[diff]
apps/tsim_example/hardware/verilog/Makefile[Added - diff]
apps/tsim_example/hardware/verilog/src/Accel.v[Renamed from apps/tsim_example/hardware/verilog/Accel.v - diff]
apps/tsim_example/hardware/verilog/src/Compute.v[Renamed from apps/tsim_example/hardware/verilog/Compute.v - diff]
apps/tsim_example/hardware/verilog/src/RegFile.v[Renamed from apps/tsim_example/hardware/verilog/RegFile.v - diff]
apps/tsim_example/hardware/verilog/src/TestAccel.v[Renamed from apps/tsim_example/hardware/verilog/TestAccel.v - diff]
apps/tsim_example/python/accel/__init__.py[Renamed from apps/tsim_example/python/tsim/__init__.py - diff]
apps/tsim_example/python/accel/driver.py[Renamed from apps/tsim_example/python/tsim/driver.py - diff]
apps/tsim_example/src/driver.cc[diff]
apps/tsim_example/tests/python/chisel_accel.py[Renamed from apps/tsim_example/tests/python/add_by_one.py - diff]
apps/tsim_example/tests/python/verilog_accel.py[Copied from apps/tsim_example/tests/python/add_by_one.py - diff]
hardware/chisel/src/main/resources/verilog/VTAHostDPI.v[diff]
hardware/dpi/tsim_device.cc[diff]

23 files changed

tree: 474f9e34f9ee6e1c1272f2e3d632c674cd6f98e5

README.md

VTA: Open, Modular, Deep Learning Accelerator Stack

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

Generic, modular, open-source hardware
- Streamlined workflow to deploy to FPGAs.
- Simulator support to prototype compilation passes on regular workstations.
Driver and JIT runtime for both simulator and FPGA hardware back-end.
End-to-end TVM stack integration
- Direct optimization and deployment of models from deep learning frameworks via TVM.
- Customized and extensible TVM compiler back-end.
- Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.

Learn more about VTA here.