commit	b097f0143c30c3126d41f35df4d5be197561af11	[log] [tgz]
author	tqchen <tqchen@octoml.ai>	Sun Mar 29 16:57:20 2020 -0700
committer	tqchen <tqchen@octoml.ai>	Sun Mar 29 18:21:04 2020 -0700
tree	3ee5203e792c38300cd4212f7772795cf42bb452
parent	ed30d7b3461793feb579f0a2072d1b53df34553b [diff]

[REFACTOR] VTA-HW setup

README.md[diff]
apps/gemm/CMakeLists.txt[Renamed from vta-hw/apps/gemm/CMakeLists.txt - diff]
apps/gemm/Makefile[Renamed from vta-hw/apps/gemm/Makefile - diff]
apps/gemm/README.md[Renamed from vta-hw/apps/gemm/README.md - diff]
apps/gemm/hardware/chisel/Makefile[Renamed from vta-hw/apps/gemm/hardware/chisel/Makefile - diff]
apps/gemm/hardware/chisel/build.sbt[Renamed from vta-hw/apps/gemm/hardware/chisel/build.sbt - diff]
apps/gemm/hardware/chisel/project/build.properties[Renamed from vta-hw/apps/gemm/hardware/chisel/project/build.properties - diff]
apps/gemm/hardware/chisel/project/plugins.sbt[Renamed from vta-hw/apps/gemm/hardware/chisel/project/plugins.sbt - diff]
apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala[Renamed from vta-hw/apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala - diff]
apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala[Renamed from vta-hw/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala - diff]
apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala[Renamed from vta-hw/apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala - diff]
apps/gemm/hardware/chisel/src/test/scala/dut/TestAccel.scala[Renamed from vta-hw/apps/gemm/hardware/chisel/src/test/scala/dut/TestAccel.scala - diff]
apps/gemm/python/__init__.py[Renamed from vta-hw/apps/gemm/python/__init__.py - diff]
apps/gemm/python/tsim.py[Renamed from vta-hw/apps/gemm/python/tsim.py - diff]
apps/gemm/src/driver.cc[Renamed from vta-hw/apps/gemm/src/driver.cc - diff]
apps/gemm/tests/python/chisel_accel.py[Renamed from vta-hw/apps/gemm/tests/python/chisel_accel.py - diff]
apps/tsim_example/CMakeLists.txt[Renamed from vta-hw/apps/tsim_example/CMakeLists.txt - diff]
apps/tsim_example/Makefile[Renamed from vta-hw/apps/tsim_example/Makefile - diff]
apps/tsim_example/README.md[Renamed from vta-hw/apps/tsim_example/README.md - diff]
apps/tsim_example/hardware/chisel/Makefile[Renamed from vta-hw/apps/tsim_example/hardware/chisel/Makefile - diff]
apps/tsim_example/hardware/chisel/build.sbt[Renamed from vta-hw/apps/tsim_example/hardware/chisel/build.sbt - diff]
apps/tsim_example/hardware/chisel/project/build.properties[Renamed from vta-hw/apps/tsim_example/hardware/chisel/project/build.properties - diff]
apps/tsim_example/hardware/chisel/project/plugins.sbt[Renamed from vta-hw/apps/tsim_example/hardware/chisel/project/plugins.sbt - diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala[Renamed from vta-hw/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala - diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala[Renamed from vta-hw/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala - diff]
apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala[Renamed from vta-hw/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala - diff]
apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala[Renamed from vta-hw/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala - diff]
apps/tsim_example/hardware/verilog/Makefile[Renamed from vta-hw/apps/tsim_example/hardware/verilog/Makefile - diff]
apps/tsim_example/hardware/verilog/src/Accel.v[Renamed from vta-hw/apps/tsim_example/hardware/verilog/src/Accel.v - diff]
apps/tsim_example/hardware/verilog/src/Compute.v[Renamed from vta-hw/apps/tsim_example/hardware/verilog/src/Compute.v - diff]
apps/tsim_example/hardware/verilog/src/RegFile.v[Renamed from vta-hw/apps/tsim_example/hardware/verilog/src/RegFile.v - diff]
apps/tsim_example/hardware/verilog/src/TestAccel.v[Renamed from vta-hw/apps/tsim_example/hardware/verilog/src/TestAccel.v - diff]
apps/tsim_example/python/__init__.py[Renamed from vta-hw/apps/tsim_example/python/__init__.py - diff]
apps/tsim_example/python/tsim.py[Renamed from vta-hw/apps/tsim_example/python/tsim.py - diff]
apps/tsim_example/src/driver.cc[Renamed from vta-hw/apps/tsim_example/src/driver.cc - diff]
apps/tsim_example/tests/python/chisel_accel.py[Renamed from vta-hw/apps/tsim_example/tests/python/chisel_accel.py - diff]
apps/tsim_example/tests/python/verilog_accel.py[Renamed from vta-hw/apps/tsim_example/tests/python/verilog_accel.py - diff]
config/README.md[Renamed from vta-hw/config/README.md - diff]
config/de10nano_sample.json[Renamed from vta-hw/config/de10nano_sample.json - diff]
config/fsim_sample.json[Renamed from vta-hw/config/fsim_sample.json - diff]
config/pkg_config.py[Renamed from vta-hw/config/pkg_config.py - diff]
config/pynq_sample.json[Renamed from vta-hw/config/pynq_sample.json - diff]
config/tsim_sample.json[Renamed from vta-hw/config/tsim_sample.json - diff]
config/ultra96_sample.json[Renamed from vta-hw/config/ultra96_sample.json - diff]
config/vta_config.json[Renamed from vta-hw/config/vta_config.json - diff]
config/vta_config.py[Renamed from vta-hw/config/vta_config.py - diff]
hardware/chisel/.gitignore[Renamed from vta-hw/hardware/chisel/.gitignore - diff]
hardware/chisel/Makefile[Renamed from vta-hw/hardware/chisel/Makefile - diff]
hardware/chisel/README.md[Renamed from vta-hw/hardware/chisel/README.md - diff]
hardware/chisel/build.sbt[Renamed from vta-hw/hardware/chisel/build.sbt - diff]
hardware/chisel/project/build.properties[Renamed from vta-hw/hardware/chisel/project/build.properties - diff]
hardware/chisel/project/plugins.sbt[Renamed from vta-hw/hardware/chisel/project/plugins.sbt - diff]
hardware/chisel/scalastyle-config.xml[Renamed from vta-hw/hardware/chisel/scalastyle-config.xml - diff]
hardware/chisel/src/main/resources/verilog/VTAHostDPI.v[Renamed from vta-hw/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v - diff]
hardware/chisel/src/main/resources/verilog/VTAMemDPI.v[Renamed from vta-hw/hardware/chisel/src/main/resources/verilog/VTAMemDPI.v - diff]
hardware/chisel/src/main/resources/verilog/VTASimDPI.v[Renamed from vta-hw/hardware/chisel/src/main/resources/verilog/VTASimDPI.v - diff]
hardware/chisel/src/main/scala/core/Compute.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Compute.scala - diff]
hardware/chisel/src/main/scala/core/Configs.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Configs.scala - diff]
hardware/chisel/src/main/scala/core/Core.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Core.scala - diff]
hardware/chisel/src/main/scala/core/Decode.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Decode.scala - diff]
hardware/chisel/src/main/scala/core/EventCounters.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/EventCounters.scala - diff]
hardware/chisel/src/main/scala/core/Fetch.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Fetch.scala - diff]
hardware/chisel/src/main/scala/core/ISA.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/ISA.scala - diff]
hardware/chisel/src/main/scala/core/Load.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Load.scala - diff]
hardware/chisel/src/main/scala/core/LoadUop.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/LoadUop.scala - diff]
hardware/chisel/src/main/scala/core/Semaphore.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Semaphore.scala - diff]
hardware/chisel/src/main/scala/core/Store.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/Store.scala - diff]
hardware/chisel/src/main/scala/core/TensorAlu.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/TensorAlu.scala - diff]
hardware/chisel/src/main/scala/core/TensorGemm.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/TensorGemm.scala - diff]
hardware/chisel/src/main/scala/core/TensorLoad.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/TensorLoad.scala - diff]
hardware/chisel/src/main/scala/core/TensorStore.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/TensorStore.scala - diff]
hardware/chisel/src/main/scala/core/TensorUtil.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/TensorUtil.scala - diff]
hardware/chisel/src/main/scala/core/package.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/core/package.scala - diff]
hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala - diff]
hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala - diff]
hardware/chisel/src/main/scala/dpi/VTASimDPI.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala - diff]
hardware/chisel/src/main/scala/interface/axi/AXI.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/interface/axi/AXI.scala - diff]
hardware/chisel/src/main/scala/shell/Configs.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/Configs.scala - diff]
hardware/chisel/src/main/scala/shell/IntelShell.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/IntelShell.scala - diff]
hardware/chisel/src/main/scala/shell/SimShell.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/SimShell.scala - diff]
hardware/chisel/src/main/scala/shell/VCR.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/VCR.scala - diff]
hardware/chisel/src/main/scala/shell/VME.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/VME.scala - diff]
hardware/chisel/src/main/scala/shell/VTAShell.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/VTAShell.scala - diff]
hardware/chisel/src/main/scala/shell/XilinxShell.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/shell/XilinxShell.scala - diff]
hardware/chisel/src/main/scala/test/Test.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/test/Test.scala - diff]
hardware/chisel/src/main/scala/util/Config.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/util/Config.scala - diff]
hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala - diff]
hardware/chisel/src/main/scala/vta/Configs.scala[Renamed from vta-hw/hardware/chisel/src/main/scala/vta/Configs.scala - diff]
hardware/chisel/src/test/scala/unittest/AluTest.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/AluTest.scala - diff]
hardware/chisel/src/test/scala/unittest/Launcher.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/Launcher.scala - diff]
hardware/chisel/src/test/scala/unittest/MvmTest.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/MvmTest.scala - diff]
hardware/chisel/src/test/scala/unittest/utils/Helper.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/utils/Helper.scala - diff]
hardware/chisel/src/test/scala/unittest/utils/RandomArray.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/utils/RandomArray.scala - diff]
hardware/chisel/src/test/scala/unittest/utils/TestRunner.scala[Renamed from vta-hw/hardware/chisel/src/test/scala/unittest/utils/TestRunner.scala - diff]
hardware/dpi/tsim_device.cc[Renamed from vta-hw/hardware/dpi/tsim_device.cc - diff]
hardware/intel/Makefile[Renamed from vta-hw/hardware/intel/Makefile - diff]
hardware/intel/README.md[Renamed from vta-hw/hardware/intel/README.md - diff]
hardware/intel/scripts/compile_design.tcl[Renamed from vta-hw/hardware/intel/scripts/compile_design.tcl - diff]
hardware/intel/scripts/de10_nano_top.v[Renamed from vta-hw/hardware/intel/scripts/de10_nano_top.v - diff]
hardware/intel/scripts/ip/vta/vta_hw.tcl[Renamed from vta-hw/hardware/intel/scripts/ip/vta/vta_hw.tcl - diff]
hardware/intel/scripts/set_attrs.py[Renamed from vta-hw/hardware/intel/scripts/set_attrs.py - diff]
hardware/intel/scripts/set_clocks.sdc[Renamed from vta-hw/hardware/intel/scripts/set_clocks.sdc - diff]
hardware/intel/scripts/soc_system.tcl[Renamed from vta-hw/hardware/intel/scripts/soc_system.tcl - diff]
hardware/xilinx/.gitignore[Renamed from vta-hw/hardware/xilinx/.gitignore - diff]
hardware/xilinx/Makefile[Renamed from vta-hw/hardware/xilinx/Makefile - diff]
hardware/xilinx/README.md[Renamed from vta-hw/hardware/xilinx/README.md - diff]
hardware/xilinx/scripts/hls.tcl[Renamed from vta-hw/hardware/xilinx/scripts/hls.tcl - diff]
hardware/xilinx/scripts/hsi.tcl[Renamed from vta-hw/hardware/xilinx/scripts/hsi.tcl - diff]
hardware/xilinx/scripts/vivado.tcl[Renamed from vta-hw/hardware/xilinx/scripts/vivado.tcl - diff]
hardware/xilinx/sim/vta_test.cc[Renamed from vta-hw/hardware/xilinx/sim/vta_test.cc - diff]
hardware/xilinx/src/vta.cc[Renamed from vta-hw/hardware/xilinx/src/vta.cc - diff]
hardware/xilinx/src/vta.h[Renamed from vta-hw/hardware/xilinx/src/vta.h - diff]
include/vta/dpi/module.h[Renamed from vta-hw/include/vta/dpi/module.h - diff]
include/vta/dpi/tsim.h[Renamed from vta-hw/include/vta/dpi/tsim.h - diff]
include/vta/driver.h[Renamed from vta-hw/include/vta/driver.h - diff]
include/vta/hw_spec.h[Renamed from vta-hw/include/vta/hw_spec.h - diff]
include/vta/sim_tlpp.h[Renamed from vta-hw/include/vta/sim_tlpp.h - diff]
python/vta/__init__.py[Deleted - diff]
python/vta/bitstream.py[Deleted - diff]
python/vta/build_module.py[Deleted - diff]
python/vta/environment.py[Deleted - diff]
python/vta/exec/__init__.py[Deleted - diff]
python/vta/exec/rpc_server.py[Deleted - diff]
python/vta/intrin.py[Deleted - diff]
python/vta/ir_pass.py[Deleted - diff]
python/vta/libinfo.py[Deleted - diff]
python/vta/program_bitstream.py[Deleted - diff]
python/vta/rpc_client.py[Deleted - diff]
python/vta/testing/__init__.py[Deleted - diff]
python/vta/testing/simulator.py[Deleted - diff]
python/vta/testing/util.py[Deleted - diff]
python/vta/top/__init__.py[Deleted - diff]
python/vta/top/bitpack.py[Deleted - diff]
python/vta/top/graphpack.py[Deleted - diff]
python/vta/top/op.py[Deleted - diff]
python/vta/top/util.py[Deleted - diff]
python/vta/top/vta_conv2d.py[Deleted - diff]
python/vta/top/vta_conv2d_transpose.py[Deleted - diff]
python/vta/top/vta_dense.py[Deleted - diff]
python/vta/top/vta_group_conv2d.py[Deleted - diff]
runtime/device_api.cc[Deleted - diff]
runtime/runtime.cc[Deleted - diff]
runtime/runtime.h[Deleted - diff]
scripts/tune_conv2d.py[Deleted - diff]
scripts/tune_conv2d_transpose.py[Deleted - diff]
scripts/tune_dense.py[Deleted - diff]
scripts/tune_group_conv2d.py[Deleted - diff]
scripts/tune_resnet.py[Deleted - diff]
src/de10nano/cma_api.cc[Renamed from vta-hw/src/de10nano/cma_api.cc - diff]
src/de10nano/cma_api.h[Renamed from vta-hw/src/de10nano/cma_api.h - diff]
src/de10nano/de10nano_driver.cc[Renamed from vta-hw/src/de10nano/de10nano_driver.cc - diff]
src/de10nano/de10nano_driver.h[Renamed from vta-hw/src/de10nano/de10nano_driver.h - diff]
src/de10nano/de10nano_mgr.h[Renamed from vta-hw/src/de10nano/de10nano_mgr.h - diff]
src/dpi/module.cc[Renamed from vta-hw/src/dpi/module.cc - diff]
src/pynq/pynq_driver.cc[Renamed from vta-hw/src/pynq/pynq_driver.cc - diff]
src/pynq/pynq_driver.h[Renamed from vta-hw/src/pynq/pynq_driver.h - diff]
src/sim/sim_driver.cc[Renamed from vta-hw/src/sim/sim_driver.cc - diff]
src/sim/sim_tlpp.cc[Renamed from vta-hw/src/sim/sim_tlpp.cc - diff]
src/tsim/tsim_driver.cc[Renamed from vta-hw/src/tsim/tsim_driver.cc - diff]
src/vmem/virtual_memory.cc[Renamed from vta-hw/src/vmem/virtual_memory.cc - diff]
src/vmem/virtual_memory.h[Renamed from vta-hw/src/vmem/virtual_memory.h - diff]
tests/hardware/common/test_lib.cc[Renamed from vta-hw/tests/hardware/common/test_lib.cc - diff]
tests/hardware/common/test_lib.h[Renamed from vta-hw/tests/hardware/common/test_lib.h - diff]
tests/hardware/metal_test/Makefile[Renamed from vta-hw/tests/hardware/metal_test/Makefile - diff]
tests/hardware/metal_test/metal_test.cc[Renamed from vta-hw/tests/hardware/metal_test/metal_test.cc - diff]
tests/python/de10nano/test_program_rpc.py[Deleted - diff]
tests/python/integration/test_benchmark_gemm.py[Deleted - diff]
tests/python/integration/test_benchmark_topi_conv2d.py[Deleted - diff]
tests/python/integration/test_benchmark_topi_conv2d_transpose.py[Deleted - diff]
tests/python/integration/test_benchmark_topi_dense.py[Deleted - diff]
tests/python/integration/test_benchmark_topi_group_conv2d.py[Deleted - diff]
tests/python/pynq/test_program_rpc.py[Deleted - diff]
tests/python/unittest/test_environment.py[Deleted - diff]
tests/python/unittest/test_vta_insn.py[Deleted - diff]
tutorials/README.txt[Deleted - diff]
tutorials/autotvm/README.txt[Deleted - diff]
tutorials/autotvm/tune_relay_vta.py[Deleted - diff]
tutorials/frontend/README.txt[Deleted - diff]
tutorials/frontend/deploy_classification.py[Deleted - diff]
tutorials/frontend/deploy_detection.py[Deleted - diff]
tutorials/matrix_multiply.py[Deleted - diff]
tutorials/optimize/README.txt[Deleted - diff]
tutorials/optimize/convolution_opt.py[Deleted - diff]
tutorials/optimize/matrix_multiply_opt.py[Deleted - diff]
tutorials/vta_get_started.py[Deleted - diff]

185 files changed

tree: 3ee5203e792c38300cd4212f7772795cf42bb452

README.md

VTA Hardware Design Stack

VTA (versatile tensor accelerator) is an open-source deep learning accelerator complemented with an end-to-end TVM-based compiler stack.

The key features of VTA include:

Generic, modular, open-source hardware
- Streamlined workflow to deploy to FPGAs.
- Simulator support to prototype compilation passes on regular workstations.
Driver and JIT runtime for both simulator and FPGA hardware back-end.
End-to-end TVM stack integration
- Direct optimization and deployment of models from deep learning frameworks via TVM.
- Customized and extensible TVM compiler back-end.
- Flexible RPC support to ease deployment, and program FPGAs with the convenience of Python.