commit 981bf2f32729b37b2ad302052d6c74c3734a17c9
author Luis Vega <vegaluisjose@users.noreply.github.com> Sun Aug 22 18:37:22 2021 -0700
committer GitHub <noreply@github.com> Sun Aug 22 18:37:22 2021 -0700
tree a5c5d5bb85f5e273a0074f624d9347f774bdb173
parent 3ec5f21a3c962c559d38f84a02a2ad15908664b4

fix types (#34)

hardware/chisel/Makefile

diff --git a/hardware/chisel/Makefile b/hardware/chisel/Makefile
index 0274c17..bbff447 100644
--- a/hardware/chisel/Makefile
+++ b/hardware/chisel/Makefile
@@ -63,7 +63,7 @@
 CXX_MAJOR := $(shell $(CXX) -dumpversion | sed 's/\..*//')
 CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true)
 
-config_test = $(TOP_TEST)$(CONFIG)
+CONFIG_TEST = $(TOP_TEST)$(CONFIG)
 
 
 ifndef TVM_PATH
@@ -182,16 +182,16 @@
 	$(CXX) $(ld_flags) $(cxx_flags) $(cxx_objs) $(patsubst %.cpp,%.cpp.o,$(shell find $(verilator_build_dir)/*.cpp)) -o $@
 
 verilator: $(verilator_build_dir)/V$(TOP_TEST).cpp
-$(verilator_build_dir)/V$(TOP_TEST).cpp: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
+$(verilator_build_dir)/V$(TOP_TEST).cpp: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv
 	verilator $(verilator_opt) $<
 
-verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).v
-$(chisel_build_dir)/$(TOP).$(CONFIG).v:
-	sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) --top-name $(TOP).$(CONFIG)'
+verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).sv
+$(chisel_build_dir)/$(TOP).$(CONFIG).sv:
+	sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) -o $(TOP).$(CONFIG)'
 
-verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
-$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v:
-	sbt 'runMain vta.$(config_test) --target-dir $(chisel_build_dir) --top-name $(TOP_TEST).$(CONFIG)'
+verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv
+$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv:
+	sbt 'runMain vta.$(CONFIG_TEST) --target-dir $(chisel_build_dir) -o $(TOP_TEST).$(CONFIG)'
 
 unittest:
 	sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)'

hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala

diff --git a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
index 73ae935..5c7c5ee 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
@@ -68,7 +68,7 @@
 class VTAHostDPI extends BlackBox with HasBlackBoxResource {
   val io = IO(new Bundle {
     val clock = Input(Clock())
-    val reset = Input(Bool())
+    val reset = Input(Reset())
     val dpi = new VTAHostDPIMaster
   })
   addResource("/verilog/VTAHostDPI.v")

hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala

diff --git a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
index c77bafd..c52260d 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
@@ -69,7 +69,7 @@
 class VTAMemDPI extends BlackBox with HasBlackBoxResource {
   val io = IO(new Bundle {
     val clock = Input(Clock())
-    val reset = Input(Bool())
+    val reset = Input(Reset())
     val dpi = new VTAMemDPIClient
   })
   addResource("/verilog/VTAMemDPI.v")

hardware/chisel/src/main/scala/dpi/VTASimDPI.scala

diff --git a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
index 96654d2..c2e7b6b 100644
--- a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
@@ -32,7 +32,7 @@
 class VTASimDPI extends BlackBox with HasBlackBoxResource {
   val io = IO(new Bundle {
     val clock = Input(Clock())
-    val reset = Input(Bool())
+    val reset = Input(Reset())
     val dpi_wait = Output(Bool())
   })
   addResource("/verilog/VTASimDPI.v")