tree 0f4ac9aaed6758f245d02abaf7adb56d02f6dfa5
parent 74f23fff285d4f57cad4afdb05e2bff08fd71f98
author Abhijit Davare <abhijit.davare@intel.com> 1623115601 -0700
committer GitHub <noreply@github.com> 1623115601 -0700
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Chisel Pipelined ALU  (#27)

* Remove parameter values from case class

* Add new blockOutFactor parameter with default value = 1

* Support split access

* Modify to support split interface, minor refactoring

* Use split read/write intefaces

* Pipelined ALU with split interfaces

* Modify instantiation and usage of pipelined ALU and split interfaces

* Don't use internal Random by default

* Change tester name

* Add generic tester class

* Derive from GenericTest, minor refactoring

* Test ALU index generator and pipelined ALU

* Add ASF header

* Bugfix: delay slicing index by a cycle to match SyncReadMem read delay

* Formatting, comment, and minor refactoring changes for clarity

* Fix scalastyle issues for test files