tree 5d9d565ccf1eebeabba5ef831c5a1f7d02a3ec2c
parent 495428cdb77493fb94a18a82cc9f26ceda2f65f9
author Pasquale Cocchini <61704028+pasqoc@users.noreply.github.com> 1583773753 -0700
committer GitHub <noreply@github.com> 1583773753 -0700

[VTA][Chisel,de10nano] Chisel fixes and de10nano support (#4986)

* [VTA][de10nano] Enable user defined target frequency.

Issue:
The VTA target frequency on the DE10-Nano is hardcoded to 50MHz
unnecessarily limiting performance.

Solution:
Add a PLL to the FPGA sub-system along with support for the
selection of a user specified frequency at build time. The board
successfully builds and runs at 100MHz.

* Added a PLL in the soc_system.tcl platform designer generator
  script.

* Modified the Makefile to automatically set the target frequency
  from that specified in the pkg_config.py file.

* Modified the Makefile to generate a bitstream with an RBF
  format that enables programming of the FPGA directly from
  the on-board processor. Specifically, the RBF is generated in
  FastParallel32 mode with compression, which corresponds to the
  default MSEL switch setting on the board, i.e. 01010.

* Added a false path override to file set_clocks.sdc to turn off
  unconstrained path warnings on the VTA pulse LED.

* [VTA][TSIM] Add more debug and tracing options.

* Modified Makefile to change default config to DafaultDe10Config.

* Added option in Makefile to produce more detailed tracing
  for extra observability in debugging complex scenarios.

* Added option in Makefile to produce traces in FST format which
  are 2 orders of magnitude smaller, although much slower to
  generate.

* Added option in Makefile to build the simulator with GCC address
  sanitizer.

* Modified Makefile to not lint the scala code by default avoiding
  unintended wrong indentation. Linting should be better performed
  manually on a per-need basis.

* [VTA][de10nano] Enable remote programming of FPGA.

Issue:
The Cyclone V FPGA on board of the DE10-Nano can only be programmed
using the JTAG port, which is a limiting option for users.

Solution:
Add support for the remote programming of the FPGA implementing
the FPGA programming manager protocol published in the Cyclone V
user manual.

* Added file de10nano_mgr.h implementing an FPGA manager class
  that supports handling of control and status registers as well
  as a push-button option to program the FPGA. The class can be
  easily extended to include more registers if needed.

* Used an instance of the FPGA manager to implement function
  VTAProgram also warning users when incompatible bitstream
  files are used.

* Registered VTAProgram as a global function and modified
  the program_bitstream python class to use it.

* [VTA][de10nano] Enhance de10nano runtime support.

Issue:
The de10nano target has incomplete, non-working support
for runtime reconfiguration, bitstream programming, and
examples of usage.

Solution:
Complete runtime support for the de10nano target.

* Modified VTA.cmake to comment out a default override for
  VTA_MAX_XFER to 21 bit wide.

* Modified VTA.cmake to add needed de10nano include dirs.

* Modified relevant files to support de10nano same way as
  other targets for VTA runtime reconfiguration and FPGA
  programming.

* Added test_program_rpc.py example as a runtime FPGA
  programming example. Note that unlike the pynq target
  no bitstream is either downloaded or programmed when
  the bitstream argument is set to None.

* Cosmetic changes to vta config files.

* [VTA][Chisel] LoadUop FSM bug fix.

Issue:
The LoadUop FSM incorrectly advances the address of the next
uop to read from DRAM when the DRAM data valid bit is deasserted
and asserted at the end of a read. This is caused by a mismatch
in the logic of the state and output portions of the FSM.
This is one of two issues that was gating the correct operation
of VTA on the DE10-Nano target.

Solution:
Modify the logic of the output section of the FSM to include
a check on the DRAM read valid bit or fold the output assignemnt
into the state section.

* Folded the assignemnt of the next uop address in the state
  section of the FSM.

* [VTA][Chisel] Dynamically adjust DMA tranfer size.

Issue:
In the DE10-Nano target and possibly in others, DMA transfers that
cross the boundaries of memory pages result in incorrect reads and
writes from and to DRAM. When this happens depending on different
input values, VTA loads and stores exhibit incorrect results for
DMA pulses at the end of a transfer. This is one of two issues that
were gating the DE10-Nano target from functioning correctly, but may
affect other Chisel based targets.

Solution:
Add support for dynamically adjustble DMA transfer sizes in load
and store operations. For a more elegant and modular implementation
the feature can be enabled at compile time with a static constant
that can be passed as a configuration option.

* Modified the load and store finite state machines to dynamically
  adjust the size of initial and stride DMA transfers. The feature
  is enabled by default by virtue of the static constant
  ADAPTIVE_DMA_XFER_ENABLE.

* [VTA][Chisel] Improve FSIM/TSIM/FPGA xref debug.

Issue:
Cross reference between FSIM, TSIM, and Chisel based FPGA traces
is an invaluable instrument that enables fast analysis on FSIM,
and analysis/debug on TSIM and FPGA, especially for complex flows
like conv2d or full inferences. Currently this cannot be done
easily since a suitable reference is missing. The clock cycle
event counter cannot be used since it is undefined in FSIM and
not reliable between TSIM and FPGA because of different latencies.

Solution:
Introduce a new event counter that preserves a program order across
FSIM, TSIM, FPGA. We propose adding the accumulator write event
counter in the Chisel EventCounter class and a simple instrumentation
in the FSIM runtime code. Note that this technique enabled finding the
Chisel issues reportes in the PR, which would have been otherwise
far more difficult.

* Added the acc_wr_count event counter and changed interfaces
  accordingly.

* [VTA][de10nano] Comply with linting rules.

* [VTA] Appease make lint.

* [VTA] Disable pylint import not top level error.

* [VTA][Chisel,de10nano] Linting changes.

* Use CamelCase class names.

* Use C++ style C include header files.

* Add comments to Chisel makefile.

* [VTA][de10nano]

* Reorder C and C++ includes in de10nano_mgr.h.

* Restore lint as default target in Chisel Makefile.

* [VTA][de10nano] Do not use f string in pkg_config.py.

* [VTA][de10nano] Remove overlooked f strings in pkg_config.py.

* [VTA][de10nano] Fixed typo.

* [VTA][TSIM] Check if gcc has align-new.

* [VTA][Chisel] Make adaptive DMA transfer default.

* [VTA][RPC] Renamed VTA_PYNQ_RPC_* to VTA_RPC_*.

Issue:
With more FPGA targets coming online the initial method of
using individual environment variables to specify target IP and port
does not scale well.

Solution:
Use a single VTA_RPC_HOST, VTA_RPC_PORT pair to be changed
every time a different target is used. For instance in a script
used to benchmark all targets.

* Replaced every instance of VTA_PYNQ_RPC_HOST and VTA_PYNQ_RPC_PORT
  with VTA_RPC_HOST and VTA_RPC_PORT, respectively.

* [VTA][Chisel] Comply with new linter.