{"version":3,"sources":["webpack:///./node_modules/react-syntax-highlighter/node_modules/highlight.js/lib/languages/vhdl.js"],"names":["module","exports","hljs","name","case_insensitive","keywords","keyword","built_in","literal","illegal","contains","C_BLOCK_COMMENT_MODE","COMMENT","QUOTE_STRING_MODE","className","begin","relevance","BACKSLASH_ESCAPE"],"mappings":"8EA6CAA,EAAOC,QAtCP,SAAcC,GAUZ,MAAO,CACLC,KAAM,OACNC,kBAAkB,EAClBC,SAAU,CACRC,QAAS,4vBACTC,SAAU,6SACVC,QAAS,8DAIXC,QAAS,IACTC,SAAU,CAACR,EAAKS,qBAChBT,EAAKU,QAAQ,KAAM,KAAMV,EAAKW,kBAAmB,CAC/CC,UAAW,SACXC,MAfY,8GAgBZC,UAAW,GACV,CACDF,UAAW,SACXC,MAAO,wBACPL,SAAU,CAACR,EAAKe,mBACf,CACDH,UAAW,SACXC,MAAO,4BACPL,SAAU,CAACR,EAAKe","file":"react-syntax-highlighter_languages_highlight_vhdl-8096a4935c4aa753b8fa.js","sourcesContent":["/*\nLanguage: VHDL\nAuthor: Igor Kalnitsky <igor@kalnitsky.org>\nContributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>\nDescription: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.\nWebsite: https://en.wikipedia.org/wiki/VHDL\n*/\nfunction vhdl(hljs) {\n  // Regular expression for VHDL numeric literals.\n  // Decimal literal:\n  var INTEGER_RE = '\\\\d(_|\\\\d)*';\n  var EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n  var DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?'; // Based literal:\n\n  var BASED_INTEGER_RE = '\\\\w+';\n  var BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n  var NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n  return {\n    name: 'VHDL',\n    case_insensitive: true,\n    keywords: {\n      keyword: 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' + 'begin block body buffer bus case component configuration constant context cover disconnect ' + 'downto default else elsif end entity exit fairness file for force function generate ' + 'generic group guarded if impure in inertial inout is label library linkage literal ' + 'loop map mod nand new next nor not null of on open or others out package parameter port ' + 'postponed procedure process property protected pure range record register reject ' + 'release rem report restrict restrict_guarantee return rol ror select sequence ' + 'severity shared signal sla sll sra srl strong subtype then to transport type ' + 'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',\n      built_in: 'boolean bit character ' + 'integer time delay_length natural positive ' + 'string bit_vector file_open_kind file_open_status ' + 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' + 'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' + 'real_vector time_vector',\n      literal: 'false true note warning error failure ' + // severity_level\n      'line text side width' // textio\n\n    },\n    illegal: '{',\n    contains: [hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.\n    hljs.COMMENT('--', '$'), hljs.QUOTE_STRING_MODE, {\n      className: 'number',\n      begin: NUMBER_RE,\n      relevance: 0\n    }, {\n      className: 'string',\n      begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n      contains: [hljs.BACKSLASH_ESCAPE]\n    }, {\n      className: 'symbol',\n      begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n      contains: [hljs.BACKSLASH_ESCAPE]\n    }]\n  };\n}\n\nmodule.exports = vhdl;"],"sourceRoot":""}