| {"version":3,"sources":["webpack:///./node_modules/react-syntax-highlighter/node_modules/highlight.js/lib/languages/verilog.js"],"names":["module","exports","hljs","name","aliases","case_insensitive","keywords","$pattern","keyword","literal","built_in","contains","C_BLOCK_COMMENT_MODE","C_LINE_COMMENT_MODE","QUOTE_STRING_MODE","className","BACKSLASH_ESCAPE","variants","begin","relevance","end"],"mappings":"8EAoDAA,EAAOC,QA7CP,SAAiBC,GAOf,MAAO,CACLC,KAAM,UACNC,QAAS,CAAC,IAAK,KAAM,OACrBC,kBAAkB,EAClBC,SAVgB,CAChBC,SAAU,UACVC,QAAS,83DACTC,QAAS,OACTC,SAAU,8hEAOVC,SAAU,CAACT,EAAKU,qBAAsBV,EAAKW,oBAAqBX,EAAKY,kBAAmB,CACtFC,UAAW,SACXJ,SAAU,CAACT,EAAKc,kBAChBC,SAAU,CAAC,CACTC,MAAO,kDACN,CACDA,MAAO,8CACN,CACDA,MAAO,eACPC,UAAW,KAIf,CACEJ,UAAW,WACXE,SAAU,CAAC,CACTC,MAAO,0BACN,CACDA,MAAO,UACPC,UAAW,KAEZ,CACDJ,UAAW,OACXG,MAAO,IACPE,IAAK,IACLd,SAAU,CACR,eAAgB,qOAElBa,UAAW","file":"react-syntax-highlighter_languages_highlight_verilog-1b6891c0e9b7ec3a6cc6.js","sourcesContent":["/*\nLanguage: Verilog\nAuthor: Jon Evans <jon@craftyjon.com>\nContributors: Boone Severson <boone.severson@gmail.com>\nDescription: Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.\nWebsite: http://www.verilog.com\n*/\nfunction verilog(hljs) {\n var SV_KEYWORDS = {\n $pattern: /[\\w\\$]+/,\n keyword: 'accept_on alias always always_comb always_ff always_latch and assert assign ' + 'assume automatic before begin bind bins binsof bit break buf|0 bufif0 bufif1 ' + 'byte case casex casez cell chandle checker class clocking cmos config const ' + 'constraint context continue cover covergroup coverpoint cross deassign default ' + 'defparam design disable dist do edge else end endcase endchecker endclass ' + 'endclocking endconfig endfunction endgenerate endgroup endinterface endmodule ' + 'endpackage endprimitive endprogram endproperty endspecify endsequence endtable ' + 'endtask enum event eventually expect export extends extern final first_match for ' + 'force foreach forever fork forkjoin function generate|5 genvar global highz0 highz1 ' + 'if iff ifnone ignore_bins illegal_bins implements implies import incdir include ' + 'initial inout input inside instance int integer interconnect interface intersect ' + 'join join_any join_none large let liblist library local localparam logic longint ' + 'macromodule matches medium modport module nand negedge nettype new nexttime nmos ' + 'nor noshowcancelled not notif0 notif1 or output package packed parameter pmos ' + 'posedge primitive priority program property protected pull0 pull1 pulldown pullup ' + 'pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos ' + 'real realtime ref reg reject_on release repeat restrict return rnmos rpmos rtran ' + 'rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared ' + 'sequence shortint shortreal showcancelled signed small soft solve specify specparam ' + 'static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on ' + 'sync_reject_on table tagged task this throughout time timeprecision timeunit tran ' + 'tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 ' + 'unsigned until until_with untyped use uwire var vectored virtual void wait wait_order ' + 'wand weak weak0 weak1 while wildcard wire with within wor xnor xor',\n literal: 'null',\n built_in: '$finish $stop $exit $fatal $error $warning $info $realtime $time $printtimescale ' + '$bitstoreal $bitstoshortreal $itor $signed $cast $bits $stime $timeformat ' + '$realtobits $shortrealtobits $rtoi $unsigned $asserton $assertkill $assertpasson ' + '$assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff ' + '$assertfailoff $assertvacuousoff $isunbounded $sampled $fell $changed $past_gclk ' + '$fell_gclk $changed_gclk $rising_gclk $steady_gclk $coverage_control ' + '$coverage_get $coverage_save $set_coverage_db_name $rose $stable $past ' + '$rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk $display ' + '$coverage_get_max $coverage_merge $get_coverage $load_coverage_db $typename ' + '$unpacked_dimensions $left $low $increment $clog2 $ln $log10 $exp $sqrt $pow ' + '$floor $ceil $sin $cos $tan $countbits $onehot $isunknown $fatal $warning ' + '$dimensions $right $high $size $asin $acos $atan $atan2 $hypot $sinh $cosh ' + '$tanh $asinh $acosh $atanh $countones $onehot0 $error $info $random ' + '$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson ' + '$dist_t $dist_uniform $q_initialize $q_remove $q_exam $async$and$array ' + '$async$nand$array $async$or$array $async$nor$array $sync$and$array ' + '$sync$nand$array $sync$or$array $sync$nor$array $q_add $q_full $psprintf ' + '$async$and$plane $async$nand$plane $async$or$plane $async$nor$plane ' + '$sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane $system ' + '$display $displayb $displayh $displayo $strobe $strobeb $strobeh $strobeo ' + '$write $readmemb $readmemh $writememh $value$plusargs ' + '$dumpvars $dumpon $dumplimit $dumpports $dumpportson $dumpportslimit ' + '$writeb $writeh $writeo $monitor $monitorb $monitorh $monitoro $writememb ' + '$dumpfile $dumpoff $dumpall $dumpflush $dumpportsoff $dumpportsall ' + '$dumpportsflush $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo ' + '$fstrobe $fstrobeb $fstrobeh $fstrobeo $swrite $swriteb $swriteh ' + '$swriteo $fscanf $fread $fseek $fflush $feof $fopen $fwrite $fwriteb ' + '$fwriteh $fwriteo $fmonitor $fmonitorb $fmonitorh $fmonitoro $sformat ' + '$sformatf $fgetc $ungetc $fgets $sscanf $rewind $ftell $ferror'\n };\n return {\n name: 'Verilog',\n aliases: ['v', 'sv', 'svh'],\n case_insensitive: false,\n keywords: SV_KEYWORDS,\n contains: [hljs.C_BLOCK_COMMENT_MODE, hljs.C_LINE_COMMENT_MODE, hljs.QUOTE_STRING_MODE, {\n className: 'number',\n contains: [hljs.BACKSLASH_ESCAPE],\n variants: [{\n begin: '\\\\b((\\\\d+\\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'\n }, {\n begin: '\\\\B((\\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'\n }, {\n begin: '\\\\b([0-9_])+',\n relevance: 0\n }]\n },\n /* parameters to instances */\n {\n className: 'variable',\n variants: [{\n begin: '#\\\\((?!parameter).+\\\\)'\n }, {\n begin: '\\\\.\\\\w+',\n relevance: 0\n }]\n }, {\n className: 'meta',\n begin: '`',\n end: '$',\n keywords: {\n 'meta-keyword': 'define __FILE__ ' + '__LINE__ begin_keywords celldefine default_nettype define ' + 'else elsif end_keywords endcelldefine endif ifdef ifndef ' + 'include line nounconnected_drive pragma resetall timescale ' + 'unconnected_drive undef undefineall'\n },\n relevance: 0\n }]\n }; // return\n}\n\nmodule.exports = verilog;"],"sourceRoot":""} |