arch/xtensa/src/esp32/bootloader/0001-esp32-Connect-Xtensa-Instruction-RAM1-to-Cache.patch

From 851a0b57377238386e8c786faeca422f6e11c911 Mon Sep 17 00:00:00 2001
From: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Date: Mon, 20 Mar 2023 11:16:52 -0300
Subject: [PATCH] esp32: Connect Xtensa Instruction RAM1 to Cache

User application image is executed with PID 5, so it accesses the
External Flash via virtual address starting from 0x40400000 (Vaddr2).

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
---
 components/bootloader_support/src/bootloader_utility.c | 2 ++
 components/hal/esp32/include/hal/mmu_ll.h              | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index 4e30ecad1b..15700a1c39 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -890,12 +890,14 @@ static void set_cache_and_start_app(
     cache_ll_l1_enable_bus(0, bus_mask);
     bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
     cache_ll_l1_enable_bus(0, bus_mask);
+    cache_ll_l1_enable_bus(0, CACHE_BUS_IBUS1);
 
 #if !CONFIG_FREERTOS_UNICORE
     bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
     cache_ll_l1_enable_bus(1, bus_mask);
     bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);
     cache_ll_l1_enable_bus(1, bus_mask);
+    cache_ll_l1_enable_bus(1, CACHE_BUS_IBUS1);
 #endif
 
     //----------------------Enable Cache----------------
diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h
index 8a572a5455..96609fe7ee 100644
--- a/components/hal/esp32/include/hal/mmu_ll.h
+++ b/components/hal/esp32/include/hal/mmu_ll.h
@@ -291,6 +291,15 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
     for (int i = 0; i < MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
+
+    /* Xtensa CPU does speculative load/store on VAddr1/2/3 when connected to cache.
+     * Hence it requires all the pages of VAddr2/3 to be set valid to any physical page.
+     * Marking any page invalid would stall the CPU.
+     */
+
+    for (int i = 64; i < 256; i++) {
+        mmu_ll_write_entry(mmu_id, i, 0, MMU_TARGET_FLASH0);
+    }
 }
 
 /**
-- 
2.37.2