Run indent.sh agains lpc2378 code
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2588 42af7a65-404d-4744-a932-0658087f49c3
diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h
index 6a557cf..3ea09d7 100755
--- a/arch/arm/include/lpc2378/irq.h
+++ b/arch/arm/include/lpc2378/irq.h
@@ -48,6 +48,7 @@
/****************************************************************************
* Included Files
****************************************************************************/
+
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
index e089d4d..42b6784 100755
--- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
@@ -107,7 +107,7 @@
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
#else
-static void lpc23xx_decodeirq( uint32_t *regs)
+static void lpc23xx_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
@@ -118,28 +118,30 @@
/* Check which IRQ fires */
- uint32_t irqbits = vic_getreg(VIC_IRQSTATUS_OFFSET) & 0xFFFFFFFF;
- unsigned int irq;
-
- for (irq = 0; irq < NR_IRQS; irq++)
- {
- if( irqbits & (uint32_t)(1<<irq) ) break;
- }
+ uint32_t irqbits = vic_getreg(VIC_IRQSTATUS_OFFSET) & 0xFFFFFFFF;
+ unsigned int irq;
+
+ for (irq = 0; irq < NR_IRQS; irq++)
+ {
+ if (irqbits & (uint32_t) (1 << irq))
+ break;
+ }
/* Verify that the resulting IRQ number is valid */
- if (irq < NR_IRQS) /* redundant check ?? */
+ if (irq < NR_IRQS) /* redundant check ?? */
{
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*/
+
DEBUGASSERT(current_regs == NULL);
current_regs = regs;
-
+
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
-
+
/* Deliver the IRQ */
irq_dispatch(irq, regs);
@@ -155,14 +157,15 @@
#ifdef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
{
- vic_vector_t vector = (vic_vector_t)vic_getreg(VIC_ADDRESS_OFFSET);
-
+ vic_vector_t vector = (vic_vector_t) vic_getreg(VIC_ADDRESS_OFFSET);
+
/* Mask and acknowledge the interrupt */
- up_maskack_irq(irq);
-
+ up_maskack_irq(irq);
+
/* Valid Interrupt */
- if(vector != NULL)
- (vector)(regs);
+
+ if (vector != NULL)
+ (vector) (regs);
}
#endif
diff --git a/arch/arm/src/lpc2378/lpc23xx_head.S b/arch/arm/src/lpc2378/lpc23xx_head.S
index eb3e1be..d9b5fdf 100755
--- a/arch/arm/src/lpc2378/lpc23xx_head.S
+++ b/arch/arm/src/lpc2378/lpc23xx_head.S
@@ -122,7 +122,6 @@
.long up_vectorfiq
.size _vector_table, . - _vector_table
-
/****************************************************************************
* OS Entry Point
****************************************************************************/
diff --git a/arch/arm/src/lpc2378/lpc23xx_io.c b/arch/arm/src/lpc2378/lpc23xx_io.c
index d87fddd..6f0474f 100755
--- a/arch/arm/src/lpc2378/lpc23xx_io.c
+++ b/arch/arm/src/lpc2378/lpc23xx_io.c
@@ -52,42 +52,50 @@
* Definitions
***********************************************************************/
-/******************************************************************************
-* Name: IO_Init()
+/***********************************************************************
+* Name: IO_Init()
*
-* Descriptions: Initialize the target board before running the main()
+* Descriptions: Initialize the target board before running the main()
*
-******************************************************************************/
+************************************************************************/
void IO_Init( void )
{
- uint32_t regval;
- /* Reset all GPIO pins to default */
- pinsel_putreg(0, PINSEL0_OFFSET);
- pinsel_putreg(0, PINSEL1_OFFSET);
- pinsel_putreg(0, PINSEL2_OFFSET);
- pinsel_putreg(0, PINSEL3_OFFSET);
- pinsel_putreg(0, PINSEL4_OFFSET);
- pinsel_putreg(0, PINSEL5_OFFSET);
- pinsel_putreg(0, PINSEL6_OFFSET);
- pinsel_putreg(0, PINSEL7_OFFSET);
- pinsel_putreg(0, PINSEL8_OFFSET);
- pinsel_putreg(0, PINSEL9_OFFSET);
- pinsel_putreg(0, PINSEL10_OFFSET);
- /*
- regval = scb_getreg(SCB_PCONP_OFFSET) & \
- ~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
- scb_getreg( regval, SCB_PCONP_OFFSET );
- */
- /* Turn off all peripheral power */
- scb_putreg( 0, SCB_PCONP_OFFSET );
-
- /* Turn on UART0/2 / Timer0 */
- //~ regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ;
- regval = PCUART0 | PCUART2 | PCTIM0 ;
- scb_putreg( regval , SCB_PCONP_OFFSET );
-
- /* Status LED P1.19 */
- dir_putreg8((1 << 3), FIO1DIR2_OFFSET);
- /* other io setup here */
- return;
+ uint32_t regval;
+
+ /* Reset all GPIO pins to default */
+
+ pinsel_putreg(0, PINSEL0_OFFSET);
+ pinsel_putreg(0, PINSEL1_OFFSET);
+ pinsel_putreg(0, PINSEL2_OFFSET);
+ pinsel_putreg(0, PINSEL3_OFFSET);
+ pinsel_putreg(0, PINSEL4_OFFSET);
+ pinsel_putreg(0, PINSEL5_OFFSET);
+ pinsel_putreg(0, PINSEL6_OFFSET);
+ pinsel_putreg(0, PINSEL7_OFFSET);
+ pinsel_putreg(0, PINSEL8_OFFSET);
+ pinsel_putreg(0, PINSEL9_OFFSET);
+ pinsel_putreg(0, PINSEL10_OFFSET);
+
+/*
+ regval = scb_getreg(SCB_PCONP_OFFSET) & ~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
+ scb_getreg(regval, SCB_PCONP_OFFSET );
+*/
+
+ /* Turn off all peripheral power */
+
+ scb_putreg(0, SCB_PCONP_OFFSET );
+
+ /* Turn on UART0/2 / Timer0 */
+ /* regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ; */
+
+ regval = PCUART0 | PCUART2 | PCTIM0 ;
+ scb_putreg(regval , SCB_PCONP_OFFSET );
+
+ /* Status LED P1.19 */
+
+ dir_putreg8((1 << 3), FIO1DIR2_OFFSET);
+
+ /* other io setup here */
+
+ return;
}
diff --git a/arch/arm/src/lpc2378/lpc23xx_irq.c b/arch/arm/src/lpc2378/lpc23xx_irq.c
index 38e058e..9a6268a 100755
--- a/arch/arm/src/lpc2378/lpc23xx_irq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_irq.c
@@ -85,23 +85,25 @@
void up_irqinitialize(void)
{
- int reg;
+ int reg;
/* Disable all interrupts. We do this by writing ones to the IntClearEnable
* register.
*/
+
vic_putreg(0xffffffff, VIC_INTENCLEAR_OFFSET);
/* Select all IRQs, FIQs are not used */
+
vic_putreg(0, VIC_INTSELECT_OFFSET);
/* Clear priority interrupts */
for (reg = 0; reg < NR_IRQS; reg++)
- {
- vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
- vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
- }
+ {
+ vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
+ vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
+ }
/* currents_regs is non-NULL only while processing an interrupt */
@@ -113,25 +115,29 @@
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
+
/***********************************************************************
* Name: up_enable_irq_protect
* VIC registers can be accessed in User or privileged mode
***********************************************************************/
+
static void up_enable_irq_protect(void)
{
- //~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
- //~ reg32 &= ~(0xFFFFFFFF);
- vic_putreg(0x01, VIC_PROTECTION_OFFSET);
+ // ~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
+ // ~ reg32 &= ~(0xFFFFFFFF);
+ vic_putreg(0x01, VIC_PROTECTION_OFFSET);
}
/***********************************************************************
* Name: up_disable_irq_protect
* VIC registers can only be accessed in privileged mode
***********************************************************************/
+
static void up_disable_irq_protect(void)
{
- vic_putreg(0, VIC_PROTECTION_OFFSET);
+ vic_putreg(0, VIC_PROTECTION_OFFSET);
}
+
/***********************************************************************
* Name: up_disable_irq
*
@@ -146,8 +152,8 @@
if (irq < NR_IRQS)
{
- /* Disable the irq by setting the corresponding bit in the VIC
- * Interrupt Enable Clear register.
+ /* Disable the irq by setting the corresponding bit in the VIC Interrupt
+ * Enable Clear register.
*/
vic_putreg((1 << irq), VIC_INTENCLEAR_OFFSET);
@@ -172,8 +178,8 @@
irqstate_t flags = irqsave();
- /* Enable the irq by setting the corresponding bit in the VIC
- * Interrupt Enable register.
+ /* Enable the irq by setting the corresponding bit in the VIC Interrupt
+ * Enable register.
*/
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
@@ -196,16 +202,21 @@
if ((unsigned)irq < NR_IRQS)
{
- /* Mask the IRQ by clearing the associated bit in Software Priority Mask register */
- reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
- reg32 &= ~(1 << irq);
- vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
+ /* Mask the IRQ by clearing the associated bit in Software Priority Mask
+ * register
+ */
+
+ reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
+ reg32 &= ~(1 << irq);
+ vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
}
- /* Clear interrupt */
- vic_putreg((1<<irq), VIC_SOFTINTCLEAR_OFFSET);
+
+ /* Clear interrupt */
+
+ vic_putreg((1 << irq), VIC_SOFTINTCLEAR_OFFSET);
#ifdef CONFIG_VECTORED_INTERRUPTS
- vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
-#endif
+ vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
+#endif
}
/****************************************************************************
@@ -218,13 +229,13 @@
int up_prioritize_irq(int irq, int priority)
{
- /* The default priority on reset is 16 */
- if (irq < NR_IRQS && priority > 0 && priority < 16)
- {
- int offset = irq << 2;
- vic_putreg( priority, VIC_VECTPRIORITY0_OFFSET + offset );
- return OK;
- }
+ /* The default priority on reset is 16 */
+ if (irq < NR_IRQS && priority > 0 && priority < 16)
+ {
+ int offset = irq << 2;
+ vic_putreg(priority, VIC_VECTPRIORITY0_OFFSET + offset);
+ return OK;
+ }
return -EINVAL;
}
@@ -251,17 +262,17 @@
/* Save the vector address */
- vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
-
- /* Set the interrupt priority */
-
+ vic_putreg((uint32_t) handler, VIC_VECTADDR0_OFFSET + offset);
+
+ /* Set the interrupt priority */
+
up_prioritize_irq(irq, vector);
-
+
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
-
+
irqrestore(flags);
}
}
diff --git a/arch/arm/src/lpc2378/lpc23xx_pllsetup.c b/arch/arm/src/lpc2378/lpc23xx_pllsetup.c
index d7a08b5..b11658f 100755
--- a/arch/arm/src/lpc2378/lpc23xx_pllsetup.c
+++ b/arch/arm/src/lpc2378/lpc23xx_pllsetup.c
@@ -71,22 +71,24 @@
#include "lpc23xx_scb.h"
extern void IO_Init(void);
+
/***********************************************************************
* Definitions
**********************************************************************/
+
#if ((FOSC < 32000) || (FOSC > 50000000))
-# error Fosc out of range (32KHz-50MHz)
-# error correct and recompile
+# error Fosc out of range (32KHz-50MHz)
+# error correct and recompile
#endif
#if ((CCLK < 10000000) || (CCLK > 72000000))
-# error cclk out of range (10MHz-72MHz)
-# error correct PLL MULTIPLIER and recompile
+# error cclk out of range (10MHz-72MHz)
+# error correct PLL MULTIPLIER and recompile
#endif
#if ((FCCO < 275000000) || (FCCO > 550000000))
-# error Fcco out of range (275MHz-550MHz)
-# error internal algorithm error
+# error Fcco out of range (275MHz-550MHz)
+# error internal algorithm error
#endif
/* Phase Locked Loop (PLL) initialization values
@@ -95,23 +97,25 @@
* CCLK = 57 600 000 Hz
* Bit 16:23 NSEL: PLL Divider "N" Value
* Fcco = (2 * M * F_in) / N
- * 275MHz <= Fcco <= 550MHz
+ * 275MHz <= Fcco <= 550MHz
*
* PLL clock sources:
- * Internal RC 0 default on reset
- * Main Oscillator 1
- * RTC 2
+ * Internal RC 0 default on reset
+ * Main Oscillator 1
+ * RTC 2
*/
+
#ifdef CONFIG_PLL_CLKSRC
-# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
-# error "PLL clock source not valid, check configuration "
-# endif
+# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
+# error "PLL clock source not valid, check configuration "
+# endif
#else
-# error "PLL clock source not defined, check configuration file"
+# error "PLL clock source not defined, check configuration file"
#endif
/* PLL provides CCLK and must always be configured */
-#define PLL ( PLL_M | (PLL_N << 16) )
+
+#define PLL ( PLL_M | (PLL_N << 16) )
/* Memory Accelerator Module (MAM) initialization values
*
@@ -131,108 +135,108 @@
* 6 = 6 CCLK
* 7 = 7 CCLK
*/
-/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
-#ifdef CONFIG_MAM_SETUP
-# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
-# define CONFIG_MAMCR_VALUE (MAMCR_PART)
-# endif
-# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
-# define CONFIG_MAMTIM_VALUE (0x00000003)
-# endif
+/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
+
+#ifdef CONFIG_MAM_SETUP
+# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
+# define CONFIG_MAMCR_VALUE (MAMCR_PART)
+# endif
+
+# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
+# define CONFIG_MAMTIM_VALUE (0x00000003)
+# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
-
/****************************************************************************
* Name: up_scbpllfeed
****************************************************************************/
+
static inline void up_scbpllfeed(void)
{
- SCB_PLLFEED = 0xAA;
- SCB_PLLFEED = 0x55;
+ SCB_PLLFEED = 0xAA;
+ SCB_PLLFEED = 0x55;
}
/****************************************************************************
* Name: ConfigurePLL
****************************************************************************/
-void ConfigurePLL ( void )
+
+void ConfigurePLL(void)
{
- uint32_t MSel, NSel;
-
- /* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
- SCB_PCONP |= PCENET;
-
- /* Vectors are remapped to Flash */
- SCB_MEMMAP = MEMMAP2FLASH;
-
- /* Enable PLL, disconnected */
- if(SCB_PLLSTAT & (1 << 25))
- {
- SCB_PLLCON = 0x01;
- up_scbpllfeed();
- }
+ uint32_t MSel, NSel;
- /* Disable PLL, disconnected */
- SCB_PLLCON = 0;
- up_scbpllfeed();
+ /* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
+ SCB_PCONP |= PCENET;
- /* Enable main OSC */
- SCB_SCS |= 0x20;
+ /* Vectors are remapped to Flash */
+ SCB_MEMMAP = MEMMAP2FLASH;
- /* Wait until main OSC is usable */
- while( !(SCB_SCS & 0x40) );
+ /* Enable PLL, disconnected */
+ if (SCB_PLLSTAT & (1 << 25))
+ {
+ SCB_PLLCON = 0x01;
+ up_scbpllfeed();
+ }
+ /* Disable PLL, disconnected */
+ SCB_PLLCON = 0;
+ up_scbpllfeed();
- /* select main OSC, 12MHz, as the PLL clock source */
- SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
+ /* Enable main OSC */
+ SCB_SCS |= 0x20;
- /* Reconfigure PLL */
- SCB_PLLCFG = PLL;
- up_scbpllfeed();
+ /* Wait until main OSC is usable */
+ while (!(SCB_SCS & 0x40));
+ /* select main OSC, 12MHz, as the PLL clock source */
+ SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
- /* Enable PLL */
- SCB_PLLCON = 0x01;
- up_scbpllfeed();
+ /* Reconfigure PLL */
+ SCB_PLLCFG = PLL;
+ up_scbpllfeed();
- /* Set clock divider */
- SCB_CCLKCFG = CCLK_DIV;
+ /* Enable PLL */
+ SCB_PLLCON = 0x01;
+ up_scbpllfeed();
+ /* Set clock divider */
+ SCB_CCLKCFG = CCLK_DIV;
#ifdef CONFIG_USBDEV
- /* usbclk = 288 MHz/6 = 48 MHz */
- SCB_USBCLKCFG = USBCLK_DIV;
- /* Turn On USB PCLK */
- SCB_PCONP |= PCUSB;
+ /* usbclk = 288 MHz/6 = 48 MHz */
+ SCB_USBCLKCFG = USBCLK_DIV;
+ /* Turn On USB PCLK */
+ SCB_PCONP |= PCUSB;
#endif
- /* Wait for PLL to lock */
- while( ( SCB_PLLSTAT & (1 << 26) ) == 0);
+ /* Wait for PLL to lock */
+ while ((SCB_PLLSTAT & (1 << 26)) == 0);
- MSel = SCB_PLLSTAT & 0x00007FFF;
- NSel = ( SCB_PLLSTAT & 0x00FF0000 ) >> 16;
- while( (MSel != PLL_M) && (NSel != PLL_N) );
-
- /* Enable and connect */
- SCB_PLLCON = 0x03;
- up_scbpllfeed();
-
- /* Check connect bit status */
- while( ( SCB_PLLSTAT & ( 1 << 25 ) ) == 0 );
+ MSel = SCB_PLLSTAT & 0x00007FFF;
+ NSel = (SCB_PLLSTAT & 0x00FF0000) >> 16;
+ while ((MSel != PLL_M) && (NSel != PLL_N));
- /* Set memory accelerater module*/
- SCB_MAMCR = 0;
- SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
- SCB_MAMCR = CONFIG_MAMCR_VALUE;
+ /* Enable and connect */
+ SCB_PLLCON = 0x03;
+ up_scbpllfeed();
- /* Enable FastIO on P0:P1 */
- SCB_SCS |= 0x01;
-
- IO_Init();
-
- return;
+ /* Check connect bit status */
+ while ((SCB_PLLSTAT & (1 << 25)) == 0);
+
+ /* Set memory accelerater module */
+ SCB_MAMCR = 0;
+ SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
+ SCB_MAMCR = CONFIG_MAMCR_VALUE;
+
+ /* Enable FastIO on P0:P1 */
+ SCB_SCS |= 0x01;
+
+ IO_Init();
+
+ return;
}
diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c
index b627613..7590c7c 100755
--- a/arch/arm/src/lpc2378/lpc23xx_serial.c
+++ b/arch/arm/src/lpc2378/lpc23xx_serial.c
@@ -79,13 +79,13 @@
struct up_dev_s
{
- uint32_t uartbase; /* Base address of UART registers */
- uint32_t baud; /* Configured baud */
- uint8_t ier; /* Saved IER value */
- uint8_t irq; /* IRQ associated with this UART */
- uint8_t parity; /* 0=none, 1=odd, 2=even */
- uint8_t bits; /* Number of bits (7 or 8) */
- bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+ uint32_t uartbase; /* Base address of UART registers */
+ uint32_t baud; /* Configured baud */
+ uint8_t ier; /* Saved IER value */
+ uint8_t irq; /* IRQ associated with this UART */
+ uint8_t parity; /* 0=none, 1=odd, 2=even */
+ uint8_t bits; /* Number of bits (7 or 8) */
+ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
};
/****************************************************************************
@@ -98,7 +98,7 @@
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
-static int up_receive(struct uart_dev_s *dev, uint32_t *status);
+static int up_receive(struct uart_dev_s *dev, uint32_t * status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -112,18 +112,18 @@
struct uart_ops_s g_uart_ops =
{
- .setup = up_setup,
- .shutdown = up_shutdown,
- .attach = up_attach,
- .detach = up_detach,
- .ioctl = up_ioctl,
- .receive = up_receive,
- .rxint = up_rxint,
- .rxavailable = up_rxavailable,
- .send = up_send,
- .txint = up_txint,
- .txready = up_txready,
- .txempty = up_txempty,
+ .setup = up_setup,
+ .shutdown = up_shutdown,
+ .attach = up_attach,
+ .detach = up_detach,
+ .ioctl = up_ioctl,
+ .receive = up_receive,
+ .rxint = up_rxint,
+ .rxavailable = up_rxavailable,
+ .send = up_send,
+ .txint = up_txint,
+ .txready = up_txready,
+ .txempty = up_txempty,
};
/* I/O buffers */
@@ -134,65 +134,68 @@
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
/* This describes the state of the LPC214X uart0 port. */
+
#ifdef CONFIG_UART0
static struct up_dev_s g_uart0priv =
{
- .uartbase = UART0_BASE_ADDR,
- .baud = CONFIG_UART0_BAUD,
- .irq = UART0_IRQ,
- .parity = CONFIG_UART0_PARITY,
- .bits = CONFIG_UART0_BITS,
- .stopbits2 = CONFIG_UART0_2STOP,
+ .uartbase = UART0_BASE_ADDR,
+ .baud = CONFIG_UART0_BAUD,
+ .irq = UART0_IRQ,
+ .parity = CONFIG_UART0_PARITY,
+ .bits = CONFIG_UART0_BITS,
+ .stopbits2 = CONFIG_UART0_2STOP,
};
static uart_dev_t g_uart0port =
{
- .recv =
+ .recv =
{
- .size = CONFIG_UART0_RXBUFSIZE,
- .buffer = g_uart0rxbuffer,
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0rxbuffer,
},
- .xmit =
+ .xmit =
{
- .size = CONFIG_UART0_TXBUFSIZE,
- .buffer = g_uart0txbuffer,
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0txbuffer,
},
- .ops = &g_uart_ops,
- .priv = &g_uart0priv,
- };
+ .ops = &g_uart_ops,
+ .priv = &g_uart0priv,
+};
#endif
#ifdef CONFIG_UART2
+
/* This describes the state of the LPC23XX uart2 port. */
static struct up_dev_s g_uart2priv =
{
- .uartbase = UART2_BASE_ADDR,
- .baud = CONFIG_UART2_BAUD,
- .irq = UART2_IRQ,
- .parity = CONFIG_UART2_PARITY,
- .bits = CONFIG_UART2_BITS,
- .stopbits2 = CONFIG_UART2_2STOP,
+ .uartbase = UART2_BASE_ADDR,
+ .baud = CONFIG_UART2_BAUD,
+ .irq = UART2_IRQ,
+ .parity = CONFIG_UART2_PARITY,
+ .bits = CONFIG_UART2_BITS,
+ .stopbits2 = CONFIG_UART2_2STOP,
};
static uart_dev_t g_uart2port =
{
- .recv =
+ .recv =
{
- .size = CONFIG_UART2_RXBUFSIZE,
- .buffer = g_uart2rxbuffer,
+ .size = CONFIG_UART2_RXBUFSIZE,
+ .buffer = g_uart2rxbuffer,
},
- .xmit =
+ .xmit =
{
- .size = CONFIG_UART2_TXBUFSIZE,
- .buffer = g_uart2txbuffer,
+ .size = CONFIG_UART2_TXBUFSIZE,
+ .buffer = g_uart2txbuffer,
},
- .ops = &g_uart_ops,
- .priv = &g_uart2priv,
- };
+ .ops = &g_uart_ops,
+ .priv = &g_uart2priv,
+};
#endif
+
/* Now, which one with be tty0/console and which tty1? */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
@@ -217,7 +220,7 @@
static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
{
- return getreg8(priv->uartbase + offset);
+ return getreg8(priv->uartbase + offset);
}
/****************************************************************************
@@ -226,22 +229,22 @@
static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
{
- putreg8(value, priv->uartbase + offset);
+ putreg8(value, priv->uartbase + offset);
}
/****************************************************************************
* Name: up_disableuartint
****************************************************************************/
-static inline void up_disableuartint(struct up_dev_s *priv, uint8_t *ier)
+static inline void up_disableuartint(struct up_dev_s *priv, uint8_t * ier)
{
- if (ier)
+ if (ier)
{
- *ier = priv->ier & IER_ALLIE;
+ *ier = priv->ier & IER_ALLIE;
}
- priv->ier &= ~IER_ALLIE;
- up_serialout(priv, UART_IER_OFFSET, priv->ier);
+ priv->ier &= ~IER_ALLIE;
+ up_serialout(priv, UART_IER_OFFSET, priv->ier);
}
/****************************************************************************
@@ -250,8 +253,8 @@
static inline void up_restoreuartint(struct up_dev_s *priv, uint8_t ier)
{
- priv->ier |= ier & IER_ALLIE;
- up_serialout(priv, UART_IER_OFFSET, priv->ier);
+ priv->ier |= ier & IER_ALLIE;
+ up_serialout(priv, UART_IER_OFFSET, priv->ier);
}
/****************************************************************************
@@ -260,16 +263,19 @@
static inline void up_waittxready(struct up_dev_s *priv)
{
- int tmp;
+ int tmp;
- /* Limit how long we will wait for the TX available condition */
- for (tmp = 1000 ; tmp > 0 ; tmp--)
+ /* Limit how long we will wait for the TX available condition */
+
+ for (tmp = 1000; tmp > 0; tmp--)
{
- /* Check if the tranmitter holding register (THR) is empty */
- if ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0)
+ /* Check if the tranmitter holding register (THR) is empty */
+
+ if ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0)
{
- /* The THR is empty, return */
- break;
+ /* The THR is empty, return */
+
+ break;
}
}
}
@@ -280,16 +286,16 @@
static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
{
- uint8_t lcr = up_serialin(priv, UART_LCR_OFFSET);
- if (enable)
+ uint8_t lcr = up_serialin(priv, UART_LCR_OFFSET);
+ if (enable)
{
- lcr |= LCR_BREAK_ENABLE;
+ lcr |= LCR_BREAK_ENABLE;
}
- else
+ else
{
- lcr &= ~LCR_BREAK_ENABLE;
+ lcr &= ~LCR_BREAK_ENABLE;
}
- up_serialout(priv, UART_LCR_OFFSET, lcr);
+ up_serialout(priv, UART_LCR_OFFSET, lcr);
}
/****************************************************************************
@@ -298,113 +304,112 @@
static inline void up_configbaud(struct up_dev_s *priv)
{
- /* In a buckled-up, embedded system, there is no reason to constantly
- * calculate the following. The calculation can be skipped if the
- * MULVAL, DIVADDVAL, and DIVISOR values are provided in the configuration
- * file.
- */
+ /* In a buckled-up, embedded system, there is no reason to constantly
+ * calculate the following. The calculation can be skipped if the MULVAL,
+ * DIVADDVAL, and DIVISOR values are provided in the configuration file.
+ */
#ifndef CONFIG_UART_MULVAL
- uint32_t qtrclk;
+ uint32_t qtrclk;
- /* Test values calculated for every multiplier/divisor combination */
+ /* Test values calculated for every multiplier/divisor combination */
- uint32_t tdiv;
- uint32_t terr;
- int tmulval;
- int tdivaddval;
+ uint32_t tdiv;
+ uint32_t terr;
+ int tmulval;
+ int tdivaddval;
- /* Optimal multiplier/divider values */
+ /* Optimal multiplier/divider values */
- uint32_t div = 0;
- uint32_t err = 100000;
- int mulval = 1;
- int divaddval = 0;
+ uint32_t div = 0;
+ uint32_t err = 100000;
+ int mulval = 1;
+ int divaddval = 0;
- /* Baud is generated using FDR and DLL-DLM registers
- *
- * baud = clock * (mulval/(mulval+divaddval) / (16 * div)
- *
- * Or
- *
- * div = (clock/16) * (mulval/(mulval+divaddval) / baud
- *
- * Where mulval = Fractional divider multiplier
- * divaddval = Fractional divider pre-scale div
- * div = DLL-DLM divisor
- */
+ /* Baud is generated using FDR and DLL-DLM registers
+ *
+ * baud = clock * (mulval/(mulval+divaddval) / (16 * div)
+ *
+ * Or
+ *
+ * div = (clock/16) * (mulval/(mulval+divaddval) / baud
+ *
+ * Where mulval = Fractional divider multiplier
+ * divaddval = Fractional divider pre-scale div
+ * div = DLL-DLM divisor
+ */
- /* Get UART block clock divided by 16 */
+ /* Get UART block clock divided by 16 */
- qtrclk = U0_PCLK >> 4; /* TODO: Different Uart port with different clocking */
+ qtrclk = U0_PCLK >> 4; /* TODO: Different Uart port with different clocking */
- /* Try every valid multiplier, tmulval (or until a perfect
- * match is found).
- */
+ /* Try every valid multiplier, tmulval (or until a perfect match is found). */
- for (tmulval = 1 ; tmulval <= 15 && err > 0; tmulval++)
+ for (tmulval = 1; tmulval <= 15 && err > 0; tmulval++)
{
- /* Try every valid pre-scale div, tdivaddval (or until a perfect
- * match is found).
- */
+ /* Try every valid pre-scale div, tdivaddval (or until a perfect match is
+ * found).
+ */
- for (tdivaddval = 0 ; tdivaddval <= 15 && err > 0; tdivaddval++)
+ for (tdivaddval = 0; tdivaddval <= 15 && err > 0; tdivaddval++)
{
- /* Calculate the divisor with these fractional divider settings */
+ /* Calculate the divisor with these fractional divider settings */
- uint32_t tmp = (tmulval * qtrclk) / ((tmulval + tdivaddval));
- tdiv = (tmp + (priv->baud >>1)) / priv->baud;
+ uint32_t tmp = (tmulval * qtrclk) / ((tmulval + tdivaddval));
+ tdiv = (tmp + (priv->baud >> 1)) / priv->baud;
- /* Check if this candidate divisor is within a valid range */
+ /* Check if this candidate divisor is within a valid range */
- if (tdiv > 2 && tdiv < 0x10000)
+ if (tdiv > 2 && tdiv < 0x10000)
{
- /* Calculate the actual baud and the error */
+ /* Calculate the actual baud and the error */
- uint32_t actualbaud = tmp / tdiv;
+ uint32_t actualbaud = tmp / tdiv;
- if (actualbaud <= priv->baud)
+ if (actualbaud <= priv->baud)
{
- terr = priv->baud - actualbaud;
+ terr = priv->baud - actualbaud;
}
- else
+ else
{
- terr = actualbaud - priv->baud;
+ terr = actualbaud - priv->baud;
}
- /* Is this the smallest error we have encountered? */
+ /* Is this the smallest error we have encountered? */
- if (terr < err)
+ if (terr < err)
{
- /* Yes, save these settings as the new, candidate optimal settings */
+ /* Yes, save these settings as the new, candidate optimal
+ * settings
+ */
- mulval = tmulval ;
- divaddval = tdivaddval;
- div = tdiv;
- err = terr;
+ mulval = tmulval;
+ divaddval = tdivaddval;
+ div = tdiv;
+ err = terr;
}
}
}
}
- /* Configure the MS and LS DLAB registers */
+ /* Configure the MS and LS DLAB registers */
- up_serialout(priv, UART_DLM_OFFSET, div >> 8);
- up_serialout(priv, UART_DLL_OFFSET, div & 0xff);
+ up_serialout(priv, UART_DLM_OFFSET, div >> 8);
+ up_serialout(priv, UART_DLL_OFFSET, div & 0xff);
- /* Configure the Fractional Divider Register (FDR) */
+ /* Configure the Fractional Divider Register (FDR) */
- up_serialout(priv, UART_FDR_OFFSET, ((mulval << 4) | divaddval) );
+ up_serialout(priv, UART_FDR_OFFSET, ((mulval << 4) | divaddval));
#else
- /* Configure the MS and LS DLAB registers */
- up_serialout(priv, UART_DLM_OFFSET, DLMVAL >> 8);
- up_serialout(priv, UART_DLL_OFFSET, DLLVAL & 0xff);
+ /* Configure the MS and LS DLAB registers */
+ up_serialout(priv, UART_DLM_OFFSET, DLMVAL >> 8);
+ up_serialout(priv, UART_DLL_OFFSET, DLLVAL & 0xff);
- /* Configure the Fractional Divider Register (FDR) */
+ /* Configure the Fractional Divider Register (FDR) */
- up_serialout(priv, UART_FDR_OFFSET, ((MULVAL << 4) | DIVADDVAL) );
+ up_serialout(priv, UART_FDR_OFFSET, ((MULVAL << 4) | DIVADDVAL));
#endif
}
@@ -422,70 +427,68 @@
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_LPC214X_UART_CONFIG
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- uint8_t lcr;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint8_t lcr;
- /* Clear fifos */
+ /* Clear fifos */
- up_serialout(priv, UART_FCR_OFFSET,
- (FCR_RX_FIFO_RESET|FCR_TX_FIFO_RESET));
+ up_serialout(priv, UART_FCR_OFFSET, (FCR_RX_FIFO_RESET | FCR_TX_FIFO_RESET));
- /* Set trigger */
+ /* Set trigger */
- up_serialout(priv, UART_FCR_OFFSET,
- (FCR_FIFO_ENABLE|FCR_FIFO_TRIG14));
+ up_serialout(priv, UART_FCR_OFFSET, (FCR_FIFO_ENABLE | FCR_FIFO_TRIG14));
- /* Set up the IER */
+ /* Set up the IER */
- priv->ier = up_serialin(priv, UART_IER_OFFSET);
+ priv->ier = up_serialin(priv, UART_IER_OFFSET);
- /* Set up the Line Control Register */
+ /* Set up the Line Control Register */
- lcr = 0;
+ lcr = 0;
- lcr |= (priv->bits == 7) ? LCR_CHAR_7 : LCR_CHAR_8;
+ lcr |= (priv->bits == 7) ? LCR_CHAR_7 : LCR_CHAR_8;
- if (priv->stopbits2)
+ if (priv->stopbits2)
{
- lcr |= LCR_STOP_2;
+ lcr |= LCR_STOP_2;
}
- if (priv->parity == 1)
+ if (priv->parity == 1)
{
- lcr |= LCR_PAR_ODD;
+ lcr |= LCR_PAR_ODD;
}
- else if (priv->parity == 2)
+ else if (priv->parity == 2)
{
- lcr |= LCR_PAR_EVEN;
+ lcr |= LCR_PAR_EVEN;
}
- /* Enable access to latch divisor DLAB=1 */
+ /* Enable access to latch divisor DLAB=1 */
- up_serialout( priv, UART_LCR_OFFSET, (lcr | LCR_DLAB_ENABLE) );
+ up_serialout(priv, UART_LCR_OFFSET, (lcr | LCR_DLAB_ENABLE));
- /* find values for DLL, DLM, DIVADDVAL, MULVAL */
+ /* find values for DLL, DLM, DIVADDVAL, MULVAL */
- up_configbaud(priv);
+ up_configbaud(priv);
- /* Disable access to latch divisor Clear DLAB */
+ /* Disable access to latch divisor Clear DLAB */
- up_serialout(priv, UART_LCR_OFFSET, lcr);
+ up_serialout(priv, UART_LCR_OFFSET, lcr);
- /* Configure the FIFOs */
+ /* Configure the FIFOs */
- up_serialout(priv, UART_FCR_OFFSET,
- (FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET | \
- FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE));
+ up_serialout(priv, UART_FCR_OFFSET,
+ (FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET |
+ FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE));
- /* The NuttX serial driver waits for the first THRE interrrupt before
- * sending serial data... However, it appears that the LPC2378 hardware too
- * does not generate that interrupt until a transition from not-empty
- * to empty. So, the current kludge here is to send one NULL at
- * startup to kick things off.
- */
- up_serialout(priv, UART_THR_OFFSET, '\0');
+ /* The NuttX serial driver waits for the first THRE interrrupt before sending
+ * serial data... However, it appears that the LPC2378 hardware too does not
+ * generate that interrupt until a transition from not-empty to empty. So,
+ * the current kludge here is to send one NULL at startup to kick things off.
+ */
+
+ up_serialout(priv, UART_THR_OFFSET, '\0');
#endif
- return OK;
+ return OK;
}
/****************************************************************************
@@ -499,8 +502,8 @@
static void up_shutdown(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- up_disableuartint(priv, NULL);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ up_disableuartint(priv, NULL);
}
/****************************************************************************
@@ -520,32 +523,31 @@
static int up_attach(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- int ret;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ int ret;
- /* Attach and enable the IRQ */
+ /* Attach and enable the IRQ */
- ret = irq_attach(priv->irq, up_interrupt);
- if (ret == OK)
+ ret = irq_attach(priv->irq, up_interrupt);
+ if (ret == OK)
{
- /* Enable the interrupt (RX and TX interrupts are still disabled
- * in the UART
- */
+ /* Enable the interrupt (RX and TX interrupts are still disabled in the
+ * UART */
- up_enable_irq(priv->irq);
+ up_enable_irq(priv->irq);
- /* Set the uart interrupt priority (the default value is one) */
- if (priv->uartbase == UART0_BASE_ADDR)
- {
- up_prioritize_irq(priv->irq, PRIORITY_LOWEST);
- }
- else if (priv->uartbase == UART2_BASE_ADDR)
- {
- up_prioritize_irq(priv->irq, 10);
- }
-
+ /* Set the uart interrupt priority (the default value is one) */
+ if (priv->uartbase == UART0_BASE_ADDR)
+ {
+ up_prioritize_irq(priv->irq, PRIORITY_LOWEST);
+ }
+ else if (priv->uartbase == UART2_BASE_ADDR)
+ {
+ up_prioritize_irq(priv->irq, 10);
+ }
+
}
- return ret;
+ return ret;
}
/****************************************************************************
@@ -560,9 +562,9 @@
static void up_detach(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- up_disable_irq(priv->irq);
- irq_detach(priv->irq);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
}
/****************************************************************************
@@ -580,103 +582,96 @@
static int up_interrupt(int irq, void *context)
{
- struct uart_dev_s *dev = NULL;
- struct up_dev_s *priv;
- uint8_t status;
- int passes;
+ struct uart_dev_s *dev = NULL;
+ struct up_dev_s *priv;
+ uint8_t status;
+ int passes;
- if (g_uart0priv.irq == irq)
+ if (g_uart0priv.irq == irq)
{
- dev = &g_uart0port;
+ dev = &g_uart0port;
}
- else if (g_uart2priv.irq == irq)
+ else if (g_uart2priv.irq == irq)
{
- dev = &g_uart2port;
+ dev = &g_uart2port;
}
- else
+ else
{
- PANIC(OSERR_INTERNAL);
+ PANIC(OSERR_INTERNAL);
}
- priv = (struct up_dev_s*)dev->priv;
+ priv = (struct up_dev_s *)dev->priv;
- /* Loop until there are no characters to be transferred or,
- * until we have been looping for a long time.
- */
+ /* Loop until there are no characters to be transferred or, until we have
+ * been looping for a long time. */
- for (passes = 0; passes < 256; passes++)
+ for (passes = 0; passes < 256; passes++)
{
- /* Get the current UART status and check for loop
- * termination conditions
- */
+ /* Get the current UART status and check for loop termination conditions */
- status = up_serialin(priv, UART_IIR_OFFSET);
+ status = up_serialin(priv, UART_IIR_OFFSET);
- /* The NO INTERRUPT should be zero if there are pending
- * interrupts
- */
+ /* The NO INTERRUPT should be zero if there are pending interrupts */
- if ((status & IIR_NO_INT) != 0)
+ if ((status & IIR_NO_INT) != 0)
{
- /* Break out of the loop when there is no longer a
- * pending interrupt
- */
+ /* Break out of the loop when there is no longer a pending interrupt */
- break;
+ break;
}
- /* Handle the interrupt by its interrupt ID field */
+ /* Handle the interrupt by its interrupt ID field */
- switch (status & IIR_MASK)
+ switch (status & IIR_MASK)
{
- /* Handle incoming, receive bytes (with or without timeout) */
+ /* Handle incoming, receive bytes (with or without timeout) */
case IIR_RDA_INT:
case IIR_CTI_INT:
- {
+ {
uart_recvchars(dev);
break;
- }
+ }
- /* Handle outgoing, transmit bytes */
+ /* Handle outgoing, transmit bytes */
case IIR_THRE_INT:
- {
+ {
uart_xmitchars(dev);
break;
- }
+ }
- /* Just clear modem status interrupts (UART1 only) */
+ /* Just clear modem status interrupts (UART1 only) */
case IIR_MS_INT:
- {
+ {
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
break;
- }
+ }
- /* Just clear any line status interrupts */
+ /* Just clear any line status interrupts */
case IIR_RLS_INT:
- {
+ {
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
break;
- }
+ }
- /* There should be no other values */
+ /* There should be no other values */
default:
- {
+ {
dbg("Unexpected IIR: %02x\n", status);
break;
- }
+ }
}
}
- return OK;
+ return OK;
}
/****************************************************************************
@@ -689,52 +684,54 @@
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
- struct inode *inode = filep->f_inode;
- struct uart_dev_s *dev = inode->i_private;
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- int ret = OK;
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ int ret = OK;
- switch (cmd)
+ switch (cmd)
{
case TIOCSERGSTRUCT:
- {
- struct up_dev_s *user = (struct up_dev_s*)arg;
+ {
+ struct up_dev_s *user = (struct up_dev_s *)arg;
if (!user)
- {
+ {
*get_errno_ptr() = EINVAL;
ret = ERROR;
- }
+ }
else
- {
+ {
memcpy(user, dev, sizeof(struct up_dev_s));
- }
- }
- break;
+ }
+ }
+ break;
- case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
- {
+ case TIOCSBRK: /* BSD compatibility: Turn break on,
+ * unconditionally */
+ {
irqstate_t flags = irqsave();
up_enablebreaks(priv, true);
irqrestore(flags);
- }
- break;
+ }
+ break;
- case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
- {
+ case TIOCCBRK: /* BSD compatibility: Turn break off,
+ * unconditionally */
+ {
irqstate_t flags;
flags = irqsave();
up_enablebreaks(priv, false);
irqrestore(flags);
- }
- break;
+ }
+ break;
default:
- *get_errno_ptr() = ENOTTY;
- ret = ERROR;
- break;
+ *get_errno_ptr() = ENOTTY;
+ ret = ERROR;
+ break;
}
- return ret;
+ return ret;
}
/****************************************************************************
@@ -747,14 +744,14 @@
*
****************************************************************************/
-static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+static int up_receive(struct uart_dev_s *dev, uint32_t * status)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- uint8_t rbr;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint8_t rbr;
- *status = up_serialin(priv, UART_LSR_OFFSET);
- rbr = up_serialin(priv, UART_RBR_OFFSET);
- return rbr;
+ *status = up_serialin(priv, UART_LSR_OFFSET);
+ rbr = up_serialin(priv, UART_RBR_OFFSET);
+ return rbr;
}
/****************************************************************************
@@ -767,18 +764,18 @@
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- if (enable)
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
- priv->ier |= IER_ERBFI;
+ priv->ier |= IER_ERBFI;
#endif
}
- else
+ else
{
- priv->ier &= ~IER_ERBFI;
+ priv->ier &= ~IER_ERBFI;
}
- up_serialout(priv, UART_IER_OFFSET, priv->ier);
+ up_serialout(priv, UART_IER_OFFSET, priv->ier);
}
/****************************************************************************
@@ -791,8 +788,8 @@
static bool up_rxavailable(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_RDR) != 0);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_RDR) != 0);
}
/****************************************************************************
@@ -805,8 +802,8 @@
static void up_send(struct uart_dev_s *dev, int ch)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- up_serialout(priv, UART_THR_OFFSET, (uint8_t)ch);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ up_serialout(priv, UART_THR_OFFSET, (uint8_t) ch);
}
/****************************************************************************
@@ -819,18 +816,18 @@
static void up_txint(struct uart_dev_s *dev, bool enable)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- if (enable)
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
- priv->ier |= IER_ETBEI;
+ priv->ier |= IER_ETBEI;
#endif
}
- else
+ else
{
- priv->ier &= ~IER_ETBEI;
+ priv->ier &= ~IER_ETBEI;
}
- up_serialout(priv, UART_IER_OFFSET, priv->ier);
+ up_serialout(priv, UART_IER_OFFSET, priv->ier);
}
/****************************************************************************
@@ -843,8 +840,8 @@
static bool up_txready(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0);
}
/****************************************************************************
@@ -857,8 +854,8 @@
static bool up_txempty(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
- return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0);
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ return ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0);
}
/****************************************************************************
@@ -877,27 +874,29 @@
void up_earlyserialinit(void)
{
- /* Enable UART0 and 2 */
- uint32_t pinsel = getreg32(LPC23XX_PINSEL0);
+ /* Enable UART0 and 2 */
- pinsel &= ~( UART0_PINMASK | UART2_PINMASK );
- pinsel |= ( UART0_PINSEL | UART2_PINSEL );
+ uint32_t pinsel = getreg32(LPC23XX_PINSEL0);
- putreg32(pinsel, LPC23XX_PINSEL0);
+ pinsel &= ~(UART0_PINMASK | UART2_PINMASK);
+ pinsel |= (UART0_PINSEL | UART2_PINSEL);
- /* Set Uart PCLK divider */
- SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~U0_PCLKSEL_MASK) | U0_PCLKSEL;
- SCB_PCLKSEL1 = (SCB_PCLKSEL1 & ~U2_PCLKSEL_MASK) | U2_PCLKSEL;
+ putreg32(pinsel, LPC23XX_PINSEL0);
- /* Disable both UARTS */
+ /* Set Uart PCLK divider */
- up_disableuartint(TTYS0_DEV.priv, NULL);
- up_disableuartint(TTYS1_DEV.priv, NULL);
+ SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~U0_PCLKSEL_MASK) | U0_PCLKSEL;
+ SCB_PCLKSEL1 = (SCB_PCLKSEL1 & ~U2_PCLKSEL_MASK) | U2_PCLKSEL;
- /* Configuration whichever one is the console */
+ /* Disable both UARTS */
- CONSOLE_DEV.isconsole = true;
- up_setup(&CONSOLE_DEV);
+ up_disableuartint(TTYS0_DEV.priv, NULL);
+ up_disableuartint(TTYS1_DEV.priv, NULL);
+
+ /* Configuration whichever one is the console */
+
+ CONSOLE_DEV.isconsole = true;
+ up_setup(&CONSOLE_DEV);
}
/****************************************************************************
@@ -911,9 +910,9 @@
void up_serialinit(void)
{
- (void)uart_register("/dev/console", &CONSOLE_DEV);
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ (void)uart_register("/dev/console", &CONSOLE_DEV);
+ (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************
@@ -926,29 +925,29 @@
int up_putc(int ch)
{
- struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
- uint8_t ier;
+ struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
+ uint8_t ier;
- up_disableuartint(priv, &ier);
- up_waittxready(priv);
- up_serialout(priv, UART_THR_OFFSET, (uint8_t)ch);
+ up_disableuartint(priv, &ier);
+ up_waittxready(priv);
+ up_serialout(priv, UART_THR_OFFSET, (uint8_t) ch);
- /* Check for LF */
+ /* Check for LF */
- if (ch == '\n')
+ if (ch == '\n')
{
- /* Add CR */
+ /* Add CR */
- up_waittxready(priv);
- up_serialout(priv, UART_THR_OFFSET, '\r');
+ up_waittxready(priv);
+ up_serialout(priv, UART_THR_OFFSET, '\r');
}
- up_waittxready(priv);
- up_restoreuartint(priv, ier);
- return ch;
+ up_waittxready(priv);
+ up_restoreuartint(priv, ier);
+ return ch;
}
-#else /* CONFIG_USE_SERIALDRIVER */
+#else /* CONFIG_USE_SERIALDRIVER */
/****************************************************************************
* Name: up_putc
@@ -960,17 +959,16 @@
int up_putc(int ch)
{
- /* Check for LF */
+ /* Check for LF */
- if (ch == '\n')
+ if (ch == '\n')
{
- /* Add CR */
+ /* Add CR */
- up_lowputc('\r');
+ up_lowputc('\r');
}
- up_lowputc(ch);
- return ch;
+ up_lowputc(ch);
+ return ch;
}
-
#endif /* CONFIG_USE_SERIALDRIVER */
diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c
index 914593c..5e8d569 100755
--- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c
+++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c
@@ -56,33 +56,30 @@
#include "lpc23xx_vic.h"
#include "lpc23xx_timer.h"
-
/****************************************************************************
* Definitions
****************************************************************************/
+
/* T0_PCLKDIV valid values are 1,2,4 */
+
#define T0_PCLK_DIV 1
/* PCKLSEL0 bits 3:2, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef T0_PCLK_DIV
-# if T0_PCLK_DIV == 1
-# define TIMER0_PCLKSEL (0x00000004)
-# elif T0_PCLK_DIV == 2
-# define TIMER0_PCLKSEL (0x00000008)
-# elif T0_PCLK_DIV == 4
-# define TIMER0_PCLKSEL (0x00000000)
-# endif
+# if T0_PCLK_DIV == 1
+# define TIMER0_PCLKSEL (0x00000004)
+# elif T0_PCLK_DIV == 2
+# define TIMER0_PCLKSEL (0x00000008)
+# elif T0_PCLK_DIV == 4
+# define TIMER0_PCLKSEL (0x00000000)
+# endif
#endif
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_TICKS_COUNT ( (CCLK / T0_PCLK_DIV ) / TICK_PER_SEC )
-
-
-
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -105,34 +102,37 @@
****************************************************************************/
#ifdef CONFIG_VECTORED_INTERRUPTS
-int up_timerisr(uint32_t *regs)
+int up_timerisr(uint32_t * regs)
#else
-int up_timerisr(int irq, uint32_t *regs)
+int up_timerisr(int irq, uint32_t * regs)
#endif
-{
- static uint32_t tick;
-
- /* Process timer interrupt */
-
- sched_process_timer();
+{
+ static uint32_t tick;
- /* Clear the MR0 match interrupt */
+ /* Process timer interrupt */
- tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
+ sched_process_timer();
- /* Reset the VIC as well */
+ /* Clear the MR0 match interrupt */
+
+ tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
+
+ /* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
- /* write any value to VICAddress to acknowledge the interrupt */
- vic_putreg(0, VIC_ADDRESS_OFFSET);
+ /* write any value to VICAddress to acknowledge the interrupt */
+ vic_putreg(0, VIC_ADDRESS_OFFSET);
#endif
- if(tick++ > 100){
- tick =0;
- up_statledoff();
- }else up_statledon();
-
- return 0;
+ if (tick++ > 100)
+ {
+ tick = 0;
+ up_statledoff();
+ }
+ else
+ up_statledon();
+
+ return 0;
}
/****************************************************************************
@@ -149,44 +149,53 @@
uint16_t mcr;
/* Power up Timer0 */
+
SCB_PCONP |= PCTIM0;
/* Timer0 clock input frequency = CCLK / TO_PCLKDIV */
+
SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~T0_PCLKSEL_MASK) | TIMER0_PCLKSEL;
/* Clear all match and capture event interrupts */
+
tmr_putreg8(TMR_IR_ALLI, TMR_IR_OFFSET);
/* Clear the timer counter */
+
tmr_putreg32(0, TMR_TC_OFFSET);
/* No pre-scaler */
+
tmr_putreg32(0, TMR_PR_OFFSET);
tmr_putreg32(0, TMR_PC_OFFSET);
- /* Set timer match registger to get a TICK_PER_SEC rate
- * See arch/board.h and sched/os_internal.h
+ /* Set timer match register to get a TICK_PER_SEC rate See arch/board.h and
+ * sched/os_internal.h
*/
- tmr_putreg32( T0_TICKS_COUNT, TMR_MR0_OFFSET ); /* 10ms Intterrupt */
+
+ tmr_putreg32(T0_TICKS_COUNT, TMR_MR0_OFFSET); /* 10ms Intterrupt */
/* Reset timer counter register and interrupt on match */
+
mcr = tmr_getreg16(TMR_MCR_OFFSET);
mcr &= ~TMR_MCR_MR1I;
mcr |= (TMR_MCR_MR0I | TMR_MCR_MR0R);
- tmr_putreg16(mcr, TMR_MCR_OFFSET);//-- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0
+ tmr_putreg16(mcr, TMR_MCR_OFFSET); /* -- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0 */
/* Enable counting */
- //~ tmr_putreg32(1, TMR_TCR_OFFSET);
+ /* ~ tmr_putreg32(1, TMR_TCR_OFFSET); */
+
tmr_putreg8(TMR_CR_ENABLE, TMR_TCR_OFFSET);
/* Attach the timer interrupt vector */
#ifdef CONFIG_VECTORED_INTERRUPTS
- up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t)up_timerisr);
+ up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t) up_timerisr);
#else
- (void)irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+ (void)irq_attach(IRQ_SYSTIMER, (xcpt_t) up_timerisr);
up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST);
#endif
+
/* And enable the system timer interrupt */
up_enable_irq(IRQ_SYSTIMER);
