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  <section id="debugging-flashing-nuttx-on-arm-with-hardware-debugger-jtag-swd">
<h1>Debugging / flashing NuttX on ARM with hardware debugger (JTAG/SWD)<a class="headerlink" href="#debugging-flashing-nuttx-on-arm-with-hardware-debugger-jtag-swd" title="Permalink to this heading"></a></h1>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>Migrated from:
<a class="reference external" href="https://cwiki.apache.org/confluence/pages/viewpage.action?pageId=139629444">https://cwiki.apache.org/confluence/pages/viewpage.action?pageId=139629444</a></p>
</div>
<p>NOTE: If you experience the issues described on this page, you can enable the
configuration option below to resolve it.</p>
<div class="highlight-makefile notranslate"><div class="highlight"><pre><span></span><span class="nv">CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG</span><span class="o">=</span>y
</pre></div>
</div>
<section id="what-s-the-problem">
<h2>What’s the problem?<a class="headerlink" href="#what-s-the-problem" title="Permalink to this heading"></a></h2>
<p>On some architectures (like ARM Cortex-M3) Idle thread causes the core to stop
using WFI (Wait For Interrupt) assembly instruction. This effectively stops
clocking of the core, which is resumed only by some enabled interrupt. This
causes hardware debuggers to believe that they were disconnected from the
target, as they lose connection with the now stopped core. For example OpenOCD
shows errors like these the moment you start the target:</p>
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 100ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 300ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 700ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 1500ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 3100ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 6300ms</span>
<span class="go">Error: jtag status contains invalid mode value - communication failure</span>
<span class="go">Polling target failed, GDB will be halted. Polling again in 6300ms</span>
</pre></div>
</div>
<p>This makes debugging the code impossible and flashing the chip is much harder -
you have to connect to the chip at the right moment (when it’s not disabled
due to WFI) - the chances of doing that are inverse proportional to the load
of your system (if your chip spends 99% of time in Idle mode, you have 1%
chance of connecting and halting it).</p>
</section>
<section id="solution">
<h2>Solution<a class="headerlink" href="#solution" title="Permalink to this heading"></a></h2>
<p>Some ARM cores that support disabling of clocking after WFI instruction have
special configuration options to make debugging possible. One example is STM32
family - with it’s <code class="docutils literal notranslate"><span class="pre">DBGMCU-&gt;CR</span></code> register it’s possible to keep the core
clocked during power-down modes. If your chip supports such configuration you
should put it in some early stage of initialization, like in
<code class="docutils literal notranslate"><span class="pre">stm32_boardinitialize()</span></code> function. The following code demonstrates the
change for STM32:</p>
<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">cr</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">getreg32</span><span class="p">(</span><span class="n">STM32_DBGMCU_CR</span><span class="p">);</span>
<span class="n">cr</span><span class="w"> </span><span class="o">|=</span><span class="w"> </span><span class="n">DBGMCU_CR_STANDBY</span><span class="w"> </span><span class="o">|</span><span class="w"> </span><span class="n">DBGMCU_CR_STOP</span><span class="w"> </span><span class="o">|</span><span class="w"> </span><span class="n">DBGMCU_CR_SLEEP</span><span class="p">;</span>
<span class="n">putreg32</span><span class="p">(</span><span class="n">cr</span><span class="p">,</span><span class="w"> </span><span class="n">STM32_DBGMCU_CR</span><span class="p">);</span>
</pre></div>
</div>
<p>If your chip doesn’t provide such options there is no other way than not using
WFI instruction in up_idle() function.</p>
<p>It should be noted that such modification should be done only for development
stage, as keeping the core clocked during power-down modes contradicts the
major purpose of using them - reducing power usage.</p>
<p>In rare cases that you still have problems with connecting to the target
(especially after power cycle), you should try connecting and halting the chip
under reset (this is supported by new versions of OpenOCD), by holding the
reset button while starting OpenOCD or by configuring OpenOCD to do that for
you.</p>
<section id="work-around">
<h3>Work-around<a class="headerlink" href="#work-around" title="Permalink to this heading"></a></h3>
<p>If you keep the RESET button pressed and run OpenOCD command to connected to
it, then it will connect successful. After connecting you need to keep the
reset button pressed until you open the telnet connection
(telnet 127.0.0.1 4444) and execute “reset halt”:</p>
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="go">&gt; reset halt</span>
<span class="go">timed out while waiting for target halted</span>
<span class="go">TARGET: stm32f1x.cpu - Not halted</span>

<span class="go">in procedure &#39;reset&#39;</span>
<span class="go">target state: halted</span>
<span class="go">target halted due to debug-request, current mode: Thread</span>
<span class="go">xPSR: 0x01000000 pc: 0x080003d0 msp: 0x20001278</span>
</pre></div>
</div>
<p>Then release the RESET boot and it will reset correctly.</p>
<p>This work-around was tested on viewtool-stm32f107 board and bypassed the above
error reported by OpenOCD. The SWD programmer was a STLink-V2 and this was
the command to connect:</p>
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="go">openocd -f interface/stlink-v2.cfg -f target/stm32f1x_stlink.cfg</span>
</pre></div>
</div>
<p>The OpenOCD version used was: Open On-Chip Debugger 0.8.0-dev-00307-g215c41c
(git commit 215c41c)</p>
</section>
</section>
</section>


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