build: Replace "$(shell $(DEFINE) $(CC) ...)" with $(DEFINE_PREFIX)
to unify the way to define macros in Makefile
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
diff --git a/Application.mk b/Application.mk
index 121532c..6bf6e66 100644
--- a/Application.mk
+++ b/Application.mk
@@ -205,8 +205,8 @@
$(MAINCXXOBJ): %$(CXXEXT)$(SUFFIX)$(OBJEXT): %$(CXXEXT)
$(eval MAIN=$(word $(call GETINDEX,$<,$(MAINCXXSRCS)),$(MAINNAME)))
- $(eval $<_CXXFLAGS += ${shell $(DEFINE) "$(CXX)" main=$(MAIN)})
- $(eval $<_CXXELFFLAGS += ${shell $(DEFINE) "$(CXX)" main=$(MAIN)})
+ $(eval $<_CXXFLAGS += ${DEFINE_PREFIX}main=$(MAIN))
+ $(eval $<_CXXELFFLAGS += ${DEFINE_PREFIX}main=$(MAIN))
$(if $(and $(CONFIG_BUILD_LOADABLE),$(CXXELFFLAGS)), \
$(call ELFCOMPILEXX, $<, $@), $(call COMPILEXX, $<, $@))