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/*
Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NRF51_BITS_H
#define __NRF51_BITS_H
/*lint ++flb "Enter library region" */
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver. */
/* Register: AAR_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on RESOLVED event. */
#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on END event. */
#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
/* Register: AAR_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on RESOLVED event. */
#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on ENDKSGEN event. */
#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: AAR_STATUS */
/* Description: Resolution status. */
/* Bits 3..0 : The IRK used last time an address was resolved. */
#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
/* Register: AAR_ENABLE */
/* Description: Enable AAR. */
/* Bits 1..0 : Enable AAR. */
#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
/* Register: AAR_NIRK */
/* Description: Number of Identity root Keys in the IRK data structure. */
/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
/* Register: AAR_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: ADC */
/* Description: Analog to digital converter. */
/* Register: ADC_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 0 : Enable interrupt on END event. */
#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
/* Register: ADC_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 0 : Disable interrupt on END event. */
#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: ADC_BUSY */
/* Description: ADC busy register. */
/* Bit 0 : ADC busy register. */
#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
/* Register: ADC_ENABLE */
/* Description: ADC enable. */
/* Bits 1..0 : ADC enable. */
#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
/* Register: ADC_CONFIG */
/* Description: ADC configuration register. */
/* Bits 17..16 : ADC external reference pin selection. */
#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
/* Bits 15..8 : ADC analog pin selection. */
#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
/* Bits 6..5 : ADC reference selection. */
#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
/* Bits 4..2 : ADC input selection. */
#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
/* Bits 1..0 : ADC resolution. */
#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
/* Register: ADC_RESULT */
/* Description: Result of ADC conversion. */
/* Bits 9..0 : Result of ADC conversion. */
#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
/* Register: ADC_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: CCM */
/* Description: AES CCM Mode Encryption. */
/* Register: CCM_SHORTS */
/* Description: Shortcuts for the CCM. */
/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
/* Register: CCM_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 2 : Enable interrupt on ERROR event. */
#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on ENDCRYPT event. */
#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on ENDKSGEN event. */
#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
/* Register: CCM_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 2 : Disable interrupt on ERROR event. */
#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on ENDCRYPT event. */
#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on ENDKSGEN event. */
#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: CCM_MICSTATUS */
/* Description: CCM RX MIC check result. */
/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
/* Register: CCM_ENABLE */
/* Description: CCM enable. */
/* Bits 1..0 : CCM enable. */
#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
/* Register: CCM_MODE */
/* Description: Operation mode. */
/* Bit 0 : CCM mode operation. */
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
/* Register: CCM_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: CLOCK */
/* Description: Clock control. */
/* Register: CLOCK_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 4 : Enable interrupt on CTTO event. */
#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 3 : Enable interrupt on DONE event. */
#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
/* Register: CLOCK_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 4 : Disable interrupt on CTTO event. */
#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 3 : Disable interrupt on DONE event. */
#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: CLOCK_HFCLKRUN */
/* Description: Task HFCLKSTART trigger status. */
/* Bit 0 : Task HFCLKSTART trigger status. */
#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
/* Register: CLOCK_HFCLKSTAT */
/* Description: High frequency clock status. */
/* Bit 16 : State for the HFCLK. */
#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
/* Bit 0 : Active clock source for the HF clock. */
#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
/* Register: CLOCK_LFCLKRUN */
/* Description: Task LFCLKSTART triggered status. */
/* Bit 0 : Task LFCLKSTART triggered status. */
#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
/* Register: CLOCK_LFCLKSTAT */
/* Description: Low frequency clock status. */
/* Bit 16 : State for the LF clock. */
#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
/* Bits 1..0 : Active clock source for the LF clock. */
#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
/* Register: CLOCK_LFCLKSRCCOPY */
/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
/* Register: CLOCK_LFCLKSRC */
/* Description: Clock source for the LFCLK clock. */
/* Bits 1..0 : Clock source. */
#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
/* Register: CLOCK_CTIV */
/* Description: Calibration timer interval. */
/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
/* Register: CLOCK_XTALFREQ */
/* Description: Crystal frequency. */
/* Bits 7..0 : External Xtal frequency selection. */
#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
/* Peripheral: ECB */
/* Description: AES ECB Mode Encryption. */
/* Register: ECB_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 1 : Enable interrupt on ERRORECB event. */
#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on ENDECB event. */
#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
/* Register: ECB_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 1 : Disable interrupt on ERRORECB event. */
#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on ENDECB event. */
#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: ECB_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: FICR */
/* Description: Factory Information Configuration. */
/* Register: FICR_PPFC */
/* Description: Pre-programmed factory code present. */
/* Bits 7..0 : Pre-programmed factory code present. */
#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
/* Register: FICR_CONFIGID */
/* Description: Configuration identifier. */
/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
/* Bits 15..0 : Hardware Identification Number. */
#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
/* Register: FICR_DEVICEADDRTYPE */
/* Description: Device address type. */
/* Bit 0 : Device address type. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
/* Register: FICR_OVERRIDEEN */
/* Description: Radio calibration override enable. */
/* Bit 3 : Override default values for BLE_1Mbit mode. */
#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
/* Bit 0 : Override default values for NRF_1Mbit mode. */
#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
/* Peripheral: GPIO */
/* Description: General purpose input and output. */
/* Register: GPIO_OUT */
/* Description: Write GPIO port. */
/* Bit 31 : Pin 31. */
#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
/* Bit 30 : Pin 30. */
#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
/* Bit 29 : Pin 29. */
#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
/* Bit 28 : Pin 28. */
#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
/* Bit 27 : Pin 27. */
#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
/* Bit 26 : Pin 26. */
#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
/* Bit 25 : Pin 25. */
#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
/* Bit 24 : Pin 24. */
#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
/* Bit 23 : Pin 23. */
#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
/* Bit 22 : Pin 22. */
#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
/* Bit 21 : Pin 21. */
#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
/* Bit 20 : Pin 20. */
#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
/* Bit 19 : Pin 19. */
#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
/* Bit 18 : Pin 18. */
#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
/* Bit 17 : Pin 17. */
#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
/* Bit 16 : Pin 16. */
#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
/* Bit 15 : Pin 15. */
#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
/* Bit 14 : Pin 14. */
#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
/* Bit 13 : Pin 13. */
#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
/* Bit 12 : Pin 12. */
#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
/* Bit 11 : Pin 11. */
#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
/* Bit 10 : Pin 10. */
#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
/* Bit 9 : Pin 9. */
#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
/* Bit 8 : Pin 8. */
#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
/* Bit 7 : Pin 7. */
#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
/* Bit 6 : Pin 6. */
#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
/* Bit 5 : Pin 5. */
#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
/* Bit 4 : Pin 4. */
#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
/* Bit 3 : Pin 3. */
#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
/* Bit 2 : Pin 2. */
#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
/* Bit 1 : Pin 1. */
#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
/* Bit 0 : Pin 0. */
#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
/* Register: GPIO_OUTSET */
/* Description: Set individual bits in GPIO port. */
/* Bit 31 : Pin 31. */
#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
/* Bit 30 : Pin 30. */
#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
/* Bit 29 : Pin 29. */
#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
/* Bit 28 : Pin 28. */
#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
/* Bit 27 : Pin 27. */
#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
/* Bit 26 : Pin 26. */
#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
/* Bit 25 : Pin 25. */
#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
/* Bit 24 : Pin 24. */
#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
/* Bit 23 : Pin 23. */
#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
/* Bit 22 : Pin 22. */
#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
/* Bit 21 : Pin 21. */
#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
/* Bit 20 : Pin 20. */
#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
/* Bit 19 : Pin 19. */
#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
/* Bit 18 : Pin 18. */
#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
/* Bit 17 : Pin 17. */
#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
/* Bit 16 : Pin 16. */
#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
/* Bit 15 : Pin 15. */
#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
/* Bit 14 : Pin 14. */
#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
/* Bit 13 : Pin 13. */
#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
/* Bit 12 : Pin 12. */
#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
/* Bit 11 : Pin 11. */
#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
/* Bit 10 : Pin 10. */
#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
/* Bit 9 : Pin 9. */
#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
/* Bit 8 : Pin 8. */
#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
/* Bit 7 : Pin 7. */
#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
/* Bit 6 : Pin 6. */
#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
/* Bit 5 : Pin 5. */
#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
/* Bit 4 : Pin 4. */
#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
/* Bit 3 : Pin 3. */
#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
/* Bit 2 : Pin 2. */
#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
/* Bit 1 : Pin 1. */
#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
/* Bit 0 : Pin 0. */
#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
/* Register: GPIO_OUTCLR */
/* Description: Clear individual bits in GPIO port. */
/* Bit 31 : Pin 31. */
#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
/* Bit 30 : Pin 30. */
#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
/* Bit 29 : Pin 29. */
#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
/* Bit 28 : Pin 28. */
#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
/* Bit 27 : Pin 27. */
#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
/* Bit 26 : Pin 26. */
#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
/* Bit 25 : Pin 25. */
#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
/* Bit 24 : Pin 24. */
#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
/* Bit 23 : Pin 23. */
#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
/* Bit 22 : Pin 22. */
#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
/* Bit 21 : Pin 21. */
#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
/* Bit 20 : Pin 20. */
#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
/* Bit 19 : Pin 19. */
#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
/* Bit 18 : Pin 18. */
#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
/* Bit 17 : Pin 17. */
#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
/* Bit 16 : Pin 16. */
#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
/* Bit 15 : Pin 15. */
#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
/* Bit 14 : Pin 14. */
#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
/* Bit 13 : Pin 13. */
#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
/* Bit 12 : Pin 12. */
#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
/* Bit 11 : Pin 11. */
#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
/* Bit 10 : Pin 10. */
#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
/* Bit 9 : Pin 9. */
#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
/* Bit 8 : Pin 8. */
#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
/* Bit 7 : Pin 7. */
#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
/* Bit 6 : Pin 6. */
#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
/* Bit 5 : Pin 5. */
#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
/* Bit 4 : Pin 4. */
#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
/* Bit 3 : Pin 3. */
#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
/* Bit 2 : Pin 2. */
#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
/* Bit 1 : Pin 1. */
#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
/* Bit 0 : Pin 0. */
#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
/* Register: GPIO_IN */
/* Description: Read GPIO port. */
/* Bit 31 : Pin 31. */
#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
/* Bit 30 : Pin 30. */
#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
/* Bit 29 : Pin 29. */
#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
/* Bit 28 : Pin 28. */
#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
/* Bit 27 : Pin 27. */
#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
/* Bit 26 : Pin 26. */
#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
/* Bit 25 : Pin 25. */
#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
/* Bit 24 : Pin 24. */
#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
/* Bit 23 : Pin 23. */
#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
/* Bit 22 : Pin 22. */
#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
/* Bit 21 : Pin 21. */
#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
/* Bit 20 : Pin 20. */
#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
/* Bit 19 : Pin 19. */
#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
/* Bit 18 : Pin 18. */
#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
/* Bit 17 : Pin 17. */
#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
/* Bit 16 : Pin 16. */
#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
/* Bit 15 : Pin 15. */
#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
/* Bit 14 : Pin 14. */
#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
/* Bit 13 : Pin 13. */
#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
/* Bit 12 : Pin 12. */
#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
/* Bit 11 : Pin 11. */
#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
/* Bit 10 : Pin 10. */
#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
/* Bit 9 : Pin 9. */
#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
/* Bit 8 : Pin 8. */
#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
/* Bit 7 : Pin 7. */
#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
/* Bit 6 : Pin 6. */
#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
/* Bit 5 : Pin 5. */
#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
/* Bit 4 : Pin 4. */
#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
/* Bit 3 : Pin 3. */
#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
/* Bit 2 : Pin 2. */
#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
/* Bit 1 : Pin 1. */
#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
/* Bit 0 : Pin 0. */
#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
/* Register: GPIO_DIR */
/* Description: Direction of GPIO pins. */
/* Bit 31 : Pin 31. */
#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
/* Bit 30 : Pin 30. */
#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
/* Bit 29 : Pin 29. */
#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
/* Bit 28 : Pin 28. */
#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
/* Bit 27 : Pin 27. */
#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
/* Bit 26 : Pin 26. */
#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
/* Bit 25 : Pin 25. */
#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
/* Bit 24 : Pin 24. */
#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
/* Bit 23 : Pin 23. */
#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
/* Bit 22 : Pin 22. */
#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
/* Bit 21 : Pin 21. */
#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
/* Bit 20 : Pin 20. */
#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
/* Bit 19 : Pin 19. */
#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
/* Bit 18 : Pin 18. */
#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
/* Bit 17 : Pin 17. */
#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
/* Bit 16 : Pin 16. */
#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
/* Bit 15 : Pin 15. */
#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
/* Bit 14 : Pin 14. */
#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
/* Bit 13 : Pin 13. */
#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
/* Bit 12 : Pin 12. */
#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
/* Bit 11 : Pin 11. */
#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
/* Bit 10 : Pin 10. */
#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
/* Bit 9 : Pin 9. */
#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
/* Bit 8 : Pin 8. */
#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
/* Bit 7 : Pin 7. */
#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
/* Bit 6 : Pin 6. */
#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
/* Bit 5 : Pin 5. */
#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
/* Bit 4 : Pin 4. */
#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
/* Bit 3 : Pin 3. */
#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
/* Bit 2 : Pin 2. */
#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
/* Bit 1 : Pin 1. */
#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
/* Bit 0 : Pin 0. */
#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
/* Register: GPIO_DIRSET */
/* Description: DIR set register. */
/* Bit 31 : Set as output pin 31. */
#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
/* Bit 30 : Set as output pin 30. */
#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
/* Bit 29 : Set as output pin 29. */
#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
/* Bit 28 : Set as output pin 28. */
#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
/* Bit 27 : Set as output pin 27. */
#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
/* Bit 26 : Set as output pin 26. */
#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
/* Bit 25 : Set as output pin 25. */
#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
/* Bit 24 : Set as output pin 24. */
#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
/* Bit 23 : Set as output pin 23. */
#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
/* Bit 22 : Set as output pin 22. */
#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
/* Bit 21 : Set as output pin 21. */
#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
/* Bit 20 : Set as output pin 20. */
#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
/* Bit 19 : Set as output pin 19. */
#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
/* Bit 18 : Set as output pin 18. */
#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
/* Bit 17 : Set as output pin 17. */
#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
/* Bit 16 : Set as output pin 16. */
#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
/* Bit 15 : Set as output pin 15. */
#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
/* Bit 14 : Set as output pin 14. */
#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
/* Bit 13 : Set as output pin 13. */
#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
/* Bit 12 : Set as output pin 12. */
#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
/* Bit 11 : Set as output pin 11. */
#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
/* Bit 10 : Set as output pin 10. */
#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
/* Bit 9 : Set as output pin 9. */
#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
/* Bit 8 : Set as output pin 8. */
#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
/* Bit 7 : Set as output pin 7. */
#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
/* Bit 6 : Set as output pin 6. */
#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
/* Bit 5 : Set as output pin 5. */
#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
/* Bit 4 : Set as output pin 4. */
#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
/* Bit 3 : Set as output pin 3. */
#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
/* Bit 2 : Set as output pin 2. */
#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
/* Bit 1 : Set as output pin 1. */
#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
/* Bit 0 : Set as output pin 0. */
#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
/* Register: GPIO_DIRCLR */
/* Description: DIR clear register. */
/* Bit 31 : Set as input pin 31. */
#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
/* Bit 30 : Set as input pin 30. */
#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
/* Bit 29 : Set as input pin 29. */
#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
/* Bit 28 : Set as input pin 28. */
#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
/* Bit 27 : Set as input pin 27. */
#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
/* Bit 26 : Set as input pin 26. */
#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
/* Bit 25 : Set as input pin 25. */
#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
/* Bit 24 : Set as input pin 24. */
#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
/* Bit 23 : Set as input pin 23. */
#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
/* Bit 22 : Set as input pin 22. */
#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
/* Bit 21 : Set as input pin 21. */
#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
/* Bit 20 : Set as input pin 20. */
#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
/* Bit 19 : Set as input pin 19. */
#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
/* Bit 18 : Set as input pin 18. */
#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
/* Bit 17 : Set as input pin 17. */
#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
/* Bit 16 : Set as input pin 16. */
#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
/* Bit 15 : Set as input pin 15. */
#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
/* Bit 14 : Set as input pin 14. */
#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
/* Bit 13 : Set as input pin 13. */
#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
/* Bit 12 : Set as input pin 12. */
#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
/* Bit 11 : Set as input pin 11. */
#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
/* Bit 10 : Set as input pin 10. */
#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
/* Bit 9 : Set as input pin 9. */
#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
/* Bit 8 : Set as input pin 8. */
#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
/* Bit 7 : Set as input pin 7. */
#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
/* Bit 6 : Set as input pin 6. */
#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
/* Bit 5 : Set as input pin 5. */
#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
/* Bit 4 : Set as input pin 4. */
#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
/* Bit 3 : Set as input pin 3. */
#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
/* Bit 2 : Set as input pin 2. */
#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
/* Bit 1 : Set as input pin 1. */
#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
/* Bit 0 : Set as input pin 0. */
#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
/* Register: GPIO_PIN_CNF */
/* Description: Configuration of GPIO pins. */
/* Bits 17..16 : Pin sensing mechanism. */
#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
/* Bits 10..8 : Drive configuration. */
#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
/* Bits 3..2 : Pull-up or -down configuration. */
#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
/* Bit 1 : Connect or disconnect input path. */
#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
/* Bit 0 : Pin direction. */
#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
/* Peripheral: GPIOTE */
/* Description: GPIO tasks and events. */
/* Register: GPIOTE_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 31 : Enable interrupt on PORT event. */
#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 3 : Enable interrupt on IN[3] event. */
#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 2 : Enable interrupt on IN[2] event. */
#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on IN[1] event. */
#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on IN[0] event. */
#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
/* Register: GPIOTE_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 31 : Disable interrupt on PORT event. */
#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 3 : Disable interrupt on IN[3] event. */
#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 2 : Disable interrupt on IN[2] event. */
#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on IN[1] event. */
#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on IN[0] event. */
#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: GPIOTE_CONFIG */
/* Description: Channel configuration registers. */
/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
/* Bits 12..8 : Pin select. */
#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
/* Bits 1..0 : Mode */
#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
/* Register: GPIOTE_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: LPCOMP */
/* Description: Low power comparator. */
/* Register: LPCOMP_SHORTS */
/* Description: Shortcuts for the LPCOMP. */
/* Bit 4 : Shortcut between CROSS event and STOP task. */
#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
/* Bit 3 : Shortcut between UP event and STOP task. */
#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
/* Bit 2 : Shortcut between DOWN event and STOP task. */
#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
/* Bit 1 : Shortcut between RADY event and STOP task. */
#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
/* Bit 0 : Shortcut between READY event and SAMPLE task. */
#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
/* Register: LPCOMP_INTENSET */
/* Description: Interrupt enable set register. */
/* Bit 3 : Enable interrupt on CROSS event. */
#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 2 : Enable interrupt on UP event. */
#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on DOWN event. */
#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 0 : Enable interrupt on READY event. */
#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
/* Register: LPCOMP_INTENCLR */
/* Description: Interrupt enable clear register. */
/* Bit 3 : Disable interrupt on CROSS event. */
#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 2 : Disable interrupt on UP event. */
#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on DOWN event. */
#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 0 : Disable interrupt on READY event. */
#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
/* Register: LPCOMP_RESULT */
/* Description: Result of last compare. */
/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */
#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
/* Register: LPCOMP_ENABLE */
/* Description: Enable the LPCOMP. */
/* Bits 1..0 : Enable or disable LPCOMP. */
#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
/* Register: LPCOMP_PSEL */
/* Description: Input pin select. */
/* Bits 2..0 : Analog input pin select. */
#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
/* Register: LPCOMP_REFSEL */
/* Description: Reference select. */
/* Bits 2..0 : Reference select. */
#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
/* Register: LPCOMP_EXTREFSEL */
/* Description: External reference select. */
/* Bit 0 : External analog reference pin selection. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
/* Register: LPCOMP_ANADETECT */
/* Description: Analog detect configuration. */
/* Bits 1..0 : Analog detect configuration. */
#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
/* Register: LPCOMP_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: MPU */
/* Description: Memory Protection Unit. */
/* Register: MPU_PERR0 */
/* Description: Configuration of peripherals in mpu regions. */
/* Bit 31 : PPI region configuration. */
#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 30 : NVMC region configuration. */
#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 19 : LPCOMP region configuration. */
#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 18 : QDEC region configuration. */
#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 17 : RTC1 region configuration. */
#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 16 : WDT region configuration. */
#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 15 : CCM and AAR region configuration. */
#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 14 : ECB region configuration. */
#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 13 : RNG region configuration. */
#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 12 : TEMP region configuration. */
#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 11 : RTC0 region configuration. */
#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 10 : TIMER2 region configuration. */
#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 9 : TIMER1 region configuration. */
#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 8 : TIMER0 region configuration. */
#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 7 : ADC region configuration. */
#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 6 : GPIOTE region configuration. */
#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 4 : SPI1 and TWI1 region configuration. */
#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 3 : SPI0 and TWI0 region configuration. */
#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 2 : UART0 region configuration. */
#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 1 : RADIO region configuration. */
#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Bit 0 : POWER_CLOCK region configuration. */
#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
/* Register: MPU_PROTENSET0 */
/* Description: Erase and write protection bit enable set register. */
/* Bit 31 : Protection enable for region 31. */
#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
/* Bit 30 : Protection enable for region 30. */
#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
/* Bit 29 : Protection enable for region 29. */
#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
/* Bit 28 : Protection enable for region 28. */
#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */