| /* ---------------------------------------------------------------------------------------*/ | |
| /* @file: startup_MKW40Z4.s */ | |
| /* @purpose: CMSIS Cortex-M0P Core Device Startup File */ | |
| /* MKW40Z4 */ | |
| /* @version: 1.2 */ | |
| /* @date: 2015-5-7 */ | |
| /* @build: b150513 */ | |
| /* ---------------------------------------------------------------------------------------*/ | |
| /* */ | |
| /* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ | |
| /* All rights reserved. */ | |
| /* */ | |
| /* Redistribution and use in source and binary forms, with or without modification, */ | |
| /* are permitted provided that the following conditions are met: */ | |
| /* */ | |
| /* o Redistributions of source code must retain the above copyright notice, this list */ | |
| /* of conditions and the following disclaimer. */ | |
| /* */ | |
| /* o Redistributions in binary form must reproduce the above copyright notice, this */ | |
| /* list of conditions and the following disclaimer in the documentation and/or */ | |
| /* other materials provided with the distribution. */ | |
| /* */ | |
| /* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ | |
| /* contributors may be used to endorse or promote products derived from this */ | |
| /* software without specific prior written permission. */ | |
| /* */ | |
| /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ | |
| /* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ | |
| /* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ | |
| /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ | |
| /* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ | |
| /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ | |
| /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ | |
| /* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ | |
| /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ | |
| /* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ | |
| /*****************************************************************************/ | |
| /* Version: GCC for ARM Embedded Processors */ | |
| /*****************************************************************************/ | |
| .syntax unified | |
| .arch armv6-m | |
| .section .stack | |
| .align 3 | |
| .equ Stack_Size, 432 | |
| .globl __StackTop | |
| .globl __StackLimit | |
| __StackLimit: | |
| .space Stack_Size | |
| .size __StackLimit, . - __StackLimit | |
| __StackTop: | |
| .size __StackTop, . - __StackTop | |
| /* XXX: probably not needed; just possibly the global __HeapBase and __HeapLimit labels */ | |
| .section .heap | |
| .align 3 | |
| #ifdef __HEAP_SIZE | |
| .equ Heap_Size, __HEAP_SIZE | |
| #else | |
| .equ Heap_Size, 0 | |
| #endif | |
| .globl __HeapBase | |
| .globl __HeapLimit | |
| __HeapBase: | |
| .if Heap_Size | |
| .space Heap_Size | |
| .endif | |
| .size __HeapBase, . - __HeapBase | |
| __HeapLimit: | |
| .size __HeapLimit, . - __HeapLimit | |
| .section .isr_vector, "a" | |
| .align 2 | |
| .globl __isr_vector | |
| __isr_vector: | |
| .long __StackTop /* Top of Stack */ | |
| .long Reset_Handler /* Reset Handler */ | |
| .long NMI_Handler /* NMI Handler*/ | |
| .long HardFault_Handler /* Hard Fault Handler*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long SVC_Handler /* SVCall Handler*/ | |
| .long 0 /* Reserved*/ | |
| .long 0 /* Reserved*/ | |
| .long PendSV_Handler /* PendSV Handler*/ | |
| .long SysTick_Handler /* SysTick Handler*/ | |
| /* External Interrupts*/ | |
| .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ | |
| .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ | |
| .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ | |
| .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ | |
| .long Reserved20_IRQHandler /* Reserved interrupt*/ | |
| .long FTFA_IRQHandler /* Command complete and read collision*/ | |
| .long LVD_LVW_DCDC_IRQHandler /* Low-voltage detect, low-voltage warning, DCDC*/ | |
| .long LLWU_IRQHandler /* Low leakage wakeup Unit*/ | |
| .long I2C0_IRQHandler /* I2C0 interrupt*/ | |
| .long I2C1_IRQHandler /* I2C1 interrupt*/ | |
| .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ | |
| .long TSI0_IRQHandler /* TSI0 single interrupt vector for all sources*/ | |
| .long LPUART0_IRQHandler /* LPUART0 status and error*/ | |
| .long TRNG0_IRQHandler /* TRNG0 interrupt*/ | |
| .long CMT_IRQHandler /* CMT interrupt*/ | |
| .long ADC0_IRQHandler /* ADC0 interrupt*/ | |
| .long CMP0_IRQHandler /* CMP0 interrupt*/ | |
| .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ | |
| .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ | |
| .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ | |
| .long RTC_IRQHandler /* RTC alarm*/ | |
| .long RTC_Seconds_IRQHandler /* RTC seconds*/ | |
| .long PIT_IRQHandler /* PIT interrupt*/ | |
| .long LTC0_IRQHandler /* LTC0 interrupt*/ | |
| .long RF2400_0_IRQHandler /* 2.4 GHz radio INT0 */ | |
| .long DAC0_IRQHandler /* DAC0 interrupt*/ | |
| .long RF2400_1_IRQHandler /* 2.4 GHz radio INT1 */ | |
| .long MCG_IRQHandler /* MCG interrupt*/ | |
| .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ | |
| .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ | |
| .long PORTA_IRQHandler /* PORTA Pin detect*/ | |
| .long PORTB_PORTC_IRQHandler /* PORTB and PORTC Pin detect*/ | |
| .size __isr_vector, . - __isr_vector | |
| /* Flash Configuration */ | |
| .section .FlashConfig, "a" | |
| .long 0xFFFFFFFF | |
| .long 0xFFFFFFFF | |
| .long 0xFFFFFFFF | |
| .long 0xFFFFFFFE | |
| /* Reset Handler */ | |
| .text | |
| .thumb | |
| .thumb_func | |
| .align 2 | |
| .globl Reset_Handler | |
| .type Reset_Handler, %function | |
| Reset_Handler: | |
| .fnstart | |
| /* Loop to copy data from read only memory to RAM. The ranges | |
| * of copy from/to are specified by following symbols evaluated in | |
| * linker script. | |
| * __etext: End of code section, i.e., begin of data sections to copy from. | |
| * __data_start__/__data_end__: RAM address range that data should be | |
| * copied to. Both must be aligned to 4 bytes boundary. */ | |
| ldr r1, =__etext | |
| ldr r2, =__data_start__ | |
| ldr r3, =__data_end__ | |
| subs r3, r2 | |
| ble .LC0 | |
| .LC1: | |
| subs r3, 4 | |
| ldr r0, [r1,r3] | |
| str r0, [r2,r3] | |
| bgt .LC1 | |
| .LC0: | |
| LDR R0, =__HeapBase | |
| LDR R1, =__HeapLimit | |
| BL _sbrkInit | |
| LDR R0, =SystemInit | |
| BLX R0 | |
| LDR R0, =_start | |
| BX R0 | |
| .pool | |
| .size Reset_Handler, . - Reset_Handler | |
| .section ".text" | |
| /* Default handler. This uses the vector in the relocated vector table */ | |
| .globl Default_Handler | |
| .type Default_Handler, %function | |
| Default_Handler: | |
| LDR R2, =__vector_tbl_reloc__ | |
| MRS R0, PSR | |
| MOVS R1, #0x3F | |
| ANDS R0, R1 | |
| LSLS R0, R0, #2 | |
| LDR R0, [R0, R2] | |
| BX R0 | |
| .size Default_Handler, . - Default_Handler | |
| /* Macro to define default handlers. Default handler | |
| * will be weak symbol and just dead loops. They can be | |
| * overwritten by other handlers */ | |
| .macro def_irq_handler handler_name | |
| .weak \handler_name | |
| .set \handler_name, Default_Handler | |
| .endm | |
| /* Exception Handlers */ | |
| def_irq_handler NMI_Handler | |
| def_irq_handler HardFault_Handler | |
| def_irq_handler SVC_Handler | |
| def_irq_handler PendSV_Handler | |
| def_irq_handler SysTick_Handler | |
| def_irq_handler DMA0_IRQHandler | |
| def_irq_handler DMA1_IRQHandler | |
| def_irq_handler DMA2_IRQHandler | |
| def_irq_handler DMA3_IRQHandler | |
| def_irq_handler Reserved20_IRQHandler | |
| def_irq_handler FTFA_IRQHandler | |
| def_irq_handler LVD_LVW_DCDC_IRQHandler | |
| def_irq_handler LLWU_IRQHandler | |
| def_irq_handler I2C0_IRQHandler | |
| def_irq_handler I2C1_IRQHandler | |
| def_irq_handler SPI0_IRQHandler | |
| def_irq_handler TSI0_IRQHandler | |
| def_irq_handler LPUART0_IRQHandler | |
| def_irq_handler TRNG0_IRQHandler | |
| def_irq_handler CMT_IRQHandler | |
| def_irq_handler ADC0_IRQHandler | |
| def_irq_handler CMP0_IRQHandler | |
| def_irq_handler TPM0_IRQHandler | |
| def_irq_handler TPM1_IRQHandler | |
| def_irq_handler TPM2_IRQHandler | |
| def_irq_handler RTC_IRQHandler | |
| def_irq_handler RTC_Seconds_IRQHandler | |
| def_irq_handler PIT_IRQHandler | |
| def_irq_handler LTC0_IRQHandler | |
| def_irq_handler RF2400_0_IRQHandler | |
| def_irq_handler DAC0_IRQHandler | |
| def_irq_handler RF2400_1_IRQHandler | |
| def_irq_handler MCG_IRQHandler | |
| def_irq_handler LPTMR0_IRQHandler | |
| def_irq_handler SPI1_IRQHandler | |
| def_irq_handler PORTA_IRQHandler | |
| def_irq_handler PORTB_PORTC_IRQHandler | |
| .end |