hw: Add initial support for Nordic nRF54L15
This adds initial support for Nordic nRF54L15.
GPIO, timers, GRTC and UART is implemented.
diff --git a/hw/bsp/nordic_pca10156/bsp.yml b/hw/bsp/nordic_pca10156/bsp.yml
new file mode 100644
index 0000000..c323504
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/bsp.yml
@@ -0,0 +1,59 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.name: "nRF54L15 PDK"
+bsp.url:
+bsp.maker: "Nordic Semiconductor"
+bsp.arch: cortex_m33
+bsp.compiler: "@apache-mynewt-core/compiler/arm-none-eabi-m33"
+bsp.linkerscript: autogenerated
+bsp.downloadscript: "hw/scripts/download.sh"
+bsp.debugscript: "hw/bsp/nordic_pca10156/nordic_pca10156_debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 32kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x0000c000
+ size: 722kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x000C0800
+ size: 722kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x00175000
+ size: 16kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00008000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x00179000
+ size: 16kB
diff --git a/hw/bsp/nordic_pca10156/include/bsp/bsp.h b/hw/bsp/nordic_pca10156/include/bsp/bsp.h
new file mode 100644
index 0000000..10bdbf7
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/include/bsp/bsp.h
@@ -0,0 +1,57 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _BSP_H_
+#define _BSP_H_
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+#define RAM_SIZE 0x40000
+
+/* LED pins */
+#define LED_1 (73)
+#define LED_2 (42)
+#define LED_3 (71)
+#define LED_4 (46)
+#define LED_BLINK_PIN (LED_1)
+
+/* Buttons */
+#define BUTTON_1 (45)
+#define BUTTON_2 (41)
+#define BUTTON_3 (40)
+#define BUTTON_4 (4)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BSP_H_ */
diff --git a/hw/bsp/nordic_pca10156/nordic_pca10156_debug.sh b/hw/bsp/nordic_pca10156/nordic_pca10156_debug.sh
new file mode 100755
index 0000000..a521c89
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/nordic_pca10156_debug.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+JLINK_DEV="Cortex-M33"
+
+jlink_debug
+
diff --git a/hw/bsp/nordic_pca10156/pkg.yml b/hw/bsp/nordic_pca10156/pkg.yml
new file mode 100644
index 0000000..de94b7e
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/pkg.yml
@@ -0,0 +1,42 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nordic_pca10156
+pkg.type: bsp
+pkg.description: BSP definition for the Nordic PCA10156 (nRF54L15-PDK)
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - nrf54
+ - nordic
+ - pca10156
+
+pkg.cflags:
+ - '-DNRF54L15_XXAA'
+ - '-DNRF_APPLICATION'
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/scripts"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf54lxx"
+ - "@apache-mynewt-core/libc/baselibc"
+ - "@apache-mynewt-core/sys/flash_map"
+ - "@apache-mynewt-core/boot/startup"
diff --git a/hw/bsp/nordic_pca10156/src/hal_bsp.c b/hw/bsp/nordic_pca10156/src/hal_bsp.c
new file mode 100644
index 0000000..a61c809
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/src/hal_bsp.c
@@ -0,0 +1,78 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <os/mynewt.h>
+#include <nrfx.h>
+#include <flash_map/flash_map.h>
+#include <hal/hal_bsp.h>
+#include <hal/hal_flash.h>
+#include <hal/hal_system.h>
+#include <mcu/nrf54l_hal.h>
+#include <mcu/nrf54l_periph.h>
+#include <bsp/bsp.h>
+
+/*
+ * What memory to include in coredump.
+ */
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = { .hbmd_start = &_ram_start, .hbmd_size = RAM_SIZE }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id == 0) {
+ return &nrf54l_flash_dev;
+ }
+
+ return NULL;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+int
+hal_bsp_power_state(int state)
+{
+ return 0;
+}
+
+void
+hal_bsp_init(void)
+{
+ /* Make sure system clocks have started */
+ hal_system_clock_start();
+
+ /* Create all available nRF54 peripherals */
+ nrf54l_periph_create();
+}
+
+void
+hal_bsp_deinit(void)
+{}
diff --git a/hw/bsp/nordic_pca10156/src/sbrk.c b/hw/bsp/nordic_pca10156/src/sbrk.c
new file mode 100644
index 0000000..38be573
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/src/sbrk.c
@@ -0,0 +1,60 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <hal/hal_bsp.h>
+
+/* put these in the data section so they are not cleared by _start */
+static char *sbrkBase __attribute__((section(".data")));
+static char *sbrkLimit __attribute__((section(".data")));
+static char *brk __attribute__((section(".data")));
+
+void
+_sbrkInit(char *base, char *limit)
+{
+ sbrkBase = base;
+ sbrkLimit = limit;
+ brk = base;
+}
+
+void *
+_sbrk(int incr)
+{
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < sbrkBase) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if (sbrkLimit - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
diff --git a/hw/bsp/nordic_pca10156/syscfg.yml b/hw/bsp/nordic_pca10156/syscfg.yml
new file mode 100644
index 0000000..28c25c6
--- /dev/null
+++ b/hw/bsp/nordic_pca10156/syscfg.yml
@@ -0,0 +1,40 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ BSP_NRF54:
+ description: 'Set to indicate that BSP has NRF54'
+ value: 1
+
+syscfg.vals:
+ # Set default pins for peripherals
+ UART_0_PIN_TX: 36
+ UART_0_PIN_RX: 37
+ UART_0_PIN_RTS: 38
+ UART_0_PIN_CTS: 39
+
+ MCU_RAM_SIZE: 256K
+ MCU_RAM_START: 0x20000000
+
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ MCU_DCDC_ENABLED: 1
+ MCU_LFCLK_SOURCE: LFXO
+
+ MYNEWT_DOWNLOADER: nrfutil
+ JLINK_TARGET: CORTEX-M33
+ MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x0
diff --git a/hw/mcu/nordic/include/nrfx_config.h b/hw/mcu/nordic/include/nrfx_config.h
index 17dacac..4c6c0e6 100644
--- a/hw/mcu/nordic/include/nrfx_config.h
+++ b/hw/mcu/nordic/include/nrfx_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2024, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -36,25 +36,33 @@
#include <nrfx_config_common.h>
#if defined(NRF51)
- #include <nrfx_config_nrf51.h>
+#include <nrfx_config_nrf51.h>
#elif defined(NRF52805_XXAA)
- #include <nrfx_config_nrf52805.h>
+#include <nrfx_config_nrf52805.h>
#elif defined(NRF52810_XXAA)
- #include <nrfx_config_nrf52810.h>
+#include <nrfx_config_nrf52810.h>
#elif defined(NRF52811_XXAA)
- #include <nrfx_config_nrf52811.h>
+#include <nrfx_config_nrf52811.h>
#elif defined(NRF52820_XXAA)
- #include <nrfx_config_nrf52820.h>
+#include <nrfx_config_nrf52820.h>
#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
- #include <nrfx_config_nrf52832.h>
+#include <nrfx_config_nrf52832.h>
#elif defined(NRF52833_XXAA)
- #include <nrfx_config_nrf52833.h>
+#include <nrfx_config_nrf52833.h>
#elif defined(NRF52840_XXAA)
- #include <nrfx_config_nrf52840.h>
+#include <nrfx_config_nrf52840.h>
#elif defined(NRF5340_XXAA_APPLICATION)
- #include <nrfx_config_nrf5340_application.h>
+#include <nrfx_config_nrf5340_application.h>
#elif defined(NRF5340_XXAA_NETWORK)
- #include <nrfx_config_nrf5340_network.h>
+#include <nrfx_config_nrf5340_network.h>
+#elif defined(NRF54H20_XXAA) && defined(NRF_APPLICATION)
+#include <nrfx_config_nrf54h20_application.h>
+#elif defined(NRF54H20_XXAA) && defined(NRF_RADIOCORE)
+#include <nrfx_config_nrf54h20_radiocore.h>
+#elif defined(NRF54H20_XXAA) && defined(NRF_PPR)
+ #include <nrfx_config_nrf54h20_ppr.h>
+#elif defined(NRF54H20_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54h20_flpr.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION)
#include <nrfx_config_nrf54h20_enga_application.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE)
@@ -63,12 +71,50 @@
#include <nrfx_config_nrf54h20_enga_ppr.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_FLPR)
#include <nrfx_config_nrf54h20_enga_flpr.h>
+#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54h20_engb_application.h>
+#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_RADIOCORE)
+ #include <nrfx_config_nrf54h20_engb_radiocore.h>
+#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_PPR)
+ #include <nrfx_config_nrf54h20_engb_ppr.h>
+#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54h20_engb_flpr.h>
+#elif defined(NRF54L05_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54l05_application.h>
+#elif defined(NRF54L05_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l05_flpr.h>
+#elif defined(NRF54L09_ENGA_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54l09_enga_application.h>
+#elif defined(NRF54L09_ENGA_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l09_enga_flpr.h>
+#elif defined(NRF54L10_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54l10_application.h>
+#elif defined(NRF54L10_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l10_flpr.h>
+#elif defined(NRF54L15_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54l15_application.h>
+#elif defined(NRF54L15_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l15_flpr.h>
#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_APPLICATION)
#include <nrfx_config_nrf54l15_enga_application.h>
+#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l15_enga_flpr.h>
+#elif defined(NRF54L20_ENGA_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf54l20_enga_application.h>
+#elif defined(NRF54L20_ENGA_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf54l20_enga_flpr.h>
#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
#include <nrfx_config_nrf91.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf9230_engb_application.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_RADIOCORE)
+ #include <nrfx_config_nrf9230_engb_radiocore.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_PPR)
+ #include <nrfx_config_nrf9230_engb_ppr.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_FLPR)
+ #include <nrfx_config_nrf9230_engb_flpr.h>
#else
- #error "Unknown device."
+ #include "nrfx_config_ext.h"
#endif
#endif // NRFX_CONFIG_H__
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/cmsis_nvic.h b/hw/mcu/nordic/nrf54lxx/include/mcu/cmsis_nvic.h
new file mode 100644
index 0000000..a75189c
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/cmsis_nvic.h
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef _CMSIS_NVIC_H_
+#define _CMSIS_NVIC_H_
+
+#include <stdint.h>
+#include <nrf.h>
+
+#define NVIC_NUM_VECTORS (16 + 270) /* CORE + MCU Peripherals */
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/cortex_m33.h b/hw/mcu/nordic/nrf54lxx/include/mcu/cortex_m33.h
new file mode 100644
index 0000000..7421ae7
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/cortex_m33.h
@@ -0,0 +1,43 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _CORTEX_M33_H_
+#define _CORTEX_M33_H_
+
+#include <nrf.h>
+#include <core_cm33.h>
+#include <syscfg/syscfg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+hal_debug_break(void)
+{
+#if !MYNEWT_VAL(MCU_DEBUG_IGNORE_BKPT)
+ __BKPT(1);
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CORTEX_M33_H_ */
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/mcu_vectors.h b/hw/mcu/nordic/nrf54lxx/include/mcu/mcu_vectors.h
new file mode 100644
index 0000000..b9185f9
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/mcu_vectors.h
@@ -0,0 +1,307 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemoryManagement_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+
+/* External Interrupts */
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SWI00_IRQHandler)
+INT_VECTOR(SWI01_IRQHandler)
+INT_VECTOR(SWI02_IRQHandler)
+INT_VECTOR(SWI03_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPU00_IRQHandler)
+INT_VECTOR(MPC00_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(AAR00_CCM00_IRQHandler)
+INT_VECTOR(ECB00_IRQHandler)
+INT_VECTOR(CRACEN_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SERIAL00_IRQHandler)
+INT_VECTOR(RRAMC_IRQHandler)
+INT_VECTOR(VPR00_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CTRLAP_IRQHandler)
+INT_VECTOR(CM33SS_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIMER00_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPU10_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIMER10_IRQHandler)
+INT_VECTOR(RTC10_IRQHandler)
+INT_VECTOR(EGU10_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RADIO_0_IRQHandler)
+INT_VECTOR(RADIO_1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPU20_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SERIAL20_IRQHandler)
+INT_VECTOR(SERIAL21_IRQHandler)
+INT_VECTOR(SERIAL22_IRQHandler)
+INT_VECTOR(EGU20_IRQHandler)
+INT_VECTOR(TIMER20_IRQHandler)
+INT_VECTOR(TIMER21_IRQHandler)
+INT_VECTOR(TIMER22_IRQHandler)
+INT_VECTOR(TIMER23_IRQHandler)
+INT_VECTOR(TIMER24_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(PDM20_IRQHandler)
+INT_VECTOR(PDM21_IRQHandler)
+INT_VECTOR(PWM20_IRQHandler)
+INT_VECTOR(PWM21_IRQHandler)
+INT_VECTOR(PWM22_IRQHandler)
+INT_VECTOR(SAADC_IRQHandler)
+INT_VECTOR(NFCT_IRQHandler)
+INT_VECTOR(TEMP_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(GPIOTE20_0_IRQHandler)
+INT_VECTOR(GPIOTE20_1_IRQHandler)
+INT_VECTOR(TAMPC_IRQHandler)
+INT_VECTOR(I2S20_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(QDEC20_IRQHandler)
+INT_VECTOR(QDEC21_IRQHandler)
+INT_VECTOR(GRTC_0_IRQHandler)
+INT_VECTOR(GRTC_1_IRQHandler)
+INT_VECTOR(GRTC_2_IRQHandler)
+INT_VECTOR(GRTC_3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPU30_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SERIAL30_IRQHandler)
+INT_VECTOR(CLOCK_POWER_IRQHandler)
+INT_VECTOR(COMP_LPCOMP_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(WDT30_IRQHandler)
+INT_VECTOR(WDT31_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(GPIOTE30_0_IRQHandler)
+INT_VECTOR(GPIOTE30_1_IRQHandler)
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_clock.h b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_clock.h
new file mode 100644
index 0000000..da3dc6b
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_clock.h
@@ -0,0 +1,50 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_NRF54L_CLOCK_
+#define H_NRF54L_CLOCK_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Request HFXO clock be turned on. Note that each request must have a
+ * corresponding release.
+ *
+ * @return int 0: hfxo was already on. 1: hfxo was turned on.
+ */
+int nrf54l_clock_hfxo_request(void);
+
+/**
+ * Release the HFXO; caller no longer needs the HFXO to be turned on. Each call
+ * to release should have been preceeded by a corresponding call to request the
+ * HFXO
+ *
+ *
+ * @return int 0: HFXO not stopped by this call (others using it) 1: HFXO
+ * stopped.
+ */
+int nrf54l_clock_hfxo_release(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_NRF54L_CLOCK_ */
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_hal.h b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_hal.h
new file mode 100644
index 0000000..2ca522d
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_hal.h
@@ -0,0 +1,55 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _NRF54L_HAL_H_
+#define _NRF54L_HAL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while (0)
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while (0)
+
+struct nrf54l_uart_cfg {
+ int8_t suc_pin_tx; /* pins for IO */
+ int8_t suc_pin_rx;
+ int8_t suc_pin_rts;
+ int8_t suc_pin_cts;
+};
+const struct nrf54l_uart_cfg *bsp_uart_config(void);
+struct hal_flash;
+extern const struct hal_flash nrf54l_flash_dev;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NRF54L_HAL_H_ */
diff --git a/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_periph.h b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_periph.h
new file mode 100644
index 0000000..0322a23
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/mcu/nrf54l_periph.h
@@ -0,0 +1,33 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _NRF54L_PERIPH_H_
+#define _NRF54L_PERIPH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void nrf54l_periph_create(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NRF54L_PERIPH_H_ */
diff --git a/hw/mcu/nordic/nrf54lxx/include/nrfx_config_nrf54l15_application.h b/hw/mcu/nordic/nrf54lxx/include/nrfx_config_nrf54l15_application.h
new file mode 100644
index 0000000..13f9457
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/include/nrfx_config_nrf54l15_application.h
@@ -0,0 +1,1800 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_CONFIG_NRF54L15_APPLICATION_H__
+#define NRFX_CONFIG_NRF54L15_APPLICATION_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+#include "syscfg/syscfg.h"
+
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief NRFX_CLOCK_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_SRC
+ *
+ * Integer value.
+ * Supported values:
+ * - RC = 0
+ * - XTAL = 1
+ * - Synth = 2
+ */
+#ifndef NRFX_CLOCK_CONFIG_LF_SRC
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
+#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
+#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_ENABLED
+#define NRFX_DPPI_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
+#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
+#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI00_ENABLED
+#define NRFX_DPPI00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI10_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI10_ENABLED
+#define NRFX_DPPI10_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI20_ENABLED
+#define NRFX_DPPI20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI30_ENABLED
+#define NRFX_DPPI30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_EGU10_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU10_ENABLED
+#define NRFX_EGU10_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU20_ENABLED
+#define NRFX_EGU20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0. Maximum: 15.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_GPIOTE20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE20_ENABLED
+#define NRFX_GPIOTE20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE30_ENABLED
+#define NRFX_GPIOTE30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_ENABLED
+#define NRFX_GRTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOEN
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOEN
+#define NRFX_GRTC_CONFIG_AUTOEN 1
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOSTART
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOSTART
+#define NRFX_GRTC_CONFIG_AUTOSTART 1
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_CLEAR_AT_INIT
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_CLEAR_AT_INIT
+#define NRFX_GRTC_CONFIG_CLEAR_AT_INIT 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+ *
+ * Integer value.
+ */
+#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 8
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+ */
+#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f0f
+#endif
+
+/**
+ * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED
+#define NRFX_GRTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL
+#define NRFX_GRTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S20_ENABLED
+#define NRFX_I2S20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_NFCT_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_NFCT_ENABLED
+#define NRFX_NFCT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
+ *
+ * Integer value. Minimum: 0. Maximum: 5.
+ */
+#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID
+#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0
+#endif
+
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
+#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
+#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PDM20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM20_ENABLED
+#define NRFX_PDM20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM21_ENABLED
+#define NRFX_PDM21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_POWER_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PPIB_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB_ENABLED
+#define NRFX_PPIB_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED
+#define NRFX_PPIB_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL
+#define NRFX_PPIB_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PPIB00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB00_ENABLED
+#define NRFX_PPIB00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB01_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB01_ENABLED
+#define NRFX_PPIB01_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB10_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB10_ENABLED
+#define NRFX_PPIB10_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB11_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB11_ENABLED
+#define NRFX_PPIB11_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB20_ENABLED
+#define NRFX_PPIB20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB21_ENABLED
+#define NRFX_PPIB21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB22_ENABLED
+#define NRFX_PPIB22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PPIB30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PPIB30_ENABLED
+#define NRFX_PPIB30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_4_ENABLED
+#define NRFX_PRS_BOX_4_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_5_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_5_ENABLED
+#define NRFX_PRS_BOX_5_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PWM20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM20_ENABLED
+#define NRFX_PWM20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM21_ENABLED
+#define NRFX_PWM21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM22_ENABLED
+#define NRFX_PWM22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_QDEC20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC20_ENABLED
+#define NRFX_QDEC20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC21_ENABLED
+#define NRFX_QDEC21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RRAMC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RRAMC_ENABLED
+#define NRFX_RRAMC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RRAMC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RRAMC_CONFIG_LOG_ENABLED
+#define NRFX_RRAMC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RRAMC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RRAMC_CONFIG_LOG_LEVEL
+#define NRFX_RRAMC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC10_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC10_ENABLED
+#define NRFX_RTC10_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC30_ENABLED
+#define NRFX_RTC30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM00_ENABLED
+#define NRFX_SPIM00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM20_ENABLED
+#define NRFX_SPIM20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM21_ENABLED
+#define NRFX_SPIM21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM22_ENABLED
+#define NRFX_SPIM22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM30_ENABLED
+#define NRFX_SPIM30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIS00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS00_ENABLED
+#define NRFX_SPIS00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS20_ENABLED
+#define NRFX_SPIS20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS21_ENABLED
+#define NRFX_SPIS21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS22_ENABLED
+#define NRFX_SPIS22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS30_ENABLED
+#define NRFX_SPIS30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER00_ENABLED
+#define NRFX_TIMER00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER10_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER10_ENABLED
+#define NRFX_TIMER10_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_TIMER20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER20_ENABLED
+#define NRFX_TIMER20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER21_ENABLED
+#define NRFX_TIMER21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER22_ENABLED
+#define NRFX_TIMER22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER23_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER23_ENABLED
+#define NRFX_TIMER23_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER24_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER24_ENABLED
+#define NRFX_TIMER24_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIM20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM20_ENABLED
+#define NRFX_TWIM20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM21_ENABLED
+#define NRFX_TWIM21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM22_ENABLED
+#define NRFX_TWIM22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM30_ENABLED
+#define NRFX_TWIM30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIS20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS20_ENABLED
+#define NRFX_TWIS20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS21_ENABLED
+#define NRFX_TWIS21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS22_ENABLED
+#define NRFX_TWIS22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS30_ENABLED
+#define NRFX_TWIS30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for configuring GPIO pins is removed from the driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for configuring PSEL registers is removed from the driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_TX_LINK
+#define NRFX_UARTE_CONFIG_TX_LINK 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_UARTE00_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE00_ENABLED
+#define NRFX_UARTE00_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE20_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE20_ENABLED
+#define NRFX_UARTE20_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE21_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE21_ENABLED
+#define NRFX_UARTE21_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE22_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE22_ENABLED
+#define NRFX_UARTE22_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE30_ENABLED
+#define NRFX_UARTE30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_WDT30_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT30_ENABLED
+#define NRFX_WDT30_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT31_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT31_ENABLED
+#define NRFX_WDT31_ENABLED 0
+#endif
+
+#endif /* NRFX_CONFIG_NRF54L15_APPLICATION_H__ */
diff --git a/hw/mcu/nordic/nrf54lxx/pkg.yml b/hw/mcu/nordic/nrf54lxx/pkg.yml
new file mode 100644
index 0000000..80d09c0
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/pkg.yml
@@ -0,0 +1,52 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/nordic/nrf54lxx
+pkg.description: MCU definition for Nordic nRF54Lxx ARM Cortex-M33 chip.
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - nrf54lxx
+ - nrf54
+ - nrfx
+
+#TODO: should be removed when dereferencing type-punned pointer is removed from nrfx's nrf_grtc.h
+pkg.cflags:
+ - -Wno-error=strict-aliasing
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/nordic"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf_common"
+
+pkg.deps.UART_0:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+
+pkg.deps.UART_1:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+
+pkg.deps.UART_2:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+
+pkg.deps.UART_3:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+
+pkg.deps.BLE_CONTROLLER:
+ - "@apache-mynewt-nimble/nimble/drivers/nrf5x"
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_flash.c b/hw/mcu/nordic/nrf54lxx/src/hal_flash.c
new file mode 100644
index 0000000..0ce4870
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_flash.c
@@ -0,0 +1,160 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <mcu/nrf54l_hal.h>
+#include <hal/hal_flash_int.h>
+#include <nrf_mem.h>
+
+#define NRF54L_FLASH_SECTOR_SZ 4096
+
+static int
+nrf54l_flash_wait_ready(void)
+{
+ int i;
+
+ for (i = 0; i < 100000; i++) {
+ if (NRF_RRAMC->READY == RRAMC_READY_READY_Ready) {
+ return 0;
+ }
+ }
+ return -1;
+}
+
+static int
+nrf54l_flash_read(const struct hal_flash *dev, uint32_t address, void *dst,
+ uint32_t num_bytes)
+{
+ memcpy(dst, (void *)address, num_bytes);
+ return 0;
+}
+
+/*
+ * Flash write is done by writing 4 bytes at a time at a word boundary.
+ */
+static int
+nrf54l_flash_write(const struct hal_flash *dev, uint32_t address,
+ const void *src, uint32_t num_bytes)
+{
+ int sr;
+ int rc = -1;
+ uint32_t val;
+ int cnt;
+ uint32_t tmp;
+
+ if (nrf54l_flash_wait_ready()) {
+ return -1;
+ }
+ __HAL_DISABLE_INTERRUPTS(sr);
+
+ NRF_RRAMC->CONFIG = RRAMC_CONFIG_WEN_Enabled; /* Enable erase OP */
+
+ tmp = address & 0x3;
+ if (tmp) {
+ if (nrf54l_flash_wait_ready()) {
+ goto out;
+ }
+ /*
+ * Starts at a non-word boundary. Read 4 bytes which were there
+ * before, update with new data, and write back.
+ */
+ val = *(uint32_t *)(address & ~0x3);
+ cnt = 4 - tmp;
+ if (cnt > num_bytes) {
+ cnt = num_bytes;
+ }
+ memcpy((uint8_t *)&val + tmp, src, cnt);
+ *(uint32_t *)(address & ~0x3) = val;
+ address += cnt;
+ num_bytes -= cnt;
+ src += cnt;
+ }
+
+ while (num_bytes >= sizeof(uint32_t)) {
+ /*
+ * Write data 4 bytes at a time.
+ */
+ if (nrf54l_flash_wait_ready()) {
+ goto out;
+ }
+ *(uint32_t *)address = *(uint32_t *)src;
+ address += sizeof(uint32_t);
+ src += sizeof(uint32_t);
+ num_bytes -= sizeof(uint32_t);
+ }
+ if (num_bytes) {
+ /*
+ * Deal with the trailing bytes.
+ */
+ val = *(uint32_t *)address;
+ memcpy(&val, src, num_bytes);
+ if (nrf54l_flash_wait_ready()) {
+ goto out;
+ }
+ *(uint32_t *)address = val;
+ }
+
+ rc = nrf54l_flash_wait_ready();
+out:
+ NRF_RRAMC->CONFIG = RRAMC_CONFIG_WEN_Disabled;
+ __HAL_ENABLE_INTERRUPTS(sr);
+ return rc;
+}
+
+static int
+nrf54l_flash_erase_sector(const struct hal_flash *dev, uint32_t sector_address)
+{
+ uint32_t val = 0xffffffff;
+
+ return nrf54l_flash_write(dev, sector_address, &val, sizeof(val));
+}
+
+static int
+nrf54l_flash_sector_info(const struct hal_flash *dev, int idx,
+ uint32_t *address, uint32_t *sz)
+{
+ assert(idx < nrf54l_flash_dev.hf_sector_cnt);
+ *address = idx * NRF54L_FLASH_SECTOR_SZ;
+ *sz = NRF54L_FLASH_SECTOR_SZ;
+ return 0;
+}
+
+static int
+nrf54l_flash_init(const struct hal_flash *dev)
+{
+ return 0;
+}
+
+static const struct hal_flash_funcs nrf54l_flash_funcs = {
+ .hff_read = nrf54l_flash_read,
+ .hff_write = nrf54l_flash_write,
+ .hff_erase_sector = nrf54l_flash_erase_sector,
+ .hff_sector_info = nrf54l_flash_sector_info,
+ .hff_init = nrf54l_flash_init
+};
+
+const struct hal_flash nrf54l_flash_dev = {
+ .hf_itf = &nrf54l_flash_funcs,
+ .hf_base_addr = NRF_MEMORY_FLASH_BASE,
+ .hf_size = NRF_MEMORY_FLASH_SIZE,
+ .hf_sector_cnt = NRF54L_FLASH_SECTOR_SZ,
+ .hf_align = MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE),
+ .hf_erased_val = 0xff,
+};
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_nvreg.c b/hw/mcu/nordic/nrf54lxx/src/hal_nvreg.c
new file mode 100644
index 0000000..03f0033
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_nvreg.c
@@ -0,0 +1,59 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <mcu/cortex_m33.h>
+#include <hal/hal_nvreg.h>
+#include <nrf.h>
+
+/* There are two GPREGRET registers on the NRF54 */
+#define HAL_NVREG_MAX (2)
+
+/* GPREGRET registers only save the 8 lsbits */
+#define HAL_NVREG_WIDTH_BYTES (1)
+
+void
+hal_nvreg_write(unsigned int reg, uint32_t val)
+{
+ if (reg < HAL_NVREG_MAX) {
+ NRF_POWER_S->GPREGRET[reg] = val;
+ }
+}
+
+uint32_t
+hal_nvreg_read(unsigned int reg)
+{
+ uint32_t val = 0;
+
+ if (reg < HAL_NVREG_MAX) {
+ val = NRF_POWER_S->GPREGRET[reg];
+ }
+
+ return val;
+}
+
+unsigned int
+hal_nvreg_get_num_regs(void)
+{
+ return HAL_NVREG_MAX;
+}
+
+unsigned int
+hal_nvreg_get_reg_width(void)
+{
+ return HAL_NVREG_WIDTH_BYTES;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_os_tick.c b/hw/mcu/nordic/nrf54lxx/src/hal_os_tick.c
new file mode 100644
index 0000000..c1ecc6d
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_os_tick.c
@@ -0,0 +1,202 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_os_tick.h>
+#include <nrf.h>
+#include <nrf_grtc.h>
+
+/* The OS scheduler requires a low-frequency timer. */
+#if MYNEWT_VAL(OS_SCHEDULING) && !MYNEWT_VAL(MCU_LFCLK_SOURCE)
+#error The OS scheduler requires a low-frequency timer; configure MCU_LFCLK_SOURCE
+#endif
+
+#define GRTC_FREQ 1000000 /* in Hz */
+#define GRTC_COMPARE_INT_MASK(ccreg) (1UL << (ccreg))
+
+/*
+ * Use two compare channels - one for os_tick and one to wake up from idle
+ * state. This way we can utilize INTERVAL register used with CC[0] for
+ * OS ticks. To wake up from idle state CC[1] channel is used.
+ */
+#define OS_TICK_CMPREG 0
+#define OS_TICK_CMPEV NRF_GRTC_EVENT_COMPARE_0
+#define OS_IDLE_CMPREG 1
+#define OS_IDLE_CMPEV NRF_GRTC_EVENT_COMPARE_1
+
+struct hal_os_tick {
+ int ticks_per_ostick;
+ os_time_t max_idle_ticks;
+ uint64_t lastocmp;
+};
+struct hal_os_tick g_hal_os_tick;
+
+static inline uint64_t
+nrf54l_os_tick_counter(void)
+{
+ uint32_t counterl_val, counterh_val, counterh;
+ uint64_t counter;
+
+ do {
+ counterl_val = nrf_grtc_sys_counter_low_get(NRF_GRTC);
+ counterh = nrf_grtc_sys_counter_high_get(NRF_GRTC);
+ counterh_val = counterh & NRF_GRTC_SYSCOUNTERH_VALUE_MASK;
+ } while (counterh & NRF_GRTC_SYSCOUNTERH_BUSY_MASK);
+
+ if (counterh & NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK) {
+ --counterh_val;
+ }
+
+ counter = ((uint64_t)counterh_val << 32) | counterl_val;
+ return counter;
+}
+
+static inline void
+nrf54l_os_idle_set_ocmp(uint64_t ocmp)
+{
+ int delta;
+ uint64_t counter;
+
+ OS_ASSERT_CRITICAL();
+ while (1) {
+ nrf_grtc_sys_counter_cc_set(NRF_GRTC, OS_IDLE_CMPREG, ocmp);
+ counter = nrf54l_os_tick_counter();
+
+ delta = ocmp - counter;
+ if (delta > 0) {
+ break;
+ }
+ ocmp += g_hal_os_tick.ticks_per_ostick;
+ }
+}
+
+static void
+nrf54l_timer_handler(void)
+{
+ int delta;
+ int ticks;
+ os_sr_t sr;
+ uint64_t counter;
+
+ os_trace_isr_enter();
+ OS_ENTER_CRITICAL(sr);
+
+ /* Calculate elapsed ticks and advance OS time. */
+ counter = nrf54l_os_tick_counter();
+ delta = counter - g_hal_os_tick.lastocmp;
+ ticks = delta / g_hal_os_tick.ticks_per_ostick;
+ os_time_advance(ticks);
+
+ /* Clear timer interrupt */
+ nrf_grtc_event_clear(NRF_GRTC, OS_TICK_CMPEV);
+ nrf_grtc_event_clear(NRF_GRTC, OS_IDLE_CMPEV);
+
+ /* Update the time associated with the most recent tick */
+ g_hal_os_tick.lastocmp =
+ g_hal_os_tick.lastocmp + ticks * g_hal_os_tick.ticks_per_ostick;
+
+ OS_EXIT_CRITICAL(sr);
+ os_trace_isr_exit();
+}
+
+void
+os_tick_idle(os_time_t ticks)
+{
+ uint64_t ocmp;
+
+ OS_ASSERT_CRITICAL();
+
+ if (ticks > 0) {
+ /*
+ * Enter tickless regime during long idle durations.
+ */
+ if (ticks > g_hal_os_tick.max_idle_ticks) {
+ ticks = g_hal_os_tick.max_idle_ticks;
+ }
+
+ /* Disable OS tick interrupt */
+ nrf_grtc_int_disable(NRF_GRTC, GRTC_COMPARE_INT_MASK(OS_TICK_CMPREG));
+
+ /* Set ocmp for wake up */
+ ocmp = g_hal_os_tick.lastocmp + (ticks * g_hal_os_tick.ticks_per_ostick);
+ nrf54l_os_idle_set_ocmp(ocmp);
+ }
+
+ __DSB();
+ __WFI();
+
+ if (ticks > 0) {
+ /*
+ * Update OS time and re-enable OS tick interrupt before anything else
+ * when coming out of the tickless regime.
+ */
+ nrf_grtc_int_enable(NRF_GRTC, GRTC_COMPARE_INT_MASK(OS_TICK_CMPREG));
+ nrf54l_timer_handler();
+ }
+}
+
+void
+os_tick_init(uint32_t os_ticks_per_sec, int prio)
+{
+ uint32_t sr;
+
+ assert(GRTC_FREQ % os_ticks_per_sec == 0);
+
+ g_hal_os_tick.lastocmp = 0;
+ g_hal_os_tick.ticks_per_ostick = GRTC_FREQ / os_ticks_per_sec;
+
+ /* XXX: selected this value by intuition, trying to make it roughly appropriate */
+ g_hal_os_tick.max_idle_ticks = (1UL << 27) / g_hal_os_tick.ticks_per_ostick;
+
+ /* disable interrupts */
+ OS_ENTER_CRITICAL(sr);
+
+ /* Set isr in vector table and enable interrupt */
+ NVIC_SetPriority(GRTC_IRQn, prio);
+ NVIC_SetVector(GRTC_IRQn, (uint32_t)nrf54l_timer_handler);
+ NVIC_EnableIRQ(GRTC_IRQn);
+
+ /*
+ * Program the NRF_GRTC to trigger an interrupt
+ * at an interval of 'ticks_per_ostick' and initialize CC channel
+ * for waking up from idle state.
+ */
+ nrf_grtc_task_trigger(NRF_GRTC, NRF_GRTC_TASK_STOP);
+ nrf_grtc_task_trigger(NRF_GRTC, NRF_GRTC_TASK_CLEAR);
+
+ nrf_grtc_event_disable(NRF_GRTC, 0xffffffff);
+
+ nrf_grtc_int_disable(NRF_GRTC, 0xffffffff);
+ nrf_grtc_int_enable(NRF_GRTC, GRTC_COMPARE_INT_MASK(OS_TICK_CMPREG));
+ nrf_grtc_int_enable(NRF_GRTC, GRTC_COMPARE_INT_MASK(OS_IDLE_CMPREG));
+
+ nrf_grtc_clksel_set(NRF_GRTC, NRF_GRTC_CLKSEL_LFXO);
+
+ nrf_grtc_event_clear(NRF_GRTC, OS_TICK_CMPEV);
+ nrf_grtc_event_clear(NRF_GRTC, OS_IDLE_CMPEV);
+ nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC, OS_TICK_CMPREG);
+ nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC, OS_IDLE_CMPREG);
+
+ nrf_grtc_sys_counter_interval_set(NRF_GRTC, g_hal_os_tick.ticks_per_ostick);
+ nrf_grtc_sys_counter_set(NRF_GRTC, true);
+ nrf_grtc_task_trigger(NRF_GRTC, NRF_GRTC_TASK_START);
+
+ OS_EXIT_CRITICAL(sr);
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_reset_cause.c b/hw/mcu/nordic/nrf54lxx/src/hal_reset_cause.c
new file mode 100644
index 0000000..b730de8
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_reset_cause.c
@@ -0,0 +1,50 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <nrf.h>
+#include <hal/hal_system.h>
+
+enum hal_reset_reason
+hal_reset_cause(void)
+{
+ static enum hal_reset_reason reason;
+ uint32_t reg;
+
+ if (reason) {
+ return reason;
+ }
+
+ reg = NRF_RESET->RESETREAS;
+
+ if (reg & (RESET_RESETREAS_DOG0_Msk | RESET_RESETREAS_DOG1_Msk |
+ RESET_RESETREAS_LOCKUP_Msk)) {
+ reason = HAL_RESET_WATCHDOG;
+ } else if (reg & RESET_RESETREAS_SREQ_Msk) {
+ reason = HAL_RESET_SOFT;
+ } else if (reg & RESET_RESETREAS_RESETPIN_Msk) {
+ reason = HAL_RESET_PIN;
+ } else if (reg & RESET_RESETREAS_OFF_Msk) {
+ reason = HAL_RESET_SYS_OFF_INT;
+ } else {
+ reason = HAL_RESET_POR; /* could also be brownout */
+ }
+
+ NRF_RESET->RESETREAS = reg;
+ return reason;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_system.c b/hw/mcu/nordic/nrf54lxx/src/hal_system.c
new file mode 100644
index 0000000..4c5123b
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_system.c
@@ -0,0 +1,114 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <syscfg/syscfg.h>
+#include <mcu/cortex_m33.h>
+#include <hal/hal_system.h>
+#include <hal/hal_debug.h>
+#include <mynewt_cm.h>
+#include <nrf.h>
+
+/**
+ * Function called at startup. Called after BSS and .data initialized but
+ * prior to the _start function.
+ *
+ * NOTE: this function is called by both the bootloader and the application.
+ * If you add code here that you do not want executed in either case you need
+ * to conditionally compile it using the config variable BOOT_LOADER (will
+ * be set to 1 in case of bootloader build)
+ *
+ */
+void
+hal_system_init(void)
+{
+ NVIC_Relocate();
+
+#if MYNEWT_VAL(MCU_DCDC_ENABLED)
+ NRF_REGULATORS->VREGMAIN.DCDCEN = 1;
+#endif
+}
+
+void
+hal_system_reset(void)
+{
+#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB)
+ hal_system_reset_cb();
+#endif
+
+ while (1) {
+ HAL_DEBUG_BREAK();
+ NVIC_SystemReset();
+ }
+}
+
+int
+hal_debugger_connected(void)
+{
+ return CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk;
+}
+
+/**
+ * hal system clock start
+ *
+ * Makes sure the LFCLK and/or HFCLK is started.
+ */
+void
+hal_system_clock_start(void)
+{
+#if MYNEWT_VAL(MCU_LFCLK_SOURCE)
+ uint32_t regmsk;
+ uint32_t regval;
+ uint32_t clksrc;
+
+ regmsk = CLOCK_LFCLK_STAT_STATE_Msk | CLOCK_LFCLK_STAT_SRC_Msk;
+ regval = CLOCK_LFCLK_STAT_STATE_Running << CLOCK_LFCLK_STAT_STATE_Pos;
+
+#if MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFXO)
+ regval |= CLOCK_LFCLK_STAT_SRC_LFXO << CLOCK_LFCLK_STAT_SRC_Pos;
+ clksrc = CLOCK_LFCLK_STAT_SRC_LFXO;
+#elif MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFSYNTH)
+ regval |= CLOCK_LFCLK_STAT_SRC_LFSYNT << CLOCK_LFCLK_STAT_SRC_Pos;
+ clksrc = CLOCK_LFCLK_STAT_SRC_LFSYNT;
+#elif MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFRC)
+ regval |= CLOCK_LFCLK_STAT_SRC_LFRC << CLOCK_LFCLK_STAT_SRC_Pos;
+ clksrc = CLOCK_LFCLK_STAT_SRC_LFRC;
+#else
+#error Unknown LFCLK source selected
+#endif
+
+ NRF_CLOCK_S->TASKS_XOSTOP = 1;
+
+ /* Check if this clock source is already running */
+ if ((NRF_CLOCK_S->LFCLK.STAT & regmsk) != regval) {
+ NRF_CLOCK_S->TASKS_LFCLKSTOP = 1;
+ NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0;
+ NRF_CLOCK_S->LFCLK.SRC = clksrc;
+ NRF_CLOCK_S->TASKS_LFCLKSTART = 1;
+
+ /* Wait here till started! */
+ while (1) {
+ if (NRF_CLOCK_S->EVENTS_LFCLKSTARTED) {
+ if ((NRF_CLOCK_S->LFCLK.STAT & regmsk) == regval) {
+ break;
+ }
+ }
+ }
+ }
+#endif
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_system_start.c b/hw/mcu/nordic/nrf54lxx/src/hal_system_start.c
new file mode 100644
index 0000000..c00221c
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_system_start.c
@@ -0,0 +1,68 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stddef.h>
+#include <inttypes.h>
+#include <mcu/cortex_m33.h>
+#include <mcu/nrf54l_hal.h>
+
+/**
+ * Boots the image described by the supplied image header.
+ *
+ * @param hdr The header for the image to boot.
+ */
+void __attribute__((naked))
+hal_system_start(void *img_start)
+{
+ uint32_t *img_data = img_start;
+
+ asm volatile(".syntax unified \n"
+ /* 1st word is stack pointer */
+ " msr msp, %0 \n"
+ /* 2nd word is a reset handler (image entry) */
+ " bx %1 \n"
+ : /* no output */
+ : "r"(img_data[0]), "r"(img_data[1]));
+}
+
+/**
+ * Boots the image described by the supplied image header.
+ * This routine is used in split-app scenario when loader decides
+ * that it wants to run the app instead.
+ *
+ * @param hdr The header for the image to boot.
+ */
+void
+hal_system_restart(void *img_start)
+{
+ int i;
+ int sr;
+
+ /*
+ * Disable interrupts, and leave the disabled.
+ * They get re-enabled when system starts coming back again.
+ */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
+ NVIC->ICER[i] = 0xffffffff;
+ }
+ (void)sr;
+
+ hal_system_start(img_start);
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_timer.c b/hw/mcu/nordic/nrf54lxx/src/hal_timer.c
new file mode 100644
index 0000000..549238a
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_timer.c
@@ -0,0 +1,698 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <assert.h>
+#include <errno.h>
+#include <os/mynewt.h>
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_timer.h>
+#include <nrf.h>
+#include <mcu/nrf54l_hal.h>
+
+/* IRQ prototype */
+typedef void (*hal_timer_irq_handler_t)(void);
+
+/* User CC 2 for reading counter, CC 3 for timer isr */
+#define NRF_TIMER_CC_READ (2)
+#define NRF_TIMER_CC_INT (3)
+
+/* Output compare 2 used for RTC timers */
+#define NRF_RTC_TIMER_CC_INT (2)
+
+/* Maximum number of hal timers used */
+#define nrf54l_hal_timer_MAX (6)
+
+/* Maximum timer frequency */
+#define NRF54L_MAX_TIMER_FREQ (16000000)
+
+struct nrf54l_hal_timer {
+ uint8_t tmr_enabled;
+ uint16_t tmr_irq_num;
+ uint8_t tmr_pad;
+ uint32_t tmr_cntr;
+ uint32_t timer_isrs;
+ uint32_t tmr_freq;
+ void *tmr_reg;
+ TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_q;
+};
+
+#if MYNEWT_VAL(TIMER_0)
+struct nrf54l_hal_timer nrf54l_hal_timer0;
+#endif
+#if MYNEWT_VAL(TIMER_1)
+struct nrf54l_hal_timer nrf54l_hal_timer1;
+#endif
+#if MYNEWT_VAL(TIMER_2)
+struct nrf54l_hal_timer nrf54l_hal_timer2;
+#endif
+#if MYNEWT_VAL(TIMER_3)
+struct nrf54l_hal_timer nrf54l_hal_timer3;
+#endif
+#if MYNEWT_VAL(TIMER_4)
+struct nrf54l_hal_timer nrf54l_hal_timer4;
+#endif
+
+static const struct nrf54l_hal_timer *nrf54l_hal_timers[nrf54l_hal_timer_MAX] = {
+#if MYNEWT_VAL(TIMER_0)
+ &nrf54l_hal_timer0,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ &nrf54l_hal_timer1,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ &nrf54l_hal_timer2,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ &nrf54l_hal_timer3,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ &nrf54l_hal_timer4,
+#else
+ NULL,
+#endif
+};
+
+/* Resolve timer number into timer structure */
+#define nrf54l_hal_timer_RESOLVE(__n, __v) \
+ if ((__n) >= nrf54l_hal_timer_MAX) { \
+ rc = EINVAL; \
+ goto err; \
+ } \
+ (__v) = (struct nrf54l_hal_timer *)nrf54l_hal_timers[(__n)]; \
+ if ((__v) == NULL) { \
+ rc = EINVAL; \
+ goto err; \
+ }
+
+/* Interrupt mask for interrupt enable/clear */
+#define NRF_TIMER_INT_MASK(x) \
+ ((1 << (uint32_t)(x)) << TIMER_INTENCLR_COMPARE0_Pos)
+
+static uint32_t
+nrf_read_timer_cntr(NRF_TIMER_Type *hwtimer)
+{
+ uint32_t tcntr;
+
+ /* Force a capture of the timer into 'cntr' capture channel; read it */
+ hwtimer->TASKS_CAPTURE[NRF_TIMER_CC_READ] = 1;
+ tcntr = hwtimer->CC[NRF_TIMER_CC_READ];
+
+ return tcntr;
+}
+
+/**
+ * Set the OCMP used by the timer to the desired expiration tick
+ *
+ * NOTE: Must be called with interrupts disabled.
+ *
+ * @param bsptimer Pointer to timer.
+ * @param expiry Expiration tick
+ */
+static void
+nrf_timer_set_ocmp(struct nrf54l_hal_timer *bsptimer, uint32_t expiry)
+{
+ NRF_TIMER_Type *hwtimer;
+
+ hwtimer = bsptimer->tmr_reg;
+
+ /* Disable ocmp interrupt and set new value */
+ hwtimer->INTENCLR = NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT);
+
+ /* Set output compare register to timer expiration */
+ hwtimer->CC[NRF_TIMER_CC_INT] = expiry;
+
+ /* Clear interrupt flag */
+ hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT] = 0;
+
+ /* Enable the output compare interrupt */
+ hwtimer->INTENSET = NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT);
+
+ /* Force interrupt to occur as we may have missed it */
+ if ((int32_t)(nrf_read_timer_cntr(hwtimer) - expiry) >= 0) {
+ NVIC_SetPendingIRQ(bsptimer->tmr_irq_num);
+ }
+}
+
+/* Disable output compare used for timer */
+static void
+nrf_timer_disable_ocmp(NRF_TIMER_Type *hwtimer)
+{
+ hwtimer->INTENCLR = NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT);
+}
+
+#if (MYNEWT_VAL(TIMER_0) || MYNEWT_VAL(TIMER_1) || MYNEWT_VAL(TIMER_2) || \
+ MYNEWT_VAL(TIMER_3) || MYNEWT_VAL(TIMER_4))
+static void
+hal_timer_chk_queue(struct nrf54l_hal_timer *bsptimer)
+{
+ uint32_t tcntr;
+ uint32_t ctx;
+ struct hal_timer *timer;
+
+ /* disable interrupts */
+ __HAL_DISABLE_INTERRUPTS(ctx);
+ while ((timer = TAILQ_FIRST(&bsptimer->hal_timer_q)) != NULL) {
+ tcntr = nrf_read_timer_cntr(bsptimer->tmr_reg);
+ if ((int32_t)(tcntr - timer->expiry) >= 0) {
+ TAILQ_REMOVE(&bsptimer->hal_timer_q, timer, link);
+ timer->link.tqe_prev = NULL;
+ timer->cb_func(timer->cb_arg);
+ } else {
+ break;
+ }
+ }
+
+ /* Any timers left on queue? If so, we need to set OCMP */
+ timer = TAILQ_FIRST(&bsptimer->hal_timer_q);
+ if (timer) {
+ nrf_timer_set_ocmp(bsptimer, timer->expiry);
+ } else {
+ nrf_timer_disable_ocmp(bsptimer->tmr_reg);
+ }
+ __HAL_ENABLE_INTERRUPTS(ctx);
+}
+#endif
+
+/**
+ * Generic HAL timer irq handler.
+ *
+ * @param bsptimer Pointer to timer.
+ */
+#if (MYNEWT_VAL(TIMER_0) || MYNEWT_VAL(TIMER_1) || MYNEWT_VAL(TIMER_2) || \
+ MYNEWT_VAL(TIMER_3) || MYNEWT_VAL(TIMER_4))
+static void
+hal_timer_irq_handler(struct nrf54l_hal_timer *bsptimer)
+{
+ uint32_t compare;
+ NRF_TIMER_Type *hwtimer;
+
+ os_trace_isr_enter();
+
+ /* Check interrupt source. If set, clear them */
+ hwtimer = bsptimer->tmr_reg;
+ compare = hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT];
+ if (compare) {
+ hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT] = 0;
+ }
+
+ /* Count # of timer isrs */
+ ++bsptimer->timer_isrs;
+
+ /*
+ * NOTE: we dont check the 'compare' variable here due to how the timer
+ * is implemented on this chip. There is no way to force an output
+ * compare, so if we are late setting the output compare (i.e. the timer
+ * counter is already passed the output compare value), we use the NVIC
+ * to set a pending interrupt. This means that there will be no compare
+ * flag set, so all we do is check to see if the compare interrupt is
+ * enabled.
+ */
+ if (hwtimer->INTENCLR & NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT)) {
+ hal_timer_chk_queue(bsptimer);
+ /* XXX: Recommended by nordic to make sure interrupts are cleared */
+ compare = hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT];
+ }
+
+ os_trace_isr_exit();
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+void
+nrf54l_timer0_irq_handler(void)
+{
+ hal_timer_irq_handler(&nrf54l_hal_timer0);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_1)
+void
+nrf54l_timer1_irq_handler(void)
+{
+ hal_timer_irq_handler(&nrf54l_hal_timer1);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_2)
+void
+nrf54l_timer2_irq_handler(void)
+{
+ hal_timer_irq_handler(&nrf54l_hal_timer2);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_3)
+void
+nrf54l_timer3_irq_handler(void)
+{
+ hal_timer_irq_handler(&nrf54l_hal_timer3);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_4)
+void
+nrf54l_timer4_irq_handler(void)
+{
+ hal_timer_irq_handler(&nrf54l_hal_timer4);
+}
+#endif
+
+/**
+ * Initialize platform specific timer items
+ *
+ * @param timer_num Timer number to initialize
+ * @param cfg Pointer to platform specific configuration
+ *
+ * @return int 0: success; error code otherwise
+ */
+int
+hal_timer_init(int timer_num, void *cfg)
+{
+ int rc;
+ uint16_t irq_num;
+ struct nrf54l_hal_timer *bsptimer;
+ void *hwtimer;
+ hal_timer_irq_handler_t irq_isr;
+
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ /* If timer is enabled do not allow init */
+ if (bsptimer->tmr_enabled) {
+ rc = EINVAL;
+ goto err;
+ }
+
+ switch (timer_num) {
+#if MYNEWT_VAL(TIMER_0)
+ case 0:
+ irq_num = TIMER20_IRQn;
+ hwtimer = NRF_TIMER20;
+ irq_isr = nrf54l_timer0_irq_handler;
+ break;
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ case 1:
+ irq_num = TIMER21_IRQn;
+ hwtimer = NRF_TIMER21;
+ irq_isr = nrf54l_timer1_irq_handler;
+ break;
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ case 2:
+ irq_num = TIMER22_IRQn;
+ hwtimer = NRF_TIMER22;
+ irq_isr = nrf54l_timer2_irq_handler;
+ break;
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ case 3:
+ irq_num = TIMER23_IRQn;
+ hwtimer = NRF_TIMER23;
+ irq_isr = nrf54l_timer3_irq_handler;
+ break;
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ case 4:
+ irq_num = TIMER24_IRQn;
+ hwtimer = NRF_TIMER24;
+ irq_isr = nrf54l_timer4_irq_handler;
+ break;
+#endif
+ default:
+ hwtimer = NULL;
+ break;
+ }
+
+ if (hwtimer == NULL) {
+ rc = EINVAL;
+ goto err;
+ }
+
+ bsptimer->tmr_reg = hwtimer;
+ bsptimer->tmr_irq_num = irq_num;
+
+ /* Disable IRQ, set priority and set vector in table */
+ NVIC_DisableIRQ(irq_num);
+ NVIC_SetPriority(irq_num, (1 << __NVIC_PRIO_BITS) - 1);
+ NVIC_SetVector(irq_num, (uint32_t)irq_isr);
+
+ return 0;
+
+err:
+ return rc;
+}
+
+/**
+ * Configure a timer to run at the desired frequency. This starts the timer.
+ *
+ * @param timer_num
+ * @param freq_hz
+ *
+ * @return int
+ */
+int
+hal_timer_config(int timer_num, uint32_t freq_hz)
+{
+ int rc;
+ uint8_t prescaler;
+ uint32_t ctx;
+ uint32_t div;
+ uint32_t min_delta;
+ uint32_t max_delta;
+ struct nrf54l_hal_timer *bsptimer;
+ NRF_TIMER_Type *hwtimer;
+
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ /* Set timer to desired frequency */
+ div = NRF54L_MAX_TIMER_FREQ / freq_hz;
+
+ /*
+ * Largest prescaler is 2^9 and must make sure frequency not too high.
+ * If hwtimer is NULL it means that the timer was not initialized prior
+ * to call.
+ */
+ if (bsptimer->tmr_enabled || (div == 0) || (div > 512) ||
+ (bsptimer->tmr_reg == NULL)) {
+ rc = EINVAL;
+ goto err;
+ }
+
+ if (div == 1) {
+ prescaler = 0;
+ } else {
+ /* Find closest prescaler */
+ for (prescaler = 1; prescaler < 10; ++prescaler) {
+ if (div <= (1 << prescaler)) {
+ min_delta = div - (1 << (prescaler - 1));
+ max_delta = (1 << prescaler) - div;
+ if (min_delta < max_delta) {
+ prescaler -= 1;
+ }
+ break;
+ }
+ }
+ }
+
+ /* Now set the actual frequency */
+ bsptimer->tmr_freq = NRF54L_MAX_TIMER_FREQ / (1 << prescaler);
+ bsptimer->tmr_enabled = 1;
+
+ /* disable interrupts */
+ __HAL_DISABLE_INTERRUPTS(ctx);
+
+ /* Make sure XO (HFXO) is started */
+ if ((NRF_CLOCK_S->XO.STAT & CLOCK_XO_STAT_STATE_Msk) !=
+ (CLOCK_XO_STAT_STATE_Running << CLOCK_XO_STAT_STATE_Pos)) {
+ NRF_CLOCK_S->EVENTS_XOSTARTED = 0;
+ NRF_CLOCK_S->TASKS_XOSTART = 1;
+ while (1) {
+ if ((NRF_CLOCK_S->EVENTS_XOSTARTED != 0)) {
+ break;
+ }
+ }
+ }
+
+ hwtimer = bsptimer->tmr_reg;
+
+ /* Stop the timer first */
+ hwtimer->TASKS_STOP = 1;
+ hwtimer->TASKS_CLEAR = 1;
+
+ /* Put the timer in timer mode using 32 bits. */
+ hwtimer->MODE = TIMER_MODE_MODE_Timer;
+ hwtimer->BITMODE = TIMER_BITMODE_BITMODE_32Bit;
+
+ /* Set the pre-scalar */
+ hwtimer->PRESCALER = prescaler;
+
+ /* Start the timer */
+ hwtimer->TASKS_START = 1;
+
+ NVIC_EnableIRQ(bsptimer->tmr_irq_num);
+
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+ return 0;
+
+err:
+ return rc;
+}
+
+/**
+ * De-initialize a HW timer.
+ *
+ * @param timer_num
+ *
+ * @return int
+ */
+int
+hal_timer_deinit(int timer_num)
+{
+ int rc;
+ uint32_t ctx;
+ struct nrf54l_hal_timer *bsptimer;
+ NRF_TIMER_Type *hwtimer;
+
+ rc = 0;
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ __HAL_DISABLE_INTERRUPTS(ctx);
+ hwtimer = (NRF_TIMER_Type *)bsptimer->tmr_reg;
+ hwtimer->INTENCLR = NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT);
+ hwtimer->TASKS_STOP = 1;
+ hwtimer->TASKS_CLEAR = 1;
+
+ bsptimer->tmr_enabled = 0;
+ bsptimer->tmr_reg = NULL;
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+err:
+ return rc;
+}
+
+/**
+ * Get the resolution of the timer. This is the timer period, in nanoseconds
+ *
+ * @param timer_num
+ *
+ * @return uint32_t The
+ */
+uint32_t
+hal_timer_get_resolution(int timer_num)
+{
+ int rc;
+ uint32_t resolution;
+ struct nrf54l_hal_timer *bsptimer;
+
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ resolution = 1000000000 / bsptimer->tmr_freq;
+ return resolution;
+
+err:
+ rc = 0;
+ return rc;
+}
+
+/**
+ * Returns the timer counter. NOTE: if the timer is a 16-bit timer, only
+ * the lower 16 bits are valid. If the timer is a 64-bit timer, only the
+ * low 32-bits are returned.
+ *
+ * @return uint32_t The timer counter register.
+ */
+uint32_t
+hal_timer_read(int timer_num)
+{
+ int rc;
+ uint32_t tcntr;
+ struct nrf54l_hal_timer *bsptimer;
+
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ tcntr = nrf_read_timer_cntr(bsptimer->tmr_reg);
+
+ return tcntr;
+
+ /* Assert here since there is no invalid return code */
+err:
+ assert(0);
+ rc = 0;
+ return rc;
+}
+
+/**
+ * Blocking delay for n ticks
+ *
+ * @param timer_num
+ * @param ticks
+ *
+ * @return int 0 on success; error code otherwise.
+ */
+int
+hal_timer_delay(int timer_num, uint32_t ticks)
+{
+ uint32_t until;
+
+ until = hal_timer_read(timer_num) + ticks;
+ while ((int32_t)(hal_timer_read(timer_num) - until) <= 0) {
+ /* Loop here till finished */
+ }
+
+ return 0;
+}
+
+/**
+ * Initialize the HAL timer structure with the callback and the callback
+ * argument. Also initializes the HW specific timer pointer.
+ *
+ * @param cb_func
+ *
+ * @return int
+ */
+int
+hal_timer_set_cb(int timer_num, struct hal_timer *timer, hal_timer_cb cb_func,
+ void *arg)
+{
+ int rc;
+ struct nrf54l_hal_timer *bsptimer;
+
+ nrf54l_hal_timer_RESOLVE(timer_num, bsptimer);
+
+ timer->cb_func = cb_func;
+ timer->cb_arg = arg;
+ timer->link.tqe_prev = NULL;
+ timer->bsp_timer = bsptimer;
+
+ rc = 0;
+
+err:
+ return rc;
+}
+
+int
+hal_timer_start(struct hal_timer *timer, uint32_t ticks)
+{
+ int rc;
+ uint32_t tick;
+ struct nrf54l_hal_timer *bsptimer;
+
+ /* Set the tick value at which the timer should expire */
+ bsptimer = (struct nrf54l_hal_timer *)timer->bsp_timer;
+ tick = nrf_read_timer_cntr(bsptimer->tmr_reg) + ticks;
+ rc = hal_timer_start_at(timer, tick);
+ return rc;
+}
+
+int
+hal_timer_start_at(struct hal_timer *timer, uint32_t tick)
+{
+ uint32_t ctx;
+ struct hal_timer *entry;
+ struct nrf54l_hal_timer *bsptimer;
+
+ if (timer == NULL || timer->link.tqe_prev != NULL || timer->cb_func == NULL) {
+ return EINVAL;
+ }
+ bsptimer = (struct nrf54l_hal_timer *)timer->bsp_timer;
+ timer->expiry = tick;
+
+ __HAL_DISABLE_INTERRUPTS(ctx);
+
+ if (TAILQ_EMPTY(&bsptimer->hal_timer_q)) {
+ TAILQ_INSERT_HEAD(&bsptimer->hal_timer_q, timer, link);
+ } else {
+ TAILQ_FOREACH(entry, &bsptimer->hal_timer_q, link) {
+ if ((int32_t)(timer->expiry - entry->expiry) < 0) {
+ TAILQ_INSERT_BEFORE(entry, timer, link);
+ break;
+ }
+ }
+ if (!entry) {
+ TAILQ_INSERT_TAIL(&bsptimer->hal_timer_q, timer, link);
+ }
+ }
+
+ /* If this is the head, we need to set new OCMP */
+ if (timer == TAILQ_FIRST(&bsptimer->hal_timer_q)) {
+ nrf_timer_set_ocmp(bsptimer, timer->expiry);
+ }
+
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+ return 0;
+}
+
+/**
+ * Stop a timer.
+ *
+ * @param timer
+ *
+ * @return int
+ */
+int
+hal_timer_stop(struct hal_timer *timer)
+{
+ uint32_t ctx;
+ int reset_ocmp;
+ struct hal_timer *entry = NULL;
+ struct nrf54l_hal_timer *bsptimer;
+
+ if (timer == NULL) {
+ return EINVAL;
+ }
+
+ bsptimer = (struct nrf54l_hal_timer *)timer->bsp_timer;
+
+ __HAL_DISABLE_INTERRUPTS(ctx);
+
+ if (timer->link.tqe_prev != NULL) {
+ reset_ocmp = 0;
+ if (timer == TAILQ_FIRST(&bsptimer->hal_timer_q)) {
+ /* If first on queue, we will need to reset OCMP */
+ entry = TAILQ_NEXT(timer, link);
+ reset_ocmp = 1;
+ }
+ TAILQ_REMOVE(&bsptimer->hal_timer_q, timer, link);
+ timer->link.tqe_prev = NULL;
+ if (reset_ocmp) {
+ if (entry) {
+ nrf_timer_set_ocmp((struct nrf54l_hal_timer *)entry->bsp_timer,
+ entry->expiry);
+ } else {
+ nrf_timer_disable_ocmp(bsptimer->tmr_reg);
+ }
+ }
+ }
+
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+ return 0;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_uart.c b/hw/mcu/nordic/nrf54lxx/src/hal_uart.c
new file mode 100644
index 0000000..6bc1683
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_uart.c
@@ -0,0 +1,449 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_uart.h>
+#include <mcu/cmsis_nvic.h>
+#include <bsp/bsp.h>
+#include <nrf.h>
+#include <mcu/nrf54l_hal.h>
+
+#define UARTE_INT_ENDTX UARTE_INTEN_DMATXEND_Msk
+#define UARTE_INT_ENDRX UARTE_INTEN_DMARXEND_Msk
+#define UARTE_CONFIG_PARITY UARTE_CONFIG_PARITY_Msk
+#define UARTE_CONFIG_PARITY_ODD UARTE_CONFIG_PARITYTYPE_Msk
+#define UARTE_CONFIG_HWFC UARTE_CONFIG_HWFC_Msk
+#define UARTE_ENABLE UARTE_ENABLE_ENABLE_Enabled
+#define UARTE_DISABLE UARTE_ENABLE_ENABLE_Disabled
+
+struct hal_uart {
+ uint8_t u_open : 1;
+ uint8_t u_rx_stall : 1;
+ uint8_t u_tx_started : 1;
+ uint8_t u_rx_buf;
+ uint8_t u_tx_buf[8];
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+
+ NRF_UARTE_Type *nrf_uart;
+ uint32_t handler;
+ IRQn_Type irqn;
+};
+
+#if MYNEWT_VAL(UART_0)
+static struct hal_uart uart0;
+#endif
+#if MYNEWT_VAL(UART_1)
+static struct hal_uart uart1;
+#endif
+#if MYNEWT_VAL(UART_2)
+static struct hal_uart uart2;
+#endif
+#if MYNEWT_VAL(UART_3)
+static struct hal_uart uart3;
+#endif
+
+static struct hal_uart *
+hal_uart_get(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ return &uart0;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ return &uart1;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ return &uart2;
+#endif
+ default:
+ return NULL;
+ }
+}
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ struct hal_uart *u = hal_uart_get(port);
+
+ if (!u || u->u_open) {
+ return -1;
+ }
+ u->u_rx_func = rx_func;
+ u->u_tx_func = tx_func;
+ u->u_tx_done = tx_done;
+ u->u_func_arg = arg;
+
+ return 0;
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+ int data;
+ int i;
+
+ for (i = 0; i < sizeof(u->u_tx_buf); i++) {
+ data = u->u_tx_func(u->u_func_arg);
+ if (data < 0) {
+ break;
+ }
+ u->u_tx_buf[i] = data;
+ }
+ return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ int sr;
+ int rc;
+
+ if (!u) {
+ return;
+ }
+
+ __HAL_DISABLE_INTERRUPTS(sr);
+ if (u->u_tx_started == 0) {
+ rc = hal_uart_tx_fill_buf(u);
+ if (rc > 0) {
+ u->nrf_uart->INTENSET = UARTE_INT_ENDTX;
+ u->nrf_uart->DMA.TX.PTR = (uint32_t)&u->u_tx_buf;
+ u->nrf_uart->DMA.TX.MAXCNT = rc;
+ u->nrf_uart->TASKS_DMA.TX.START = 1;
+ u->u_tx_started = 1;
+ }
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ int sr;
+ int rc;
+
+ if (!u) {
+ return;
+ }
+
+ if (u->u_rx_stall) {
+ __HAL_DISABLE_INTERRUPTS(sr);
+ rc = u->u_rx_func(u->u_func_arg, u->u_rx_buf);
+ if (rc == 0) {
+ u->u_rx_stall = 0;
+ u->nrf_uart->TASKS_DMA.RX.START = 1;
+ }
+
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ struct hal_uart *u = hal_uart_get(port);
+
+ if (!u || !u->u_open) {
+ return;
+ }
+
+ /* If we have started, wait until the current uart dma buffer is done */
+ if (u->u_tx_started) {
+ while (u->nrf_uart->EVENTS_DMA.TX.END == 0) {
+ /* Wait here until the dma is finished */
+ }
+ }
+
+ u->nrf_uart->EVENTS_DMA.TX.END = 0;
+ u->nrf_uart->DMA.TX.PTR = (uint32_t)&data;
+ u->nrf_uart->DMA.TX.MAXCNT = 1;
+ u->nrf_uart->TASKS_DMA.TX.START = 1;
+
+ while (u->nrf_uart->EVENTS_DMA.TX.END == 0) {
+ /* Wait till done */
+ }
+
+ /* Stop the uart */
+ u->nrf_uart->TASKS_DMA.TX.STOP = 1;
+}
+
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1) || MYNEWT_VAL(UART_2) || \
+ MYNEWT_VAL(UART_3)
+static void
+uart_irq_handler(struct hal_uart *u)
+{
+ NRF_UARTE_Type *nrf_uart = u->nrf_uart;
+ int rc;
+
+ os_trace_isr_enter();
+
+ if (nrf_uart->EVENTS_DMA.TX.END) {
+ nrf_uart->EVENTS_DMA.TX.END = 0;
+ rc = hal_uart_tx_fill_buf(u);
+ if (rc > 0) {
+ nrf_uart->DMA.TX.PTR = (uint32_t)&u->u_tx_buf;
+ nrf_uart->DMA.TX.MAXCNT = rc;
+ nrf_uart->TASKS_DMA.TX.START = 1;
+ } else {
+ if (u->u_tx_done) {
+ u->u_tx_done(u->u_func_arg);
+ }
+ nrf_uart->INTENCLR = UARTE_INT_ENDTX;
+ nrf_uart->TASKS_DMA.TX.STOP = 1;
+ u->u_tx_started = 0;
+ }
+ }
+ if (nrf_uart->EVENTS_DMA.RX.END) {
+ nrf_uart->EVENTS_DMA.RX.END = 0;
+ rc = u->u_rx_func(u->u_func_arg, u->u_rx_buf);
+ if (rc < 0) {
+ u->u_rx_stall = 1;
+ } else {
+ nrf_uart->TASKS_DMA.RX.START = 1;
+ }
+ }
+ os_trace_isr_exit();
+}
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static void
+uart0_irq_handler(void)
+{
+ uart_irq_handler(&uart0);
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static void
+uart1_irq_handler(void)
+{
+ uart_irq_handler(&uart1);
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+static void
+uart2_irq_handler(void)
+{
+ uart_irq_handler(&uart2);
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+static void
+uart3_irq_handler(void)
+{
+ uart_irq_handler(&uart3);
+}
+#endif
+
+static uint32_t
+hal_uart_baudrate(int baudrate)
+{
+ switch (baudrate) {
+ case 1200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1200;
+ case 2400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud2400;
+ case 4800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud4800;
+ case 9600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud9600;
+ case 14400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud14400;
+ case 19200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud19200;
+ case 28800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud28800;
+ case 38400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud38400;
+ case 56000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud56000;
+ case 57600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud57600;
+ case 76800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud76800;
+ case 115200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud115200;
+ case 230400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud230400;
+ case 250000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud250000;
+ case 460800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud460800;
+ case 921600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud921600;
+ case 1000000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1M;
+ default:
+ return 0;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ struct nrf54l_uart_cfg *cfg = arg;
+
+ if (!u) {
+ return -1;
+ }
+
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ u->nrf_uart = NRF_UARTE20;
+ u->handler = (uint32_t)uart0_irq_handler;
+ u->irqn = UARTE20_IRQn;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ u->nrf_uart = NRF_UARTE21;
+ u->handler = (uint32_t)uart1_irq_handler;
+ u->irqn = UARTE21_IRQn;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ u->nrf_uart = NRF_UARTE22;
+ u->handler = (uint32_t)uart2_irq_handler;
+ u->irqn = UARTE22_IRQn;
+ break;
+#endif
+ default:
+ assert(false);
+ }
+
+ u->nrf_uart->PSEL.TXD = cfg->suc_pin_tx;
+ u->nrf_uart->PSEL.RXD = cfg->suc_pin_rx;
+ u->nrf_uart->PSEL.RTS = cfg->suc_pin_rts;
+ u->nrf_uart->PSEL.CTS = cfg->suc_pin_cts;
+
+ NVIC_SetVector(u->irqn, u->handler);
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ uint32_t cfg_reg = 0;
+ uint32_t baud_reg;
+
+ if (!u || u->u_open) {
+ return -1;
+ }
+
+ /*
+ * pin config
+ * UART config
+ * nvic config
+ * enable uart
+ */
+ if (databits != 8) {
+ return -1;
+ }
+ if (stopbits != 1) {
+ return -1;
+ }
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ break;
+ case HAL_UART_PARITY_ODD:
+ cfg_reg |= UARTE_CONFIG_PARITY | UARTE_CONFIG_PARITY_ODD;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ cfg_reg |= UARTE_CONFIG_PARITY;
+ break;
+ }
+
+ switch (flow_ctl) {
+ case HAL_UART_FLOW_CTL_NONE:
+ break;
+ case HAL_UART_FLOW_CTL_RTS_CTS:
+ cfg_reg |= UARTE_CONFIG_HWFC;
+ if (u->nrf_uart->PSEL.RTS == 0xffffffff || u->nrf_uart->PSEL.CTS == 0xffffffff) {
+ /*
+ * Can't turn on HW flow control if pins to do that are not
+ * defined.
+ */
+ assert(0);
+ return -1;
+ }
+ break;
+ }
+ baud_reg = hal_uart_baudrate(baudrate);
+ if (baud_reg == 0) {
+ return -1;
+ }
+ u->nrf_uart->ENABLE = 0;
+ u->nrf_uart->INTENCLR = 0xffffffff;
+ u->nrf_uart->BAUDRATE = baud_reg;
+ u->nrf_uart->CONFIG = cfg_reg;
+
+ NVIC_EnableIRQ(u->irqn);
+
+ u->nrf_uart->ENABLE = UARTE_ENABLE;
+
+ u->nrf_uart->INTENSET = UARTE_INT_ENDRX;
+ u->nrf_uart->DMA.RX.PTR = (uint32_t)&u->u_rx_buf;
+ u->nrf_uart->DMA.RX.MAXCNT = sizeof(u->u_rx_buf);
+ u->nrf_uart->TASKS_DMA.RX.START = 1;
+
+ u->u_rx_stall = 0;
+ u->u_tx_started = 0;
+ u->u_open = 1;
+
+ return 0;
+}
+
+int
+hal_uart_close(int port)
+{
+ volatile struct hal_uart *u = hal_uart_get(port);
+
+ if (!u) {
+ return -1;
+ }
+
+ u->u_open = 0;
+ while (u->u_tx_started) {
+ /* Wait here until the dma is finished */
+ }
+ u->nrf_uart->ENABLE = 0;
+ u->nrf_uart->INTENCLR = 0xffffffff;
+
+ return 0;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/hal_watchdog.c b/hw/mcu/nordic/nrf54lxx/src/hal_watchdog.c
new file mode 100644
index 0000000..2090787
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/hal_watchdog.c
@@ -0,0 +1,76 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_watchdog.h>
+#include <mcu/cmsis_nvic.h>
+#include <nrf.h>
+
+static void
+nrf54l_hal_wdt_default_handler(void)
+{
+ assert(0);
+}
+
+/**@brief WDT interrupt handler. */
+static void
+nrf54l_wdt_irq_handler(void)
+{
+ os_trace_isr_enter();
+ if (NRF_WDT30->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
+ NRF_WDT30->EVENTS_TIMEOUT = 0;
+ nrf54l_hal_wdt_default_handler();
+ }
+ os_trace_isr_exit();
+}
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ uint64_t expiration;
+ NRF_WDT30->CONFIG = WDT_CONFIG_SLEEP_Msk;
+
+ /* Convert msec timeout to counts of a 32768 crystal */
+ expiration = ((uint64_t)expire_msecs * 32768) / 1000;
+ NRF_WDT30->CRV = (uint32_t)expiration;
+
+ NRF_WDT30->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
+
+ NVIC_SetVector(WDT30_IRQn, (uint32_t)nrf54l_wdt_irq_handler);
+ NVIC_SetPriority(WDT30_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+ NVIC_ClearPendingIRQ(WDT30_IRQn);
+ NVIC_EnableIRQ(WDT30_IRQn);
+ NRF_WDT30->RREN |= 0x1;
+
+ return 0;
+}
+
+void
+hal_watchdog_enable(void)
+{
+ NRF_WDT30->INTENSET = WDT_INTENSET_TIMEOUT_Msk;
+ NRF_WDT30->TASKS_START = 1;
+}
+
+void
+hal_watchdog_tickle(void)
+{
+ NRF_WDT30->RR[0] = WDT_RR_RR_Reload;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/nrf54l_clock.c b/hw/mcu/nordic/nrf54lxx/src/nrf54l_clock.c
new file mode 100644
index 0000000..8a83b37
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/nrf54l_clock.c
@@ -0,0 +1,86 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+#include <stdint.h>
+#include "mcu/nrf54l_hal.h"
+#include "nrfx.h"
+
+static uint8_t nrf54l_clock_hfxo_refcnt;
+
+/**
+ * Request HFXO clock be turned on. Note that each request must have a
+ * corresponding release.
+ *
+ * @return int 0: hfxo was already on. 1: hfxo was turned on.
+ */
+int
+nrf54l_clock_hfxo_request(void)
+{
+ int started;
+ uint32_t ctx;
+
+ started = 0;
+ __HAL_DISABLE_INTERRUPTS(ctx);
+ assert(nrf54l_clock_hfxo_refcnt < 0xff);
+ if (nrf54l_clock_hfxo_refcnt == 0) {
+ if ((NRF_CLOCK->XO.STAT & CLOCK_XO_STAT_STATE_Msk) !=
+ (CLOCK_XO_STAT_STATE_Running << CLOCK_XO_STAT_STATE_Pos)) {
+ NRF_CLOCK->EVENTS_XOSTARTED = 0;
+ NRF_CLOCK->TASKS_XOSTART = 1;
+ while (1) {
+ if ((NRF_CLOCK->EVENTS_XOSTARTED != 0)) {
+ break;
+ }
+ }
+ }
+ started = 1;
+ }
+ ++nrf54l_clock_hfxo_refcnt;
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+ return started;
+}
+
+/**
+ * Release the HFXO. This means that the caller no longer needs the HFXO to be
+ * turned on. Each call to release should have been preceeded by a
+ * corresponding call to request the HFXO
+ *
+ *
+ * @return int 0: HFXO not stopped by this call (others using it) 1: HFXO
+ * stopped.
+ */
+int
+nrf54l_clock_hfxo_release(void)
+{
+ int stopped;
+ uint32_t ctx;
+
+ stopped = 0;
+ __HAL_DISABLE_INTERRUPTS(ctx);
+ assert(nrf54l_clock_hfxo_refcnt != 0);
+ --nrf54l_clock_hfxo_refcnt;
+ if (nrf54l_clock_hfxo_refcnt == 0) {
+ NRF_CLOCK_S->TASKS_XOSTOP = 1;
+ stopped = 1;
+ }
+ __HAL_ENABLE_INTERRUPTS(ctx);
+
+ return stopped;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/nrf54l_hw_id.c b/hw/mcu/nordic/nrf54lxx/src/nrf54l_hw_id.c
new file mode 100644
index 0000000..af026a1
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/nrf54l_hw_id.c
@@ -0,0 +1,43 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <hal/hal_bsp.h>
+#include <nrf.h>
+#include <os/os.h>
+
+int
+hal_bsp_hw_id_len(void)
+{
+ return sizeof(NRF_FICR->INFO.DEVICEID);
+}
+
+/*
+ * These values are generated at random.
+ * DEVICEID
+ */
+int
+hal_bsp_hw_id(uint8_t *id, int max_len)
+{
+ max_len = min(sizeof(NRF_FICR->INFO.DEVICEID), max_len);
+
+ memcpy(id, (void *)&NRF_FICR->INFO.DEVICEID, max_len);
+
+ return max_len;
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/nrf54l_periph.c b/hw/mcu/nordic/nrf54lxx/src/nrf54l_periph.c
new file mode 100644
index 0000000..7d5e28b
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/nrf54l_periph.c
@@ -0,0 +1,122 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <syscfg/syscfg.h>
+#include <mcu/nrf54l_hal.h>
+#include <bsp/bsp.h>
+
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1) || MYNEWT_VAL(UART_2)
+#include <uart/uart.h>
+#include <uart_hal/uart_hal.h>
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf54l_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_uart1;
+static const struct nrf54l_uart_cfg os_bsp_uart1_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+};
+#endif
+#if MYNEWT_VAL(UART_2)
+static struct uart_dev os_bsp_uart2;
+static const struct nrf54l_uart_cfg os_bsp_uart2_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_2_PIN_CTS),
+};
+#endif
+
+static void
+nrf54l_periph_create_timers(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(OS_CPUTIME_TIMER_NUM) >= 0
+ rc = os_cputime_init(MYNEWT_VAL(OS_CPUTIME_FREQ));
+ assert(rc == 0);
+#endif
+}
+
+static void
+nrf54l_periph_create_uart(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create(&os_bsp_uart0.ud_dev, "uart0", OS_DEV_INIT_PRIMARY, 0,
+ uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create(&os_bsp_uart1.ud_dev, "uart1", OS_DEV_INIT_PRIMARY, 1,
+ uart_hal_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_2)
+ rc = os_dev_create(&os_bsp_uart2.ud_dev, "uart2", OS_DEV_INIT_PRIMARY, 2,
+ uart_hal_init, (void *)&os_bsp_uart2_cfg);
+ assert(rc == 0);
+#endif
+}
+
+void
+nrf54l_periph_create(void)
+{
+ nrf54l_periph_create_timers();
+ nrf54l_periph_create_uart();
+}
diff --git a/hw/mcu/nordic/nrf54lxx/src/system_nrf54.c b/hw/mcu/nordic/nrf54lxx/src/system_nrf54.c
new file mode 100644
index 0000000..bb43db4
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/src/system_nrf54.c
@@ -0,0 +1,205 @@
+/*
+
+Copyright (c) 2009-2024 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+ be copied into the application project folder prior to its use! */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "nrf54l_erratas.h"
+#include "system_nrf54l.h"
+#include "system_nrf54l_approtect.h"
+#include "system_config_sau.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_DEFAULT (64000000ul)
+
+/* Trace configuration */
+#define TRACE_TRACECLK_PIN (6ul)
+#define TRACE_TRACEDATA0_PIN (7ul)
+#define TRACE_TRACEDATA1_PIN (8ul)
+#define TRACE_TRACEDATA2_PIN (9ul)
+#define TRACE_TRACEDATA3_PIN (10ul)
+
+#define TRACE_PIN_CLEAR (~(GPIO_PIN_CNF_CTRLSEL_Msk | GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk))
+
+#define TRACE_PIN_CONFIG ((GPIO_PIN_CNF_DRIVE0_E0 << GPIO_PIN_CNF_DRIVE0_Pos) \
+ | (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_Pos))
+
+
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT;
+#elif defined ( __ICCARM__ )
+__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+ switch(NRF_OSCILLATORS->PLL.CURRENTFREQ)
+ {
+ case OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK64M:
+ SystemCoreClock = 64000000ul;
+ break;
+ case OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK128M:
+ SystemCoreClock = 128000000ul;
+ break;
+ }
+}
+
+void SystemInit(void)
+{
+#ifdef __CORTEX_M
+#ifndef NRF_SKIP_CLOCK_CONFIGURATION
+#if defined(NRF_CONFIG_CPU_FREQ_MHZ) && (NRF_CONFIG_CPU_FREQ_MHZ==64)
+ NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK64M;
+#elif defined(NRF_CONFIG_CPU_FREQ_MHZ) && (NRF_CONFIG_CPU_FREQ_MHZ==128)
+ NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK128M;
+#elif defined(NRF_CONFIG_CPU_FREQ_MHZ)
+#error "Illegal CPU frequency set"
+#else
+ NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK128M;
+#endif
+#endif
+
+#if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE)
+#ifndef NRF_SKIP_TAMPC_SETUP
+ nrf54l_handle_approtect();
+#endif
+#if defined(__FPU_PRESENT) && __FPU_PRESENT
+ /* Allow Non-Secure code to run FPU instructions.
+ * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
+ SCB->NSACR |= (3UL << 10ul);
+#endif
+
+#ifndef NRF_SKIP_SAU_CONFIGURATION
+ configure_default_sau();
+#endif
+
+#if !defined (NRF_DISABLE_FICR_TRIMCNF)
+ /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
+ until one ADDR is not initialized. */
+ uint32_t index = 0ul;
+ for (index = 0ul; index < FICR_TRIMCNF_MaxCount && NRF_FICR_NS->TRIMCNF[index].ADDR != 0xFFFFFFFFul && NRF_FICR_NS->TRIMCNF[index].ADDR != 0x00000000ul; index++) {
+#if defined ( __ICCARM__ )
+ /* IAR will complain about the order of volatile pointer accesses. */
+ #pragma diag_suppress=Pa082
+#endif
+ * ((volatile uint32_t*)NRF_FICR_NS->TRIMCNF[index].ADDR) = NRF_FICR_NS->TRIMCNF[index].DATA;
+#if defined ( __ICCARM__ )
+#pragma diag_default=Pa082
+#endif
+ }
+#endif
+
+ /* Device configuration for ES PDK */
+#if defined (NRF54L15_XXAA)
+ if (*((volatile uint32_t *)0x50120440) == 0x00ul) {
+ *((volatile uint32_t *)0x50120440) = 0xC8ul;
+ }
+#endif
+
+#if NRF54L_ERRATA_32_ENABLE_WORKAROUND
+ /* Workaround for Errata 32 */
+ if (nrf54l_errata_32())
+ {
+ if (*((volatile uint32_t *)0x00FFC334ul) <= 0x180A1D00ul){
+ *((volatile uint32_t *)0x50120640ul) = 0x1EA9E040ul;
+ }
+ }
+#endif
+
+#endif
+
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ * operations are not used in your code. */
+
+ /* Allow Non-Secure code to run FPU instructions.
+ * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
+ SCB->NSACR |= (3UL << 10ul);
+
+#if (__FPU_USED == 1ul)
+ SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul);
+ __DSB();
+ __ISB();
+#endif
+
+#if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE)
+#if defined(NRF_CONFIG_NFCT_PINS_AS_GPIOS)
+ NRF_NFCT_S->PADCONFIG = (NFCT_PADCONFIG_ENABLE_Disabled << NFCT_PADCONFIG_ENABLE_Pos);
+#endif
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+ Specification to see which one). */
+#if defined (ENABLE_SWO)
+ // Enable trace and debug
+ NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
+
+ // Configure trace port pads
+ NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR;
+
+ NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG;
+
+ // Configure trace port speed
+ NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2;
+#endif
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
+#if defined (ENABLE_TRACE)
+ // Enable trace and debug
+ NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
+
+ // Configure trace port pads
+ NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA1_PIN] &= TRACE_PIN_CLEAR;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA2_PIN] &= TRACE_PIN_CLEAR;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA3_PIN] &= TRACE_PIN_CLEAR;
+
+ NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA1_PIN] |= TRACE_PIN_CONFIG;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA2_PIN] |= TRACE_PIN_CONFIG;
+ NRF_P2_S->PIN_CNF[TRACE_TRACEDATA3_PIN] |= TRACE_PIN_CONFIG;
+
+ // Configure trace port speed
+ NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2;
+#endif
+#endif
+
+#if !defined(NRF_TRUSTZONE_NONSECURE) && !defined (NRF_SKIP_GLITCHDETECTOR_DISABLE)
+ /* Disable glitch detector */
+#if defined (GLITCHDET_GLITCHDETECTORS)
+ NRF_GLITCHDET_S->GLITCHDETECTOR.CONFIG = (GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Disable << GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Pos);
+#else
+ NRF_GLITCHDET_S->CONFIG = (GLITCHDET_CONFIG_ENABLE_Disable << GLITCHDET_CONFIG_ENABLE_Pos);
+#endif
+#endif
+#endif
+}
+
+/*lint --flb "Leave library region" */
diff --git a/hw/mcu/nordic/nrf54lxx/syscfg.yml b/hw/mcu/nordic/nrf54lxx/syscfg.yml
new file mode 100644
index 0000000..43a5e8e
--- /dev/null
+++ b/hw/mcu/nordic/nrf54lxx/syscfg.yml
@@ -0,0 +1,137 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_TARGET:
+ description: >
+ Specifies target MCU.
+ value: nRF54L15
+ restrictions:
+ - $notnull
+ choices:
+ - nRF54L15
+
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 1
+
+ MCU_DCDC_ENABLED:
+ description: >
+ Specifies whether or not to enable DC/DC regulator. This requires
+ external circuitry so is defined to be zero by default and
+ expected to be overridden by the BSP.
+ value: 0
+
+ MCU_LFCLK_SOURCE:
+ description: >
+ Selected source for low frequency clock (LFCLK).
+ value:
+ choices:
+ - LFRC # 32.768 kHz RC oscillator
+ - LFXO # 32.768 kHz crystal oscillator
+ - LFSYNTH # 32.768 kHz synthesized from HFCLK
+
+ MCU_GPIO_USE_PORT_EVENT:
+ description: >
+ When enabled, hal_gpio will use GPIOTE PORT event instead of PIN
+ events for interrupts. This mode may be less accurate (i.e. pulse
+ length needs to be longer in order to be detected) but it reduces
+ power consumption since it does not require HFCLK to be running.
+ Refer to nRF54lxx Product Specification document for more details.
+ value: 0
+
+ MCU_DEBUG_IGNORE_BKPT:
+ description: >
+ When enabled, asm(bkpt) will be ignored. If not set, it will hit
+ the breakpoint wherever it gets called, For example, reset and crash
+ value: 0
+
+# MCU peripherals definitions
+ UART_0:
+ description: 'Enable nRF54Lxx UART20'
+ value: 1
+ UART_0_PIN_TX:
+ description: 'TX pin for UART20'
+ value: ''
+ UART_0_PIN_RX:
+ description: 'RX pin for UART20'
+ value: ''
+ UART_0_PIN_RTS:
+ description: 'RTS pin for UART20'
+ value: -1
+ UART_0_PIN_CTS:
+ description: 'CTS pin for UART20'
+ value: -1
+
+ UART_1:
+ description: 'Enable nRF54Lxx UART21'
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for UART21'
+ value: ''
+ UART_1_PIN_RX:
+ description: 'RX pin for UART21'
+ value: ''
+ UART_1_PIN_RTS:
+ description: 'RTS pin for UART21'
+ value: -1
+ UART_1_PIN_CTS:
+ description: 'CTS pin for UART21'
+ value: -1
+
+ UART_2:
+ description: 'Enable nRF54Lxx UART22'
+ value: 0
+ UART_2_PIN_TX:
+ description: 'TX pin for UART22'
+ value: ''
+ UART_2_PIN_RX:
+ description: 'RX pin for UART22'
+ value: ''
+ UART_2_PIN_RTS:
+ description: 'RTS pin for UART22'
+ value: -1
+ UART_2_PIN_CTS:
+ description: 'CTS pin for UART22'
+ value: -1
+
+ TIMER_0:
+ description: 'Enable nRF54Lxx Timer 20'
+ value: 1
+ TIMER_1:
+ description: 'Enable nRF54Lxx Timer 21'
+ value: 0
+ TIMER_2:
+ description: 'Enable nRF54Lxx Timer 22'
+ value: 0
+ TIMER_3:
+ description: 'Enable nRF54Lxx Timer 23'
+ value: 0
+ TIMER_4:
+ description: 'Enable nRF54Lxx Timer 24'
+ value: 0
+
+syscfg.vals:
+ OS_TICKS_PER_SEC: 1000
+
+syscfg.restrictions:
+ - "!UART_0 || (UART_0_PIN_TX != -1 && UART_0_PIN_RX != -1)"
+ - "!UART_1 || (UART_1_PIN_TX != -1 && UART_1_PIN_RX != -1)"
+ - "!UART_2 || (UART_2_PIN_TX != -1 && UART_2_PIN_RX != -1)"
diff --git a/hw/mcu/nordic/nrf_common/src/hal_flash.c b/hw/mcu/nordic/nrf_common/src/hal_flash.c
index be65f2b..1397e63 100644
--- a/hw/mcu/nordic/nrf_common/src/hal_flash.c
+++ b/hw/mcu/nordic/nrf_common/src/hal_flash.c
@@ -17,6 +17,8 @@
* under the License.
*/
+/* XXX: nrfx nvmc driver does not support NRF54 devices yet */
+#ifndef NRF54L15_XXAA
#include <string.h>
#include <assert.h>
#include <hal/hal_flash_int.h>
@@ -114,3 +116,4 @@
{
return 0;
}
+#endif
diff --git a/hw/mcu/nordic/nrf_common/src/hal_gpio.c b/hw/mcu/nordic/nrf_common/src/hal_gpio.c
index 2cc633f..9d1e266 100644
--- a/hw/mcu/nordic/nrf_common/src/hal_gpio.c
+++ b/hw/mcu/nordic/nrf_common/src/hal_gpio.c
@@ -47,6 +47,9 @@
#define GPIOTE_IRQn GPIOTE1_IRQn
#define GPIOTE GPIOTE1
#endif
+#elif defined(NRF54L15_XXAA)
+#define GPIOTE_IRQn GPIOTE20_IRQn
+#define NRF_GPIOTE NRF_GPIOTE20
#endif
/* Storage for GPIO callbacks. */
