tree b139b892d70af30e10efe1f5ee8a3b5abdc7ac81
parent 1a37d5c692c85db20d0c61e2f72659f3724e125e
author Jiajun Wang <jjwang@linkedin.com> 1622675630 -0700
committer GitHub <noreply@github.com> 1622675630 -0700
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Gracefully handle interruptions in the Helix logic. (#1779)

This PR aims to address the problem that the interrupt signal is swallowed by the catch logic so the thread is not really interrupted. This may cause leakage or race conditions.