bthread: implement lock-free AtomicInteger128 for RISC-V (#3355)

* bthread: implement lock-free AtomicInteger128 for RISC-V

Replace mutex-based fallback with seqlock implementation for RISC-V
platform. This brings RISC-V in line with x86 (SSE) and ARM (NEON)
lock-free implementations.

Seqlock algorithm:
- Reader: read sequence, read data, verify sequence, retry if stale
- Writer: increment sequence, write data, increment sequence
- All memory accesses use fence instructions for ordering

Performance improvement:
- bthread_start_urgent latency: 1.5-2% reduction
- adding_func throughput: 25% improvement (541ns vs 722ns)

Signed-off-by: Xiaofei Gong <gongxiaofei24@iscas.ac.cn>
Signed-off-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>

* fix: correct RISC-V inline assembly constraints for AtomicInteger128

- Use "m" (input) for ld instructions reading memory
- Use "=m" (output) for sd instructions writing memory
- Swap operand order in sd templates to match RISC-V syntax (register, memory)

The previous "+m" constraints in input operand positions caused compilation
errors on RISC-V. This fix ensures proper constraint usage:
- ld: memory is input "m", register is output "=r"
- sd: register is input "r", memory is output "=m"

Signed-off-by: Xiaofei Gong <gongxiaofei24@iscas.ac.cn>
Signed-off-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>

---------

Signed-off-by: Xiaofei Gong <gongxiaofei24@iscas.ac.cn>
Signed-off-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>